Changeset abea02a8 in rtems


Ignore:
Timestamp:
Jul 3, 2016, 7:30:20 AM (4 years ago)
Author:
Pavel Pisa <pisa@…>
Branches:
5, master
Children:
d4316537
Parents:
0e507d55
git-author:
Pavel Pisa <pisa@…> (07/03/16 07:30:20)
git-committer:
Pavel Pisa <pisa@…> (07/04/16 13:55:57)
Message:

bsp/arm: Report correct maximal cache line length for ARM Cortex-A + L2C-310.

File:
1 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/arm/shared/arm-l2c-310/cache_.h

    r0e507d55 rabea02a8  
    7373#define CPU_DATA_CACHE_ALIGNMENT ARM_CACHE_L1_CPU_DATA_ALIGNMENT
    7474#define CPU_INSTRUCTION_CACHE_ALIGNMENT ARM_CACHE_L1_CPU_INSTRUCTION_ALIGNMENT
     75#if defined(__ARM_ARCH_7A__)
     76/* Some/many ARM Cortex-A cores have L1 data line lenght 64 bytes */
     77#define CPU_MAXIMAL_CACHE_ALIGNMENT 64
     78#endif
    7579#define CPU_CACHE_SUPPORT_PROVIDES_RANGE_FUNCTIONS \
    7680  ARM_CACHE_L1_CPU_SUPPORT_PROVIDES_RANGE_FUNCTIONS
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