Changeset abc2164 in rtems for bsps/powerpc/include


Ignore:
Timestamp:
Feb 7, 2018, 8:23:49 AM (3 years ago)
Author:
Sebastian Huber <sebastian.huber@…>
Branches:
5, master
Children:
9ace2648
Parents:
18f285c
Message:

bsps/powerpc: Fix redefinitions

Location:
bsps/powerpc/include/libcpu
Files:
2 edited

Legend:

Unmodified
Added
Removed
  • bsps/powerpc/include/libcpu/raw_exception.h

    r18f285c rabc2164  
    5555#define ASM_MEBREAK_VECTOR      0x1E
    5656#define ASM_NMEBREAK_VECTOR     0x1F
    57 
    58 #define LAST_VALID_EXC          ASM_NMEBREAK_VECTOR
    5957
    6058#ifndef ASM
  • bsps/powerpc/include/libcpu/vectors.h

    r18f285c rabc2164  
    2020#define _LIBCPU_VECTORS_H
    2121
     22#include <bsp/vectors.h>
    2223
    2324/*
     
    2627#define NUM_EXCEPTIONS          0x20
    2728
    28 /*
    29  * The callee (high level exception code written in C)
    30  * will store the Link Registers (return address) at entry r1 + 4 !!!.
    31  * So let room for it!!!.
    32  */
    33 #define LINK_REGISTER_CALLEE_UPDATE_ROOM 4
    34 #define SRR0_FRAME_OFFSET 8
    35 #define SRR1_FRAME_OFFSET 12
    36 #define EXCEPTION_NUMBER_OFFSET 16
    37 #define EXC_CR_OFFSET 20
    38 #define EXC_CTR_OFFSET 24
    39 #define EXC_XER_OFFSET 28
    40 #define EXC_LR_OFFSET 32
    41 #define GPR0_OFFSET 36
    42 #define GPR1_OFFSET 40
    43 #define GPR2_OFFSET 44
    44 #define GPR3_OFFSET 48
    45 #define GPR4_OFFSET 52
    46 #define GPR5_OFFSET 56
    47 #define GPR6_OFFSET 60
    48 #define GPR7_OFFSET 64
    49 #define GPR8_OFFSET 68
    50 #define GPR9_OFFSET 72
    51 #define GPR10_OFFSET 76
    52 #define GPR11_OFFSET 80
    53 #define GPR12_OFFSET 84
    54 #define GPR13_OFFSET 88
    55 #define GPR14_OFFSET 92
    56 #define GPR15_OFFSET 96
    57 #define GPR16_OFFSET 100
    58 #define GPR17_OFFSET 104
    59 #define GPR18_OFFSET 108
    60 #define GPR19_OFFSET 112
    61 #define GPR20_OFFSET 116
    62 #define GPR21_OFFSET 120
    63 #define GPR22_OFFSET 124
    64 #define GPR23_OFFSET 128
    65 #define GPR24_OFFSET 132
    66 #define GPR25_OFFSET 136
    67 #define GPR26_OFFSET 140
    68 #define GPR27_OFFSET 144
    69 #define GPR28_OFFSET 148
    70 #define GPR29_OFFSET 152
    71 #define GPR30_OFFSET 156
    72 #define GPR31_OFFSET 160
    73 /*
    74  * maintain the EABI requested 8 bytes aligment
    75  * As SVR4 ABI requires 16, make it 16 (as some
    76  * exception may need more registers to be processed...)
    77  */
    78 #define    EXCEPTION_FRAME_END 176
    79 
    8029#ifndef ASM
    81 
    82 #include <rtems.h>
    8330
    8431/*
     
    9138
    9239typedef void rtems_exception_handler_t (CPU_Exception_frame* excPtr);
    93 /*DEBUG typedef rtems_exception_handler_t cpuExcHandlerType; */
    9440
    9541/*
     
    10753extern rtems_exception_handler_t* exception_handler_table[NUM_EXCEPTIONS];
    10854
    109 /* for compatability -- XXX remove */
    110 typedef rtems_exception_handler_t *cpuExcHandlerType;
    111 extern cpuExcHandlerType *globalExceptHdl;
    112 
    11355#endif /* ASM */
    11456
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