Index: bsps/x86_64/amd64/config/amd64.cfg
===================================================================
--- bsps/x86_64/amd64/config/amd64.cfg	(revision 382d6537df61d1783985e395b4418324cad1f324)
+++ bsps/x86_64/amd64/config/amd64.cfg	(revision ab971bf5e37a057432c267175ddf12d6799a2b35)
@@ -12,2 +12,5 @@
 # larger than their optimized container sizes.
 CPU_CFLAGS += -mcmodel=large
+CPU_CFLAGS += -Werror=return-type
+
+LDFLAGS = -Wl,--gc-sections
Index: cpukit/score/cpu/x86_64/headers.am
===================================================================
--- cpukit/score/cpu/x86_64/headers.am	(revision 382d6537df61d1783985e395b4418324cad1f324)
+++ cpukit/score/cpu/x86_64/headers.am	(revision ab971bf5e37a057432c267175ddf12d6799a2b35)
@@ -12,4 +12,5 @@
 include_rtems_score_HEADERS =
 include_rtems_score_HEADERS += include/rtems/score/cpu.h
+include_rtems_score_HEADERS += include/rtems/score/cpu_asm.h
 include_rtems_score_HEADERS += include/rtems/score/cpuatomic.h
 include_rtems_score_HEADERS += include/rtems/score/cpuimpl.h
Index: cpukit/score/cpu/x86_64/include/rtems/asm.h
===================================================================
--- cpukit/score/cpu/x86_64/include/rtems/asm.h	(revision 382d6537df61d1783985e395b4418324cad1f324)
+++ cpukit/score/cpu/x86_64/include/rtems/asm.h	(revision ab971bf5e37a057432c267175ddf12d6799a2b35)
@@ -85,4 +85,14 @@
 #define r15 REG (r15)
 
+/*
+ * Order of register usage for function arguments as per the calling convention
+ */
+#define REG_ARG0 rdi
+#define REG_ARG1 rsi
+#define REG_ARG2 rdx
+#define REG_ARG3 rcx
+#define REG_ARG4 r8
+#define REG_ARG5 r9
+
 // XXX: eax, ax, etc., segment registers
 
Index: cpukit/score/cpu/x86_64/include/rtems/score/cpu.h
===================================================================
--- cpukit/score/cpu/x86_64/include/rtems/score/cpu.h	(revision 382d6537df61d1783985e395b4418324cad1f324)
+++ cpukit/score/cpu/x86_64/include/rtems/score/cpu.h	(revision ab971bf5e37a057432c267175ddf12d6799a2b35)
@@ -41,4 +41,5 @@
 
 #include <rtems/score/basedefs.h>
+#include <rtems/score/cpu_asm.h>
 #include <rtems/score/x86_64.h>
 
@@ -55,5 +56,5 @@
 #define CPU_STACK_GROWS_UP               FALSE
 
-#define CPU_STRUCTURE_ALIGNMENT __attribute__((aligned ( 64 )))
+#define CPU_STRUCTURE_ALIGNMENT RTEMS_ALIGNED(64)
 #define CPU_CACHE_LINE_BYTES 64
 #define CPU_MODES_INTERRUPT_MASK   0x00000001
@@ -105,5 +106,5 @@
 } CPU_Interrupt_frame;
 
-#endif /* ASM */
+#endif /* !ASM */
 
 
Index: cpukit/score/cpu/x86_64/include/rtems/score/cpu_asm.h
===================================================================
--- cpukit/score/cpu/x86_64/include/rtems/score/cpu_asm.h	(revision ab971bf5e37a057432c267175ddf12d6799a2b35)
+++ cpukit/score/cpu/x86_64/include/rtems/score/cpu_asm.h	(revision ab971bf5e37a057432c267175ddf12d6799a2b35)
@@ -0,0 +1,50 @@
+/*
+ * Copyright (c) 2018.
+ * Amaan Cheval <amaan.cheval@gmail.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#ifndef _RTEMS_SCORE_CPU_ASM_H
+#define _RTEMS_SCORE_CPU_ASM_H
+
+#if !ASM
+
+#include <rtems/score/basedefs.h>
+
+RTEMS_INLINE_ROUTINE uint8_t inport_byte(uint16_t port)
+{
+  uint8_t ret;
+  __asm__ volatile ( "inb %1, %0"
+                     : "=a" (ret)
+                     : "Nd" (port) );
+  return ret;
+}
+
+RTEMS_INLINE_ROUTINE void outport_byte(uint16_t port, uint8_t val)
+{
+  __asm__ volatile ( "outb %0, %1" : : "a" (val), "Nd" (port) );
+}
+
+#endif /* !ASM */
+
+#endif
Index: cpukit/score/cpu/x86_64/include/rtems/score/cpuimpl.h
===================================================================
--- cpukit/score/cpu/x86_64/include/rtems/score/cpuimpl.h	(revision 382d6537df61d1783985e395b4418324cad1f324)
+++ cpukit/score/cpu/x86_64/include/rtems/score/cpuimpl.h	(revision ab971bf5e37a057432c267175ddf12d6799a2b35)
@@ -29,18 +29,4 @@
 #endif
 
-static inline uint8_t inport_byte(uint16_t port)
-{
-  uint8_t ret;
-  __asm__ volatile ( "inb %1, %0"
-                     : "=a" (ret)
-                     : "Nd" (port) );
-  return ret;
-}
-
-static inline void outport_byte(uint16_t port, uint8_t val)
-{
-  __asm__ volatile ( "outb %0, %1" : : "a" (val), "Nd" (port) );
-}
-
 RTEMS_INLINE_ROUTINE void _CPU_Context_volatile_clobber( uintptr_t pattern )
 {
@@ -69,5 +55,5 @@
 #endif
 
-#endif /* ASM */
+#endif /* !ASM */
 
 #endif /* _RTEMS_SCORE_CPUIMPL_H */
Index: cpukit/score/cpu/x86_64/include/rtems/score/x86_64.h
===================================================================
--- cpukit/score/cpu/x86_64/include/rtems/score/x86_64.h	(revision 382d6537df61d1783985e395b4418324cad1f324)
+++ cpukit/score/cpu/x86_64/include/rtems/score/x86_64.h	(revision ab971bf5e37a057432c267175ddf12d6799a2b35)
@@ -33,8 +33,17 @@
 
 #define CPU_NAME "x86-64"
-#define CPU_MODEL_NAME "XXX: x86-64 generic"
+#define CPU_MODEL_NAME "amd64"
 
-#define COM1_BASE_IO 0x3F8
+#define COM1_BASE_IO    0x3F8
 #define COM1_CLOCK_RATE (115200 * 16)
+
+#define EFLAGS_INTR_ENABLE 0x200
+
+#if DEBUG
+#define DBG_PRINTF(format, args...)             \
+  printf(format, ## args)
+#else
+#define DBG_PRINTF(format, args...)
+#endif
 
 #ifdef __cplusplus
Index: cpukit/score/cpu/x86_64/x86_64-context-switch.S
===================================================================
--- cpukit/score/cpu/x86_64/x86_64-context-switch.S	(revision 382d6537df61d1783985e395b4418324cad1f324)
+++ cpukit/score/cpu/x86_64/x86_64-context-switch.S	(revision ab971bf5e37a057432c267175ddf12d6799a2b35)
@@ -47,6 +47,8 @@
 PUBLIC(_CPU_Context_switch)
 
-.set RUNCONTEXT_ARG,   rdi                   /* save context argument */
-.set HEIRCONTEXT_ARG,  rsi                   /* restore context argument */
+/* save context argument */
+.set RUNCONTEXT_ARG,   REG_ARG0
+/* restore context argument */
+.set HEIRCONTEXT_ARG,  REG_ARG1
 
 SYM(_CPU_Context_switch):
@@ -89,5 +91,5 @@
 PUBLIC(_CPU_Context_restore)
 
-.set NEWCONTEXT_ARG,   rdi       /* context to restore argument */
+.set NEWCONTEXT_ARG,   REG_ARG0       /* context to restore argument */
 
 SYM(_CPU_Context_restore):
