Changeset aa7f8a1f in rtems
- Timestamp:
- 03/14/01 16:43:35 (21 years ago)
- Branches:
- 4.10, 4.11, 4.8, 4.9, 5, master
- Children:
- f849f3e
- Parents:
- acdb6558
- Files:
-
- 11 edited
Legend:
- Unmodified
- Added
- Removed
-
c/src/exec/score/cpu/mips/ChangeLog
racdb6558 raa7f8a1f 1 2001-03-14 Joel Sherrill <joel@OARcorp.com> 2 3 * cpu.c, rtems/score/cpu.h, rtems/score/mipstypes.h: 4 Removed unused variable _CPU_Thread_dispatch_pointer 5 and cleaned numerous comments. 6 1 7 2001-03-13 Joel Sherrill <joel@OARcorp.com> 2 8 -
c/src/exec/score/cpu/mips/cpu.c
racdb6558 raa7f8a1f 3 3 * 4 4 * Conversion to MIPS port by Alan Cudmore <alanc@linuxstart.com> and 5 * Joel Sherrill <joel@OARcorp.com>. 5 * Joel Sherrill <joel@OARcorp.com>. 6 * 7 * These changes made the code conditional on standard cpp predefines, 8 * merged the mips1 and mips3 code sequences as much as possible, 9 * and moved some of the assembly code to C. Alan did much of the 10 * initial analysis and rework. Joel took over from there and 11 * wrote the JMR3904 BSP so this could be tested. Joel also 12 * added the new interrupt vectoring support in libcpu and 13 * tried to better support the various interrupt controllers. 6 14 * 7 15 * Original MIP64ORION port by Craig Lebakken <craigl@transition.com> … … 19 27 * suitability of this software for any purpose. 20 28 * 21 * Derived from c/src/exec/score/cpu/no_cpu/cpu.c: 22 * 23 * COPYRIGHT (c) 1989-1999. 29 * COPYRIGHT (c) 1989-2001. 24 30 * On-Line Applications Research Corporation (OAR). 25 31 * … … 29 35 * 30 36 * $Id$ 31 */32 33 /*34 * Rather than deleting this, it is commented out to (hopefully) help35 * the submitter send updates.36 *37 * static char _sccsid[] = "@(#)cpu.c 08/20/96 1.5\n";38 37 */ 39 38 … … 58 57 ) 59 58 { 60 /*61 * The thread_dispatch argument is the address of the entry point62 * for the routine called at the end of an ISR once it has been63 * decided a context switch is necessary. On some compilation64 * systems it is difficult to call a high-level language routine65 * from assembly. This allows us to trick these systems.66 *67 * If you encounter this problem save the entry point in a CPU68 * dependent variable.69 */70 71 _CPU_Thread_dispatch_pointer = thread_dispatch;72 73 59 /* 74 60 * If there is not an easy way to initialize the FP context … … 81 67 82 68 _CPU_Table = *cpu_table; 83 84 69 } 85 70 … … 130 115 131 116 #elif __mips == 1 132 133 117 if ( (new_level & SR_IEC) == (sr & SR_IEC) ) 134 118 return; … … 149 133 * 150 134 * _CPU_ISR_install_raw_handler 135 * 136 * Input parameters: 137 * vector - interrupt vector number 138 * old_handler - former ISR for this vector number 139 * new_handler - replacement ISR for this vector number 140 * 141 * Output parameters: NONE 142 * 151 143 */ 152 144 … … 160 152 * This is where we install the interrupt handler into the "raw" interrupt 161 153 * table used by the CPU to dispatch interrupt handlers. 154 * 155 * Because all interrupts are vectored through the same exception handler 156 * this is not necessary on thi sport. 162 157 */ 163 /* Q: This will become necessary for Non IDT/Sim use...*/164 #if 0 /* not necessary */165 /* use IDT/Sim to set interrupt vector. Needed to co-exist with debugger. */166 add_ext_int_func( vector, new_handler );167 #endif168 158 } 169 159 … … 247 237 #endif 248 238 } 249 250 extern void mips_break( int error );251 252 #include <stdio.h>253 254 void mips_fatal_error( int error )255 {256 printf("fatal error 0x%x %d\n",error,error);257 mips_break( error );258 } -
c/src/exec/score/cpu/mips/rtems/score/cpu.h
racdb6558 raa7f8a1f 1 /* cpu.h 2 * 3 * This include file contains information pertaining to the IDT 4650 4 * processor. 5 * 6 * Author: Craig Lebakken <craigl@transition.com> 7 * 8 * COPYRIGHT (c) 1996 by Transition Networks Inc. 9 * 10 * To anyone who acknowledges that this file is provided "AS IS" 11 * without any express or implied warranty: 1 /* 2 * Mips CPU Dependent Header File 3 * 4 * Conversion to MIPS port by Alan Cudmore <alanc@linuxstart.com> and 5 * Joel Sherrill <joel@OARcorp.com>. 6 * 7 * These changes made the code conditional on standard cpp predefines, 8 * merged the mips1 and mips3 code sequences as much as possible, 9 * and moved some of the assembly code to C. Alan did much of the 10 * initial analysis and rework. Joel took over from there and 11 * wrote the JMR3904 BSP so this could be tested. Joel also 12 * added the new interrupt vectoring support in libcpu and 13 * tried to better support the various interrupt controllers. 14 * 15 * Original MIP64ORION port by Craig Lebakken <craigl@transition.com> 16 * COPYRIGHT (c) 1996 by Transition Networks Inc. 17 * 18 * To anyone who acknowledges that this file is provided "AS IS" 19 * without any express or implied warranty: 12 20 * permission to use, copy, modify, and distribute this file 13 21 * for any purpose is hereby granted without fee, provided that … … 19 27 * of this software for any purpose. 20 28 * 21 * Derived from c/src/exec/score/cpu/no_cpu/cpu.h: 22 * 23 * COPYRIGHT (c) 1989-1999. 29 * COPYRIGHT (c) 1989-2001. 24 30 * On-Line Applications Research Corporation (OAR). 25 31 * … … 30 36 * $Id$ 31 37 */ 32 /* @(#)cpu.h 08/29/96 1.7 */33 38 34 39 #ifndef __CPU_h … … 491 496 * can make it easier to invoke that routine at the end of the interrupt 492 497 * sequence (if a dispatch is necessary). 493 * /498 * 494 499 495 500 SCORE_EXTERN void (*_CPU_Thread_dispatch_pointer)(); 501 * 502 * NOTE: Not needed on this port. 503 */ 496 504 497 505 /* … … 741 749 */ 742 750 743 void mips_fatal_error ( int error );744 745 751 #define _CPU_Fatal_halt( _error ) \ 746 752 do { \ 747 753 unsigned int _level; \ 748 754 _CPU_ISR_Disable(_level); \ 749 mips_fatal_error(_error); \755 loop: goto loop; \ 750 756 } while (0) 751 757 752 /* end of Fatal Error manager macros */ 758 759 extern void mips_break( int error ); 753 760 754 761 /* Bitfield handler macros */ -
c/src/exec/score/cpu/mips/rtems/score/mips.h
racdb6558 raa7f8a1f 1 1 /* mips.h 2 2 * 3 * COPYRIGHT (c) 1989-200 0.3 * COPYRIGHT (c) 1989-2001. 4 4 * On-Line Applications Research Corporation (OAR). 5 5 * -
c/src/exec/score/cpu/mips/rtems/score/mipstypes.h
racdb6558 raa7f8a1f 1 1 /* mipstypes.h 2 2 * 3 * This include file contains type definitions pertaining to the IDT 46503 * This include file contains type definitions pertaining to the MIPS 4 4 * processor family. 5 5 * 6 * Author: Craig Lebakken <craigl@transition.com> 7 * 8 * COPYRIGHT (c) 1996 by Transition Networks Inc. 9 * 10 * To anyone who acknowledges that this file is provided "AS IS" 11 * without any express or implied warranty: 12 * permission to use, copy, modify, and distribute this file 13 * for any purpose is hereby granted without fee, provided that 14 * the above copyright notice and this notice appears in all 15 * copies, and that the name of Transition Networks not be used in 16 * advertising or publicity pertaining to distribution of the 17 * software without specific, written prior permission. 18 * Transition Networks makes no representations about the suitability 19 * of this software for any purpose. 20 * 21 * COPYRIGHT (c) 1989-1999. 6 * COPYRIGHT (c) 1989-2001. 22 7 * On-Line Applications Research Corporation (OAR). 23 8 * -
c/src/exec/score/cpu/mips/rtems/score/types.h
racdb6558 raa7f8a1f 1 1 /* mipstypes.h 2 2 * 3 * This include file contains type definitions pertaining to the IDT 46503 * This include file contains type definitions pertaining to the MIPS 4 4 * processor family. 5 5 * 6 * Author: Craig Lebakken <craigl@transition.com> 7 * 8 * COPYRIGHT (c) 1996 by Transition Networks Inc. 9 * 10 * To anyone who acknowledges that this file is provided "AS IS" 11 * without any express or implied warranty: 12 * permission to use, copy, modify, and distribute this file 13 * for any purpose is hereby granted without fee, provided that 14 * the above copyright notice and this notice appears in all 15 * copies, and that the name of Transition Networks not be used in 16 * advertising or publicity pertaining to distribution of the 17 * software without specific, written prior permission. 18 * Transition Networks makes no representations about the suitability 19 * of this software for any purpose. 20 * 21 * COPYRIGHT (c) 1989-1999. 6 * COPYRIGHT (c) 1989-2001. 22 7 * On-Line Applications Research Corporation (OAR). 23 8 * -
cpukit/score/cpu/mips/ChangeLog
racdb6558 raa7f8a1f 1 2001-03-14 Joel Sherrill <joel@OARcorp.com> 2 3 * cpu.c, rtems/score/cpu.h, rtems/score/mipstypes.h: 4 Removed unused variable _CPU_Thread_dispatch_pointer 5 and cleaned numerous comments. 6 1 7 2001-03-13 Joel Sherrill <joel@OARcorp.com> 2 8 -
cpukit/score/cpu/mips/cpu.c
racdb6558 raa7f8a1f 3 3 * 4 4 * Conversion to MIPS port by Alan Cudmore <alanc@linuxstart.com> and 5 * Joel Sherrill <joel@OARcorp.com>. 5 * Joel Sherrill <joel@OARcorp.com>. 6 * 7 * These changes made the code conditional on standard cpp predefines, 8 * merged the mips1 and mips3 code sequences as much as possible, 9 * and moved some of the assembly code to C. Alan did much of the 10 * initial analysis and rework. Joel took over from there and 11 * wrote the JMR3904 BSP so this could be tested. Joel also 12 * added the new interrupt vectoring support in libcpu and 13 * tried to better support the various interrupt controllers. 6 14 * 7 15 * Original MIP64ORION port by Craig Lebakken <craigl@transition.com> … … 19 27 * suitability of this software for any purpose. 20 28 * 21 * Derived from c/src/exec/score/cpu/no_cpu/cpu.c: 22 * 23 * COPYRIGHT (c) 1989-1999. 29 * COPYRIGHT (c) 1989-2001. 24 30 * On-Line Applications Research Corporation (OAR). 25 31 * … … 29 35 * 30 36 * $Id$ 31 */32 33 /*34 * Rather than deleting this, it is commented out to (hopefully) help35 * the submitter send updates.36 *37 * static char _sccsid[] = "@(#)cpu.c 08/20/96 1.5\n";38 37 */ 39 38 … … 58 57 ) 59 58 { 60 /*61 * The thread_dispatch argument is the address of the entry point62 * for the routine called at the end of an ISR once it has been63 * decided a context switch is necessary. On some compilation64 * systems it is difficult to call a high-level language routine65 * from assembly. This allows us to trick these systems.66 *67 * If you encounter this problem save the entry point in a CPU68 * dependent variable.69 */70 71 _CPU_Thread_dispatch_pointer = thread_dispatch;72 73 59 /* 74 60 * If there is not an easy way to initialize the FP context … … 81 67 82 68 _CPU_Table = *cpu_table; 83 84 69 } 85 70 … … 130 115 131 116 #elif __mips == 1 132 133 117 if ( (new_level & SR_IEC) == (sr & SR_IEC) ) 134 118 return; … … 149 133 * 150 134 * _CPU_ISR_install_raw_handler 135 * 136 * Input parameters: 137 * vector - interrupt vector number 138 * old_handler - former ISR for this vector number 139 * new_handler - replacement ISR for this vector number 140 * 141 * Output parameters: NONE 142 * 151 143 */ 152 144 … … 160 152 * This is where we install the interrupt handler into the "raw" interrupt 161 153 * table used by the CPU to dispatch interrupt handlers. 154 * 155 * Because all interrupts are vectored through the same exception handler 156 * this is not necessary on thi sport. 162 157 */ 163 /* Q: This will become necessary for Non IDT/Sim use...*/164 #if 0 /* not necessary */165 /* use IDT/Sim to set interrupt vector. Needed to co-exist with debugger. */166 add_ext_int_func( vector, new_handler );167 #endif168 158 } 169 159 … … 247 237 #endif 248 238 } 249 250 extern void mips_break( int error );251 252 #include <stdio.h>253 254 void mips_fatal_error( int error )255 {256 printf("fatal error 0x%x %d\n",error,error);257 mips_break( error );258 } -
cpukit/score/cpu/mips/rtems/score/cpu.h
racdb6558 raa7f8a1f 1 /* cpu.h 2 * 3 * This include file contains information pertaining to the IDT 4650 4 * processor. 5 * 6 * Author: Craig Lebakken <craigl@transition.com> 7 * 8 * COPYRIGHT (c) 1996 by Transition Networks Inc. 9 * 10 * To anyone who acknowledges that this file is provided "AS IS" 11 * without any express or implied warranty: 1 /* 2 * Mips CPU Dependent Header File 3 * 4 * Conversion to MIPS port by Alan Cudmore <alanc@linuxstart.com> and 5 * Joel Sherrill <joel@OARcorp.com>. 6 * 7 * These changes made the code conditional on standard cpp predefines, 8 * merged the mips1 and mips3 code sequences as much as possible, 9 * and moved some of the assembly code to C. Alan did much of the 10 * initial analysis and rework. Joel took over from there and 11 * wrote the JMR3904 BSP so this could be tested. Joel also 12 * added the new interrupt vectoring support in libcpu and 13 * tried to better support the various interrupt controllers. 14 * 15 * Original MIP64ORION port by Craig Lebakken <craigl@transition.com> 16 * COPYRIGHT (c) 1996 by Transition Networks Inc. 17 * 18 * To anyone who acknowledges that this file is provided "AS IS" 19 * without any express or implied warranty: 12 20 * permission to use, copy, modify, and distribute this file 13 21 * for any purpose is hereby granted without fee, provided that … … 19 27 * of this software for any purpose. 20 28 * 21 * Derived from c/src/exec/score/cpu/no_cpu/cpu.h: 22 * 23 * COPYRIGHT (c) 1989-1999. 29 * COPYRIGHT (c) 1989-2001. 24 30 * On-Line Applications Research Corporation (OAR). 25 31 * … … 30 36 * $Id$ 31 37 */ 32 /* @(#)cpu.h 08/29/96 1.7 */33 38 34 39 #ifndef __CPU_h … … 491 496 * can make it easier to invoke that routine at the end of the interrupt 492 497 * sequence (if a dispatch is necessary). 493 * /498 * 494 499 495 500 SCORE_EXTERN void (*_CPU_Thread_dispatch_pointer)(); 501 * 502 * NOTE: Not needed on this port. 503 */ 496 504 497 505 /* … … 741 749 */ 742 750 743 void mips_fatal_error ( int error );744 745 751 #define _CPU_Fatal_halt( _error ) \ 746 752 do { \ 747 753 unsigned int _level; \ 748 754 _CPU_ISR_Disable(_level); \ 749 mips_fatal_error(_error); \755 loop: goto loop; \ 750 756 } while (0) 751 757 752 /* end of Fatal Error manager macros */ 758 759 extern void mips_break( int error ); 753 760 754 761 /* Bitfield handler macros */ -
cpukit/score/cpu/mips/rtems/score/mips.h
racdb6558 raa7f8a1f 1 1 /* mips.h 2 2 * 3 * COPYRIGHT (c) 1989-200 0.3 * COPYRIGHT (c) 1989-2001. 4 4 * On-Line Applications Research Corporation (OAR). 5 5 * -
cpukit/score/cpu/mips/rtems/score/types.h
racdb6558 raa7f8a1f 1 1 /* mipstypes.h 2 2 * 3 * This include file contains type definitions pertaining to the IDT 46503 * This include file contains type definitions pertaining to the MIPS 4 4 * processor family. 5 5 * 6 * Author: Craig Lebakken <craigl@transition.com> 7 * 8 * COPYRIGHT (c) 1996 by Transition Networks Inc. 9 * 10 * To anyone who acknowledges that this file is provided "AS IS" 11 * without any express or implied warranty: 12 * permission to use, copy, modify, and distribute this file 13 * for any purpose is hereby granted without fee, provided that 14 * the above copyright notice and this notice appears in all 15 * copies, and that the name of Transition Networks not be used in 16 * advertising or publicity pertaining to distribution of the 17 * software without specific, written prior permission. 18 * Transition Networks makes no representations about the suitability 19 * of this software for any purpose. 20 * 21 * COPYRIGHT (c) 1989-1999. 6 * COPYRIGHT (c) 1989-2001. 22 7 * On-Line Applications Research Corporation (OAR). 23 8 *
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