Changeset aa7f8a1f in rtems


Ignore:
Timestamp:
Mar 14, 2001, 4:43:35 PM (19 years ago)
Author:
Joel Sherrill <joel.sherrill@…>
Branches:
4.10, 4.11, 4.8, 4.9, master
Children:
f849f3e
Parents:
acdb6558
Message:

2001-03-14 Joel Sherrill <joel@…>

  • cpu.c, rtems/score/cpu.h, rtems/score/mipstypes.h: Removed unused variable _CPU_Thread_dispatch_pointer and cleaned numerous comments.
Files:
11 edited

Legend:

Unmodified
Added
Removed
  • c/src/exec/score/cpu/mips/ChangeLog

    racdb6558 raa7f8a1f  
     12001-03-14      Joel Sherrill <joel@OARcorp.com>
     2
     3        * cpu.c, rtems/score/cpu.h, rtems/score/mipstypes.h:
     4        Removed unused variable _CPU_Thread_dispatch_pointer
     5        and cleaned numerous comments.
     6       
    172001-03-13      Joel Sherrill <joel@OARcorp.com>
    28
  • c/src/exec/score/cpu/mips/cpu.c

    racdb6558 raa7f8a1f  
    33 *
    44 *  Conversion to MIPS port by Alan Cudmore <alanc@linuxstart.com> and
    5  *           Joel Sherrill <joel@OARcorp.com>.
     5 *           Joel Sherrill <joel@OARcorp.com>.
     6 *
     7 *    These changes made the code conditional on standard cpp predefines,
     8 *    merged the mips1 and mips3 code sequences as much as possible,
     9 *    and moved some of the assembly code to C.  Alan did much of the
     10 *    initial analysis and rework.  Joel took over from there and
     11 *    wrote the JMR3904 BSP so this could be tested.  Joel also
     12 *    added the new interrupt vectoring support in libcpu and
     13 *    tried to better support the various interrupt controllers.
    614 *
    715 *  Original MIP64ORION port by Craig Lebakken <craigl@transition.com>
     
    1927 *             suitability of this software for any purpose.
    2028 *
    21  *  Derived from c/src/exec/score/cpu/no_cpu/cpu.c:
    22  *
    23  *  COPYRIGHT (c) 1989-1999.
     29 *  COPYRIGHT (c) 1989-2001.
    2430 *  On-Line Applications Research Corporation (OAR).
    2531 *
     
    2935 *
    3036 *  $Id$
    31  */
    32 
    33 /*
    34  *  Rather than deleting this, it is commented out to (hopefully) help
    35  *  the submitter send updates.
    36  *
    37  * static char _sccsid[] = "@(#)cpu.c 08/20/96     1.5\n";
    3837 */
    3938
     
    5857)
    5958{
    60   /*
    61    *  The thread_dispatch argument is the address of the entry point
    62    *  for the routine called at the end of an ISR once it has been
    63    *  decided a context switch is necessary.  On some compilation
    64    *  systems it is difficult to call a high-level language routine
    65    *  from assembly.  This allows us to trick these systems.
    66    *
    67    *  If you encounter this problem save the entry point in a CPU
    68    *  dependent variable.
    69    */
    70 
    71   _CPU_Thread_dispatch_pointer = thread_dispatch;
    72 
    7359  /*
    7460   *  If there is not an easy way to initialize the FP context
     
    8167
    8268  _CPU_Table = *cpu_table;
    83 
    8469}
    8570
     
    130115 
    131116#elif __mips == 1
    132 
    133117  if ( (new_level & SR_IEC) == (sr & SR_IEC) )
    134118    return;
     
    149133 *
    150134 *  _CPU_ISR_install_raw_handler
     135 *
     136 *  Input parameters:
     137 *    vector      - interrupt vector number
     138 *    old_handler - former ISR for this vector number
     139 *    new_handler - replacement ISR for this vector number
     140 *
     141 *  Output parameters:  NONE
     142 *
    151143 */
    152144 
     
    160152   *  This is where we install the interrupt handler into the "raw" interrupt
    161153   *  table used by the CPU to dispatch interrupt handlers.
     154   *
     155   *  Because all interrupts are vectored through the same exception handler
     156   *  this is not necessary on thi sport.
    162157   */
    163 /* Q: This will become necessary for Non IDT/Sim use...*/
    164 #if 0 /* not necessary */
    165 /* use IDT/Sim to set interrupt vector.  Needed to co-exist with debugger. */
    166    add_ext_int_func( vector, new_handler );
    167 #endif
    168158}
    169159
     
    247237#endif
    248238}
    249 
    250 extern void mips_break( int error );
    251 
    252 #include <stdio.h>
    253 
    254 void mips_fatal_error( int error )
    255 {
    256    printf("fatal error 0x%x %d\n",error,error);
    257    mips_break( error );
    258 }
  • c/src/exec/score/cpu/mips/rtems/score/cpu.h

    racdb6558 raa7f8a1f  
    1 /*  cpu.h
    2  *
    3  *  This include file contains information pertaining to the IDT 4650
    4  *  processor.
    5  *
    6  *  Author:     Craig Lebakken <craigl@transition.com>
    7  *
    8  *  COPYRIGHT (c) 1996 by Transition Networks Inc.
    9  *
    10  *  To anyone who acknowledges that this file is provided "AS IS"
    11  *  without any express or implied warranty:
     1/* 
     2 *  Mips CPU Dependent Header File
     3 * 
     4 *  Conversion to MIPS port by Alan Cudmore <alanc@linuxstart.com> and
     5 *           Joel Sherrill <joel@OARcorp.com>.
     6 * 
     7 *    These changes made the code conditional on standard cpp predefines,
     8 *    merged the mips1 and mips3 code sequences as much as possible,
     9 *    and moved some of the assembly code to C.  Alan did much of the
     10 *    initial analysis and rework.  Joel took over from there and
     11 *    wrote the JMR3904 BSP so this could be tested.  Joel also
     12 *    added the new interrupt vectoring support in libcpu and
     13 *    tried to better support the various interrupt controllers.
     14 *     
     15 *  Original MIP64ORION port by Craig Lebakken <craigl@transition.com>
     16 *           COPYRIGHT (c) 1996 by Transition Networks Inc.
     17 *
     18 *    To anyone who acknowledges that this file is provided "AS IS"
     19 *    without any express or implied warranty:
    1220 *      permission to use, copy, modify, and distribute this file
    1321 *      for any purpose is hereby granted without fee, provided that
     
    1927 *      of this software for any purpose.
    2028 *
    21  *  Derived from c/src/exec/score/cpu/no_cpu/cpu.h:
    22  *
    23  *  COPYRIGHT (c) 1989-1999.
     29 *  COPYRIGHT (c) 1989-2001.
    2430 *  On-Line Applications Research Corporation (OAR).
    2531 *
     
    3036 *  $Id$
    3137 */
    32 /* @(#)cpu.h       08/29/96     1.7 */
    3338
    3439#ifndef __CPU_h
     
    491496 *  can make it easier to invoke that routine at the end of the interrupt
    492497 *  sequence (if a dispatch is necessary).
    493  */
     498 *
    494499
    495500SCORE_EXTERN void           (*_CPU_Thread_dispatch_pointer)();
     501 *
     502 *  NOTE: Not needed on this port.
     503 */
    496504
    497505/*
     
    741749 */
    742750
    743 void mips_fatal_error ( int error );
    744 
    745751#define _CPU_Fatal_halt( _error ) \
    746752  do { \
    747753    unsigned int _level; \
    748754    _CPU_ISR_Disable(_level); \
    749     mips_fatal_error(_error); \
     755    loop: goto loop; \
    750756  } while (0)
    751757
    752 /* end of Fatal Error manager macros */
     758
     759extern void mips_break( int error );
    753760
    754761/* Bitfield handler macros */
  • c/src/exec/score/cpu/mips/rtems/score/mips.h

    racdb6558 raa7f8a1f  
    11/*  mips.h
    22 *
    3  *  COPYRIGHT (c) 1989-2000.
     3 *  COPYRIGHT (c) 1989-2001.
    44 *  On-Line Applications Research Corporation (OAR).
    55 *
  • c/src/exec/score/cpu/mips/rtems/score/mipstypes.h

    racdb6558 raa7f8a1f  
    11/*  mipstypes.h
    22 *
    3  *  This include file contains type definitions pertaining to the IDT 4650
     3 *  This include file contains type definitions pertaining to the MIPS
    44 *  processor family.
    55 *
    6  *  Author:     Craig Lebakken <craigl@transition.com>
    7  *
    8  *  COPYRIGHT (c) 1996 by Transition Networks Inc.
    9  *
    10  *  To anyone who acknowledges that this file is provided "AS IS"
    11  *  without any express or implied warranty:
    12  *      permission to use, copy, modify, and distribute this file
    13  *      for any purpose is hereby granted without fee, provided that
    14  *      the above copyright notice and this notice appears in all
    15  *      copies, and that the name of Transition Networks not be used in
    16  *      advertising or publicity pertaining to distribution of the
    17  *      software without specific, written prior permission.
    18  *      Transition Networks makes no representations about the suitability
    19  *      of this software for any purpose.
    20  *
    21  *  COPYRIGHT (c) 1989-1999.
     6 *  COPYRIGHT (c) 1989-2001.
    227 *  On-Line Applications Research Corporation (OAR).
    238 *
  • c/src/exec/score/cpu/mips/rtems/score/types.h

    racdb6558 raa7f8a1f  
    11/*  mipstypes.h
    22 *
    3  *  This include file contains type definitions pertaining to the IDT 4650
     3 *  This include file contains type definitions pertaining to the MIPS
    44 *  processor family.
    55 *
    6  *  Author:     Craig Lebakken <craigl@transition.com>
    7  *
    8  *  COPYRIGHT (c) 1996 by Transition Networks Inc.
    9  *
    10  *  To anyone who acknowledges that this file is provided "AS IS"
    11  *  without any express or implied warranty:
    12  *      permission to use, copy, modify, and distribute this file
    13  *      for any purpose is hereby granted without fee, provided that
    14  *      the above copyright notice and this notice appears in all
    15  *      copies, and that the name of Transition Networks not be used in
    16  *      advertising or publicity pertaining to distribution of the
    17  *      software without specific, written prior permission.
    18  *      Transition Networks makes no representations about the suitability
    19  *      of this software for any purpose.
    20  *
    21  *  COPYRIGHT (c) 1989-1999.
     6 *  COPYRIGHT (c) 1989-2001.
    227 *  On-Line Applications Research Corporation (OAR).
    238 *
  • cpukit/score/cpu/mips/ChangeLog

    racdb6558 raa7f8a1f  
     12001-03-14      Joel Sherrill <joel@OARcorp.com>
     2
     3        * cpu.c, rtems/score/cpu.h, rtems/score/mipstypes.h:
     4        Removed unused variable _CPU_Thread_dispatch_pointer
     5        and cleaned numerous comments.
     6       
    172001-03-13      Joel Sherrill <joel@OARcorp.com>
    28
  • cpukit/score/cpu/mips/cpu.c

    racdb6558 raa7f8a1f  
    33 *
    44 *  Conversion to MIPS port by Alan Cudmore <alanc@linuxstart.com> and
    5  *           Joel Sherrill <joel@OARcorp.com>.
     5 *           Joel Sherrill <joel@OARcorp.com>.
     6 *
     7 *    These changes made the code conditional on standard cpp predefines,
     8 *    merged the mips1 and mips3 code sequences as much as possible,
     9 *    and moved some of the assembly code to C.  Alan did much of the
     10 *    initial analysis and rework.  Joel took over from there and
     11 *    wrote the JMR3904 BSP so this could be tested.  Joel also
     12 *    added the new interrupt vectoring support in libcpu and
     13 *    tried to better support the various interrupt controllers.
    614 *
    715 *  Original MIP64ORION port by Craig Lebakken <craigl@transition.com>
     
    1927 *             suitability of this software for any purpose.
    2028 *
    21  *  Derived from c/src/exec/score/cpu/no_cpu/cpu.c:
    22  *
    23  *  COPYRIGHT (c) 1989-1999.
     29 *  COPYRIGHT (c) 1989-2001.
    2430 *  On-Line Applications Research Corporation (OAR).
    2531 *
     
    2935 *
    3036 *  $Id$
    31  */
    32 
    33 /*
    34  *  Rather than deleting this, it is commented out to (hopefully) help
    35  *  the submitter send updates.
    36  *
    37  * static char _sccsid[] = "@(#)cpu.c 08/20/96     1.5\n";
    3837 */
    3938
     
    5857)
    5958{
    60   /*
    61    *  The thread_dispatch argument is the address of the entry point
    62    *  for the routine called at the end of an ISR once it has been
    63    *  decided a context switch is necessary.  On some compilation
    64    *  systems it is difficult to call a high-level language routine
    65    *  from assembly.  This allows us to trick these systems.
    66    *
    67    *  If you encounter this problem save the entry point in a CPU
    68    *  dependent variable.
    69    */
    70 
    71   _CPU_Thread_dispatch_pointer = thread_dispatch;
    72 
    7359  /*
    7460   *  If there is not an easy way to initialize the FP context
     
    8167
    8268  _CPU_Table = *cpu_table;
    83 
    8469}
    8570
     
    130115 
    131116#elif __mips == 1
    132 
    133117  if ( (new_level & SR_IEC) == (sr & SR_IEC) )
    134118    return;
     
    149133 *
    150134 *  _CPU_ISR_install_raw_handler
     135 *
     136 *  Input parameters:
     137 *    vector      - interrupt vector number
     138 *    old_handler - former ISR for this vector number
     139 *    new_handler - replacement ISR for this vector number
     140 *
     141 *  Output parameters:  NONE
     142 *
    151143 */
    152144 
     
    160152   *  This is where we install the interrupt handler into the "raw" interrupt
    161153   *  table used by the CPU to dispatch interrupt handlers.
     154   *
     155   *  Because all interrupts are vectored through the same exception handler
     156   *  this is not necessary on thi sport.
    162157   */
    163 /* Q: This will become necessary for Non IDT/Sim use...*/
    164 #if 0 /* not necessary */
    165 /* use IDT/Sim to set interrupt vector.  Needed to co-exist with debugger. */
    166    add_ext_int_func( vector, new_handler );
    167 #endif
    168158}
    169159
     
    247237#endif
    248238}
    249 
    250 extern void mips_break( int error );
    251 
    252 #include <stdio.h>
    253 
    254 void mips_fatal_error( int error )
    255 {
    256    printf("fatal error 0x%x %d\n",error,error);
    257    mips_break( error );
    258 }
  • cpukit/score/cpu/mips/rtems/score/cpu.h

    racdb6558 raa7f8a1f  
    1 /*  cpu.h
    2  *
    3  *  This include file contains information pertaining to the IDT 4650
    4  *  processor.
    5  *
    6  *  Author:     Craig Lebakken <craigl@transition.com>
    7  *
    8  *  COPYRIGHT (c) 1996 by Transition Networks Inc.
    9  *
    10  *  To anyone who acknowledges that this file is provided "AS IS"
    11  *  without any express or implied warranty:
     1/* 
     2 *  Mips CPU Dependent Header File
     3 * 
     4 *  Conversion to MIPS port by Alan Cudmore <alanc@linuxstart.com> and
     5 *           Joel Sherrill <joel@OARcorp.com>.
     6 * 
     7 *    These changes made the code conditional on standard cpp predefines,
     8 *    merged the mips1 and mips3 code sequences as much as possible,
     9 *    and moved some of the assembly code to C.  Alan did much of the
     10 *    initial analysis and rework.  Joel took over from there and
     11 *    wrote the JMR3904 BSP so this could be tested.  Joel also
     12 *    added the new interrupt vectoring support in libcpu and
     13 *    tried to better support the various interrupt controllers.
     14 *     
     15 *  Original MIP64ORION port by Craig Lebakken <craigl@transition.com>
     16 *           COPYRIGHT (c) 1996 by Transition Networks Inc.
     17 *
     18 *    To anyone who acknowledges that this file is provided "AS IS"
     19 *    without any express or implied warranty:
    1220 *      permission to use, copy, modify, and distribute this file
    1321 *      for any purpose is hereby granted without fee, provided that
     
    1927 *      of this software for any purpose.
    2028 *
    21  *  Derived from c/src/exec/score/cpu/no_cpu/cpu.h:
    22  *
    23  *  COPYRIGHT (c) 1989-1999.
     29 *  COPYRIGHT (c) 1989-2001.
    2430 *  On-Line Applications Research Corporation (OAR).
    2531 *
     
    3036 *  $Id$
    3137 */
    32 /* @(#)cpu.h       08/29/96     1.7 */
    3338
    3439#ifndef __CPU_h
     
    491496 *  can make it easier to invoke that routine at the end of the interrupt
    492497 *  sequence (if a dispatch is necessary).
    493  */
     498 *
    494499
    495500SCORE_EXTERN void           (*_CPU_Thread_dispatch_pointer)();
     501 *
     502 *  NOTE: Not needed on this port.
     503 */
    496504
    497505/*
     
    741749 */
    742750
    743 void mips_fatal_error ( int error );
    744 
    745751#define _CPU_Fatal_halt( _error ) \
    746752  do { \
    747753    unsigned int _level; \
    748754    _CPU_ISR_Disable(_level); \
    749     mips_fatal_error(_error); \
     755    loop: goto loop; \
    750756  } while (0)
    751757
    752 /* end of Fatal Error manager macros */
     758
     759extern void mips_break( int error );
    753760
    754761/* Bitfield handler macros */
  • cpukit/score/cpu/mips/rtems/score/mips.h

    racdb6558 raa7f8a1f  
    11/*  mips.h
    22 *
    3  *  COPYRIGHT (c) 1989-2000.
     3 *  COPYRIGHT (c) 1989-2001.
    44 *  On-Line Applications Research Corporation (OAR).
    55 *
  • cpukit/score/cpu/mips/rtems/score/types.h

    racdb6558 raa7f8a1f  
    11/*  mipstypes.h
    22 *
    3  *  This include file contains type definitions pertaining to the IDT 4650
     3 *  This include file contains type definitions pertaining to the MIPS
    44 *  processor family.
    55 *
    6  *  Author:     Craig Lebakken <craigl@transition.com>
    7  *
    8  *  COPYRIGHT (c) 1996 by Transition Networks Inc.
    9  *
    10  *  To anyone who acknowledges that this file is provided "AS IS"
    11  *  without any express or implied warranty:
    12  *      permission to use, copy, modify, and distribute this file
    13  *      for any purpose is hereby granted without fee, provided that
    14  *      the above copyright notice and this notice appears in all
    15  *      copies, and that the name of Transition Networks not be used in
    16  *      advertising or publicity pertaining to distribution of the
    17  *      software without specific, written prior permission.
    18  *      Transition Networks makes no representations about the suitability
    19  *      of this software for any purpose.
    20  *
    21  *  COPYRIGHT (c) 1989-1999.
     6 *  COPYRIGHT (c) 1989-2001.
    227 *  On-Line Applications Research Corporation (OAR).
    238 *
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