Changeset a9d6c20 in rtems
- Timestamp:
- 11/19/14 11:23:02 (9 years ago)
- Branches:
- 4.11, 5, master
- Children:
- 13f1462f
- Parents:
- 957c075
- git-author:
- Sebastian Huber <sebastian.huber@…> (11/19/14 11:23:02)
- git-committer:
- Sebastian Huber <sebastian.huber@…> (11/20/14 09:30:27)
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
c/src/lib/libbsp/arm/shared/arm-l2c-310/cache_.h
r957c075 ra9d6c20 5 5 * 6 6 * @brief Cache definitions and functions. 7 * 7 * 8 8 * This file implements handling for the ARM L2C-310 cache controller 9 9 */ … … 479 479 * Please see this document for more information on these erratas */ 480 480 static bool l2c_310_cache_errata_is_applicable_753970( 481 void481 cache_l2c_310_rtl_release rtl_release 482 482 ) 483 483 { 484 volatile L2CC *l2cc = 485 (volatile L2CC *) BSP_ARM_L2C_310_BASE; 486 const cache_l2c_310_rtl_release RTL_RELEASE = 487 l2cc->cache_id & CACHE_L2C_310_L2CC_ID_RTL_MASK; 488 bool is_applicable = false; 489 490 switch( RTL_RELEASE ) { 484 bool is_applicable = false; 485 486 switch ( rtl_release ) { 491 487 case CACHE_L2C_310_RTL_RELEASE_R3_P3: 492 488 case CACHE_L2C_310_RTL_RELEASE_R3_P2: … … 496 492 case CACHE_L2C_310_RTL_RELEASE_R0_P0: 497 493 is_applicable = false; 498 break;494 break; 499 495 case CACHE_L2C_310_RTL_RELEASE_R3_P0: 500 496 is_applicable = true; 501 break;497 break; 502 498 default: 503 assert( RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P3 504 || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P2 505 || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P1 506 || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P0 507 || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R2_P0 508 || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R1_P0 509 || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R0_P0 ); 499 assert( 0 ); 510 500 break; 511 501 } … … 515 505 516 506 static bool l2c_310_cache_errata_is_applicable_727913( 517 void507 cache_l2c_310_rtl_release rtl_release 518 508 ) 519 509 { 520 volatile L2CC *l2cc = 521 (volatile L2CC *) BSP_ARM_L2C_310_BASE; 522 const cache_l2c_310_rtl_release RTL_RELEASE = 523 l2cc->cache_id & CACHE_L2C_310_L2CC_ID_RTL_MASK; 524 bool is_applicable = false; 525 526 switch( RTL_RELEASE ) { 510 bool is_applicable = false; 511 512 switch ( rtl_release ) { 527 513 case CACHE_L2C_310_RTL_RELEASE_R3_P3: 528 514 case CACHE_L2C_310_RTL_RELEASE_R3_P2: … … 532 518 case CACHE_L2C_310_RTL_RELEASE_R0_P0: 533 519 is_applicable = false; 534 break;520 break; 535 521 case CACHE_L2C_310_RTL_RELEASE_R3_P0: 536 522 is_applicable = true; 537 break;523 break; 538 524 default: 539 assert( RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P3 540 || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P2 541 || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P1 542 || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P0 543 || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R2_P0 544 || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R1_P0 545 || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R0_P0 ); 546 break; 547 } 548 525 assert( 0 ); 526 break; 527 } 528 549 529 return is_applicable; 550 530 } 551 531 552 532 static bool l2c_310_cache_errata_is_applicable_727914( 553 void533 cache_l2c_310_rtl_release rtl_release 554 534 ) 555 535 { 556 volatile L2CC *l2cc = 557 (volatile L2CC *) BSP_ARM_L2C_310_BASE; 558 const cache_l2c_310_rtl_release RTL_RELEASE = 559 l2cc->cache_id & CACHE_L2C_310_L2CC_ID_RTL_MASK; 560 bool is_applicable = false; 561 562 switch( RTL_RELEASE ) { 536 bool is_applicable = false; 537 538 switch ( rtl_release ) { 563 539 case CACHE_L2C_310_RTL_RELEASE_R3_P3: 564 540 case CACHE_L2C_310_RTL_RELEASE_R3_P2: … … 568 544 case CACHE_L2C_310_RTL_RELEASE_R0_P0: 569 545 is_applicable = false; 570 break;546 break; 571 547 case CACHE_L2C_310_RTL_RELEASE_R3_P0: 572 548 is_applicable = true; 573 break;549 break; 574 550 default: 575 assert( RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P3 576 || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P2 577 || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P1 578 || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P0 579 || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R2_P0 580 || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R1_P0 581 || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R0_P0 ); 582 break; 583 } 584 551 assert( 0 ); 552 break; 553 } 554 585 555 return is_applicable; 586 556 } 587 557 588 558 static bool l2c_310_cache_errata_is_applicable_727915( 589 void559 cache_l2c_310_rtl_release rtl_release 590 560 ) 591 561 { 592 volatile L2CC *l2cc = 593 (volatile L2CC *) BSP_ARM_L2C_310_BASE; 594 const cache_l2c_310_rtl_release RTL_RELEASE = 595 l2cc->cache_id & CACHE_L2C_310_L2CC_ID_RTL_MASK; 596 bool is_applicable = false; 597 598 switch( RTL_RELEASE ) { 562 bool is_applicable = false; 563 564 switch ( rtl_release ) { 599 565 case CACHE_L2C_310_RTL_RELEASE_R3_P3: 600 566 case CACHE_L2C_310_RTL_RELEASE_R3_P2: … … 603 569 case CACHE_L2C_310_RTL_RELEASE_R0_P0: 604 570 is_applicable = false; 605 break;571 break; 606 572 case CACHE_L2C_310_RTL_RELEASE_R3_P0: 607 573 case CACHE_L2C_310_RTL_RELEASE_R2_P0: 608 574 is_applicable = true; 609 break;575 break; 610 576 default: 611 assert( RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P3 612 || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P2 613 || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P1 614 || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P0 615 || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R2_P0 616 || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R1_P0 617 || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R0_P0 ); 618 break; 619 } 620 577 assert( 0 ); 578 break; 579 } 580 621 581 return is_applicable; 622 582 } 623 583 624 584 static bool l2c_310_cache_errata_is_applicable_729806( 625 void585 cache_l2c_310_rtl_release rtl_release 626 586 ) 627 587 { 628 volatile L2CC *l2cc = 629 (volatile L2CC *) BSP_ARM_L2C_310_BASE; 630 const cache_l2c_310_rtl_release RTL_RELEASE = 631 l2cc->cache_id & CACHE_L2C_310_L2CC_ID_RTL_MASK; 632 bool is_applicable = false; 633 634 switch( RTL_RELEASE ) { 588 bool is_applicable = false; 589 590 switch ( rtl_release ) { 635 591 case CACHE_L2C_310_RTL_RELEASE_R3_P3: 636 592 case CACHE_L2C_310_RTL_RELEASE_R3_P2: … … 639 595 case CACHE_L2C_310_RTL_RELEASE_R0_P0: 640 596 is_applicable = false; 641 break;597 break; 642 598 case CACHE_L2C_310_RTL_RELEASE_R3_P1: 643 599 case CACHE_L2C_310_RTL_RELEASE_R3_P0: 644 600 is_applicable = true; 645 break;601 break; 646 602 default: 647 assert( RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P3 648 || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P2 649 || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P1 650 || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P0 651 || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R2_P0 652 || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R1_P0 653 || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R0_P0 ); 654 break; 655 } 656 603 assert( 0 ); 604 break; 605 } 606 657 607 return is_applicable; 658 608 } 659 609 660 610 static bool l2c_310_cache_errata_is_applicable_729815( 661 void611 cache_l2c_310_rtl_release rtl_release 662 612 ) 663 613 { 664 volatile L2CC *l2cc = 665 (volatile L2CC *) BSP_ARM_L2C_310_BASE; 666 const cache_l2c_310_rtl_release RTL_RELEASE = 667 l2cc->cache_id & CACHE_L2C_310_L2CC_ID_RTL_MASK; 668 bool is_applicable = false; 669 670 switch( RTL_RELEASE ) { 614 bool is_applicable = false; 615 616 switch ( rtl_release ) { 671 617 case CACHE_L2C_310_RTL_RELEASE_R3_P3: 672 618 case CACHE_L2C_310_RTL_RELEASE_R1_P0: 673 619 case CACHE_L2C_310_RTL_RELEASE_R0_P0: 674 620 is_applicable = false; 675 break;621 break; 676 622 case CACHE_L2C_310_RTL_RELEASE_R3_P2: 677 623 case CACHE_L2C_310_RTL_RELEASE_R3_P1: … … 679 625 case CACHE_L2C_310_RTL_RELEASE_R2_P0: 680 626 is_applicable = true; 681 break;627 break; 682 628 default: 683 assert( RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P3 684 || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P2 685 || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P1 686 || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P0 687 || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R2_P0 688 || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R1_P0 689 || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R0_P0 ); 690 break; 691 } 692 629 assert( 0 ); 630 break; 631 } 632 693 633 return is_applicable; 694 634 } 695 635 696 636 static bool l2c_310_cache_errata_is_applicable_742884( 697 void637 cache_l2c_310_rtl_release rtl_release 698 638 ) 699 639 { 700 volatile L2CC *l2cc = 701 (volatile L2CC *) BSP_ARM_L2C_310_BASE; 702 const cache_l2c_310_rtl_release RTL_RELEASE = 703 l2cc->cache_id & CACHE_L2C_310_L2CC_ID_RTL_MASK; 704 bool is_applicable = false; 705 706 switch( RTL_RELEASE ) { 640 bool is_applicable = false; 641 642 switch ( rtl_release ) { 707 643 case CACHE_L2C_310_RTL_RELEASE_R3_P3: 708 644 case CACHE_L2C_310_RTL_RELEASE_R3_P2: … … 712 648 case CACHE_L2C_310_RTL_RELEASE_R0_P0: 713 649 is_applicable = false; 714 break;650 break; 715 651 case CACHE_L2C_310_RTL_RELEASE_R3_P1: 716 652 is_applicable = true; 717 break;653 break; 718 654 default: 719 assert( RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P3 720 || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P2 721 || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P1 722 || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P0 723 || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R2_P0 724 || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R1_P0 725 || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R0_P0 ); 726 break; 727 } 728 655 assert( 0 ); 656 break; 657 } 658 729 659 return is_applicable; 730 660 } 731 661 732 662 static bool l2c_310_cache_errata_is_applicable_752271( 733 void663 cache_l2c_310_rtl_release rtl_release 734 664 ) 735 665 { 736 volatile L2CC *l2cc = 737 (volatile L2CC *) BSP_ARM_L2C_310_BASE; 738 const cache_l2c_310_rtl_release RTL_RELEASE = 739 l2cc->cache_id & CACHE_L2C_310_L2CC_ID_RTL_MASK; 740 bool is_applicable = false; 741 742 switch( RTL_RELEASE ) { 666 bool is_applicable = false; 667 668 switch ( rtl_release ) { 743 669 case CACHE_L2C_310_RTL_RELEASE_R3_P3: 744 670 case CACHE_L2C_310_RTL_RELEASE_R3_P2: … … 747 673 case CACHE_L2C_310_RTL_RELEASE_R0_P0: 748 674 is_applicable = false; 749 break;675 break; 750 676 case CACHE_L2C_310_RTL_RELEASE_R3_P1: 751 677 case CACHE_L2C_310_RTL_RELEASE_R3_P0: 752 678 is_applicable = true; 753 break;679 break; 754 680 default: 755 assert( RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P3 756 || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P2 757 || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P1 758 || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P0 759 || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R2_P0 760 || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R1_P0 761 || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R0_P0 ); 762 break; 763 } 764 681 assert( 0 ); 682 break; 683 } 684 765 685 return is_applicable; 766 686 } 767 687 768 688 static bool l2c_310_cache_errata_is_applicable_765569( 769 void689 cache_l2c_310_rtl_release rtl_release 770 690 ) 771 691 { 772 volatile L2CC *l2cc = 773 (volatile L2CC *) BSP_ARM_L2C_310_BASE; 774 const cache_l2c_310_rtl_release RTL_RELEASE = 775 l2cc->cache_id & CACHE_L2C_310_L2CC_ID_RTL_MASK; 776 bool is_applicable = false; 777 778 switch( RTL_RELEASE ) { 692 bool is_applicable = false; 693 694 switch ( rtl_release ) { 695 case CACHE_L2C_310_RTL_RELEASE_R3_P3: 696 case CACHE_L2C_310_RTL_RELEASE_R3_P2: 697 case CACHE_L2C_310_RTL_RELEASE_R3_P1: 698 case CACHE_L2C_310_RTL_RELEASE_R3_P0: 699 case CACHE_L2C_310_RTL_RELEASE_R2_P0: 700 case CACHE_L2C_310_RTL_RELEASE_R1_P0: 701 case CACHE_L2C_310_RTL_RELEASE_R0_P0: 702 is_applicable = true; 703 break; 704 default: 705 assert( 0 ); 706 break; 707 } 708 709 return is_applicable; 710 } 711 712 static bool l2c_310_cache_errata_is_applicable_769419( 713 cache_l2c_310_rtl_release rtl_release 714 ) 715 { 716 bool is_applicable = false; 717 718 switch ( rtl_release ) { 719 case CACHE_L2C_310_RTL_RELEASE_R3_P3: 720 case CACHE_L2C_310_RTL_RELEASE_R3_P2: 721 is_applicable = false; 722 break; 723 case CACHE_L2C_310_RTL_RELEASE_R3_P1: 724 case CACHE_L2C_310_RTL_RELEASE_R3_P0: 725 case CACHE_L2C_310_RTL_RELEASE_R2_P0: 726 case CACHE_L2C_310_RTL_RELEASE_R1_P0: 727 case CACHE_L2C_310_RTL_RELEASE_R0_P0: 728 is_applicable = true; 729 break; 730 default: 731 assert( 0 ); 732 break; 733 } 734 735 return is_applicable; 736 } 737 738 static bool l2c_310_cache_errata_is_applicable_588369( 739 cache_l2c_310_rtl_release rtl_release 740 ) 741 { 742 bool is_applicable = false; 743 744 switch ( rtl_release ) { 745 case CACHE_L2C_310_RTL_RELEASE_R3_P3: 746 case CACHE_L2C_310_RTL_RELEASE_R3_P2: 747 case CACHE_L2C_310_RTL_RELEASE_R3_P1: 748 case CACHE_L2C_310_RTL_RELEASE_R3_P0: 749 case CACHE_L2C_310_RTL_RELEASE_R2_P0: 750 is_applicable = false; 751 break; 752 case CACHE_L2C_310_RTL_RELEASE_R1_P0: 753 case CACHE_L2C_310_RTL_RELEASE_R0_P0: 754 is_applicable = true; 755 break; 756 default: 757 assert( 0 ); 758 break; 759 } 760 761 return is_applicable; 762 } 763 764 #ifdef CACHE_ERRATA_CHECKS_FOR_IMPLEMENTED_ERRATAS 765 static bool l2c_310_cache_errata_is_applicable_754670( 766 cache_l2c_310_rtl_release rtl_release 767 ) 768 { 769 bool is_applicable = false; 770 771 switch ( rtl_release ) { 779 772 case CACHE_L2C_310_RTL_RELEASE_R3_P3: 780 773 case CACHE_L2C_310_RTL_RELEASE_R3_P2: … … 787 780 break; 788 781 default: 789 assert( RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P3 790 || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P2 791 || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P1 792 || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P0 793 || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R2_P0 794 || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R1_P0 795 || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R0_P0 ); 796 break; 797 } 798 782 assert( 0 ); 783 break; 784 } 785 799 786 return is_applicable; 800 787 } 801 802 static bool l2c_310_cache_errata_is_applicable_769419(803 void804 )805 {806 volatile L2CC *l2cc =807 (volatile L2CC *) BSP_ARM_L2C_310_BASE;808 const cache_l2c_310_rtl_release RTL_RELEASE =809 l2cc->cache_id & CACHE_L2C_310_L2CC_ID_RTL_MASK;810 bool is_applicable = false;811 812 switch( RTL_RELEASE ) {813 case CACHE_L2C_310_RTL_RELEASE_R3_P3:814 case CACHE_L2C_310_RTL_RELEASE_R3_P2:815 is_applicable = false;816 break;817 case CACHE_L2C_310_RTL_RELEASE_R3_P1:818 case CACHE_L2C_310_RTL_RELEASE_R3_P0:819 case CACHE_L2C_310_RTL_RELEASE_R2_P0:820 case CACHE_L2C_310_RTL_RELEASE_R1_P0:821 case CACHE_L2C_310_RTL_RELEASE_R0_P0:822 is_applicable = true;823 break;824 default:825 assert( RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P3826 || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P2827 || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P1828 || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P0829 || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R2_P0830 || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R1_P0831 || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R0_P0 );832 break;833 }834 835 return is_applicable;836 }837 838 static bool l2c_310_cache_errata_is_applicable_588369(839 void840 )841 {842 volatile L2CC *l2cc =843 (volatile L2CC *) BSP_ARM_L2C_310_BASE;844 const cache_l2c_310_rtl_release RTL_RELEASE =845 l2cc->cache_id & CACHE_L2C_310_L2CC_ID_RTL_MASK;846 bool is_applicable = false;847 848 switch( RTL_RELEASE ) {849 case CACHE_L2C_310_RTL_RELEASE_R3_P3:850 case CACHE_L2C_310_RTL_RELEASE_R3_P2:851 case CACHE_L2C_310_RTL_RELEASE_R3_P1:852 case CACHE_L2C_310_RTL_RELEASE_R3_P0:853 case CACHE_L2C_310_RTL_RELEASE_R2_P0:854 is_applicable = false;855 break;856 case CACHE_L2C_310_RTL_RELEASE_R1_P0:857 case CACHE_L2C_310_RTL_RELEASE_R0_P0:858 is_applicable = true;859 break;860 default:861 assert( RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P3862 || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P2863 || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P1864 || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P0865 || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R2_P0866 || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R1_P0867 || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R0_P0 );868 break;869 }870 871 return is_applicable;872 }873 874 #ifdef CACHE_ERRATA_CHECKS_FOR_IMPLEMENTED_ERRATAS875 static bool l2c_310_cache_errata_is_applicable_754670(876 void877 )878 {879 volatile L2CC *l2cc =880 (volatile L2CC *) BSP_ARM_L2C_310_BASE;881 const cache_l2c_310_rtl_release RTL_RELEASE =882 l2cc->cache_id & CACHE_L2C_310_L2CC_ID_RTL_MASK;883 bool is_applicable = false;884 885 switch( RTL_RELEASE ) {886 case CACHE_L2C_310_RTL_RELEASE_R3_P3:887 case CACHE_L2C_310_RTL_RELEASE_R3_P2:888 case CACHE_L2C_310_RTL_RELEASE_R3_P1:889 case CACHE_L2C_310_RTL_RELEASE_R3_P0:890 case CACHE_L2C_310_RTL_RELEASE_R2_P0:891 case CACHE_L2C_310_RTL_RELEASE_R1_P0:892 case CACHE_L2C_310_RTL_RELEASE_R0_P0:893 is_applicable = true;894 break;895 default:896 assert( RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P3897 || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P2898 || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P1899 || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P0900 || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R2_P0901 || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R1_P0902 || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R0_P0 );903 break;904 }905 906 return is_applicable;907 }908 788 #endif /* CACHE_ERRATA_CHECKS_FOR_IMPLEMENTED_ERRATAS */ 909 789 910 /* The common workaround for this erratum would be to add a 790 /* The common workaround for this erratum would be to add a 911 791 * data synchronization barrier to the beginning of the abort handler. 912 * But for RTEMS a call of the abort handler means a fatal condition anyway. 792 * But for RTEMS a call of the abort handler means a fatal condition anyway. 913 793 * So there is no need to handle this erratum */ 914 794 #define CACHE_ARM_ERRATA_775420_HANDLER() \ … … 916 796 } \ 917 797 918 static void l2c_310_cache_check_errata( void)798 static void l2c_310_cache_check_errata( cache_l2c_310_rtl_release rtl_release ) 919 799 { 920 800 /* This erratum gets handled within the sources */ 921 /* Unhandled erratum present: 588369 Errata 588369 says that clean + inv may 801 /* Unhandled erratum present: 588369 Errata 588369 says that clean + inv may 922 802 * keep the cache line if it was clean. See ARMs documentation on the erratum 923 803 * for a workaround */ 924 /* assert( ! l2c_310_cache_errata_is_applicable_588369( ) ); */925 926 /* Unhandled erratum present: 727913 Prefetch dropping feature can cause 927 * incorrect behavior when PL310 handles reads that cross cache line 804 /* assert( ! l2c_310_cache_errata_is_applicable_588369( rtl_release ) ); */ 805 806 /* Unhandled erratum present: 727913 Prefetch dropping feature can cause 807 * incorrect behavior when PL310 handles reads that cross cache line 928 808 * boundary */ 929 assert( ! l2c_310_cache_errata_is_applicable_727913( ) );930 931 /* Unhandled erratum present: 727914 Double linefill feature can cause 809 assert( ! l2c_310_cache_errata_is_applicable_727913( rtl_release ) ); 810 811 /* Unhandled erratum present: 727914 Double linefill feature can cause 932 812 * deadlock */ 933 assert( ! l2c_310_cache_errata_is_applicable_727914( ) );934 935 /* Unhandled erratum present: 727915 Background Clean and Invalidate by Way 813 assert( ! l2c_310_cache_errata_is_applicable_727914( rtl_release ) ); 814 815 /* Unhandled erratum present: 727915 Background Clean and Invalidate by Way 936 816 * operation can cause data corruption */ 937 assert( ! l2c_310_cache_errata_is_applicable_727915( ) );938 939 /* Unhandled erratum present: 729806 Speculative reads from the Cortex-A9 817 assert( ! l2c_310_cache_errata_is_applicable_727915( rtl_release ) ); 818 819 /* Unhandled erratum present: 729806 Speculative reads from the Cortex-A9 940 820 * MPCore processor can cause deadlock */ 941 assert( ! l2c_310_cache_errata_is_applicable_729806( ) );942 943 if( l2c_310_cache_errata_is_applicable_729815( ) )821 assert( ! l2c_310_cache_errata_is_applicable_729806( rtl_release ) ); 822 823 if( l2c_310_cache_errata_is_applicable_729815( rtl_release ) ) 944 824 { 945 825 volatile L2CC *l2cc = (volatile L2CC *) BSP_ARM_L2C_310_BASE; … … 947 827 assert( 0 == ( l2cc->aux_ctrl & CACHE_L2C_310_L2CC_AUX_HPSODRE_MASK ) ); 948 828 949 /* Erratum: 729815 The âHigh Priority for SO and Dev readsâ feature can 829 /* Erratum: 729815 The âHigh Priority for SO and Dev readsâ feature can 950 830 * cause Quality of Service issues to cacheable read transactions*/ 951 831 952 832 /* Conditions 953 833 This problem occurs when the following conditions are met: 954 1. Bit[10] âHigh Priority for SO and Dev reads enableâ of the PL310 834 1. Bit[10] âHigh Priority for SO and Dev reads enableâ of the PL310 955 835 Auxiliary Control Register is set to 1. 956 836 2. PL310 receives a cacheable read that misses in the L2 cache. 957 3. PL310 receives a continuous flow of Strongly Ordered or Device 837 3. PL310 receives a continuous flow of Strongly Ordered or Device 958 838 reads that take all address slots in the master interface. 959 839 Workaround 960 A workaround is only necessary in systems that are able to issue a 961 continuous flow of Strongly Ordered or Device reads. In such a case, 962 the workaround is to disable the âHigh Priority for SO and Dev readsâ 840 A workaround is only necessary in systems that are able to issue a 841 continuous flow of Strongly Ordered or Device reads. In such a case, 842 the workaround is to disable the âHigh Priority for SO and Dev readsâ 963 843 feature. This is the default behavior.*/ 964 844 } 965 966 /* Unhandled erratum present: 742884 Double linefill feature might introduce 845 846 /* Unhandled erratum present: 742884 Double linefill feature might introduce 967 847 * circular dependency and deadlock */ 968 assert( ! l2c_310_cache_errata_is_applicable_742884( ) );969 970 /* Unhandled erratum present: 752271 Double linefill feature can cause data 848 assert( ! l2c_310_cache_errata_is_applicable_742884( rtl_release ) ); 849 850 /* Unhandled erratum present: 752271 Double linefill feature can cause data 971 851 * corruption */ 972 assert( ! l2c_310_cache_errata_is_applicable_752271( ) );973 974 /* This erratum can not be worked around: 754670 A continuous write flow can 852 assert( ! l2c_310_cache_errata_is_applicable_752271( rtl_release ) ); 853 854 /* This erratum can not be worked around: 754670 A continuous write flow can 975 855 * stall a read targeting the same memory area 976 856 * But this erratum does not lead to any data corruption */ 977 857 /* assert( ! l2c_310_cache_errata_is_applicable_754670() ); */ 978 858 979 if( l2c_310_cache_errata_is_applicable_765569( ) )859 if( l2c_310_cache_errata_is_applicable_765569( rtl_release ) ) 980 860 { 981 861 volatile L2CC *l2cc = (volatile L2CC *) BSP_ARM_L2C_310_BASE; … … 986 866 == 23 ) ) ); 987 867 988 /* Unhandled erratum present: 765569 Prefetcher can cross 4KB boundary if 868 /* Unhandled erratum present: 765569 Prefetcher can cross 4KB boundary if 989 869 * offset is programmed with value 23 */ 990 870 991 871 /* Conditions 992 872 This problem occurs when the following conditions are met: 993 1. One of the Prefetch Enable bits (bits [29:28] of the Auxiliary or 873 1. One of the Prefetch Enable bits (bits [29:28] of the Auxiliary or 994 874 Prefetch Control Register) is set HIGH. 995 875 2. The prefetch offset bits are programmed with value 23 (5'b10111). … … 999 879 } 1000 880 1001 /* Unhandled erratum present: 769419 No automatic Store Buffer drain, 881 /* Unhandled erratum present: 769419 No automatic Store Buffer drain, 1002 882 * visibility of written data requires an explicit Cache */ 1003 assert( ! l2c_310_cache_errata_is_applicable_769419( ) );883 assert( ! l2c_310_cache_errata_is_applicable_769419( rtl_release ) ); 1004 884 } 1005 885 … … 1008 888 { 1009 889 volatile L2CC *l2cc = (volatile L2CC *) BSP_ARM_L2C_310_BASE; 1010 1011 if( l2c_310_cache_errata_is_applicable_753970() ) { 890 cache_l2c_310_rtl_release rtl_release = 891 l2cc->cache_id & CACHE_L2C_310_L2CC_ID_RTL_MASK; 892 893 if( l2c_310_cache_errata_is_applicable_753970( rtl_release ) ) { 1012 894 l2cc->dummy_cache_sync_reg = 0; 1013 895 } else { … … 1050 932 uint32_t block_end = 1051 933 CACHE_MIN( ADDR_LAST, adx + CACHE_MAX_LOCKING_BYTES ); 934 volatile L2CC *l2cc = (volatile L2CC *) BSP_ARM_L2C_310_BASE; 935 cache_l2c_310_rtl_release rtl_release = 936 l2cc->cache_id & CACHE_L2C_310_L2CC_ID_RTL_MASK; 1052 937 bool is_errata_588369_applicable = 1053 l2c_310_cache_errata_is_applicable_588369( );938 l2c_310_cache_errata_is_applicable_588369( rtl_release ); 1054 939 1055 940 rtems_interrupt_lock_acquire( &l2c_310_cache_lock, &lock_context ); … … 1186 1071 uint32_t way_size; 1187 1072 uint32_t num_ways; 1188 1073 1189 1074 way_size = (cache_type & CACHE_L2C_310_L2CC_TYPE_SIZE_D_WAYS_MASK) 1190 1075 >> CACHE_L2C_310_L2CC_TYPE_SIZE_D_WAYS_SHIFT; … … 1245 1130 { 1246 1131 volatile L2CC *l2cc = (volatile L2CC *) BSP_ARM_L2C_310_BASE; 1247 1132 cache_l2c_310_rtl_release rtl_release = 1133 l2cc->cache_id & CACHE_L2C_310_L2CC_ID_RTL_MASK; 1134 1248 1135 /* Only enable if L2CC is currently disabled */ 1249 1136 if( ( l2cc->ctrl & CACHE_L2C_310_L2CC_ENABLE_MASK ) == 0 ) { … … 1257 1144 case CACHE_L2C_310_L2CC_ID_PART_L310: 1258 1145 { 1259 const cache_l2c_310_rtl_release RTL_RELEASE =1260 l2cc->cache_id & CACHE_L2C_310_L2CC_ID_RTL_MASK;1261 1146 /* If this assertion fails, you have a release of the 1262 1147 * L2C-310 cache for which the l2c_310_cache_errata_is_applicable_ ... 1263 1148 * methods are not yet implemented. This means you will get incorrect 1264 1149 * errata handling */ 1265 assert( RTL_RELEASE== CACHE_L2C_310_RTL_RELEASE_R3_P31266 || RTL_RELEASE== CACHE_L2C_310_RTL_RELEASE_R3_P21267 || RTL_RELEASE== CACHE_L2C_310_RTL_RELEASE_R3_P11268 || RTL_RELEASE== CACHE_L2C_310_RTL_RELEASE_R3_P01269 || RTL_RELEASE== CACHE_L2C_310_RTL_RELEASE_R2_P01270 || RTL_RELEASE== CACHE_L2C_310_RTL_RELEASE_R1_P01271 || RTL_RELEASE== CACHE_L2C_310_RTL_RELEASE_R0_P0 );1150 assert( rtl_release == CACHE_L2C_310_RTL_RELEASE_R3_P3 1151 || rtl_release == CACHE_L2C_310_RTL_RELEASE_R3_P2 1152 || rtl_release == CACHE_L2C_310_RTL_RELEASE_R3_P1 1153 || rtl_release == CACHE_L2C_310_RTL_RELEASE_R3_P0 1154 || rtl_release == CACHE_L2C_310_RTL_RELEASE_R2_P0 1155 || rtl_release == CACHE_L2C_310_RTL_RELEASE_R1_P0 1156 || rtl_release == CACHE_L2C_310_RTL_RELEASE_R0_P0 ); 1272 1157 if ( l2cc->aux_ctrl & ( 1 << 16 ) ) { 1273 1158 ways = 16; … … 1325 1210 l2cc->int_clr = l2cc->int_raw_status; 1326 1211 1327 l2c_310_cache_check_errata( );1212 l2c_310_cache_check_errata( rtl_release ); 1328 1213 1329 1214 /* Enable the L2CC */ … … 1333 1218 } 1334 1219 1335 static inline void 1220 static inline void 1336 1221 cache_l2c_310_disable( void ) 1337 1222 { … … 1358 1243 } 1359 1244 1360 static inline void 1245 static inline void 1361 1246 _CPU_cache_enable_data( void ) 1362 1247 { … … 1364 1249 } 1365 1250 1366 static inline void 1251 static inline void 1367 1252 _CPU_cache_disable_data( void ) 1368 1253 { … … 1371 1256 } 1372 1257 1373 static inline void 1258 static inline void 1374 1259 _CPU_cache_enable_instruction( void ) 1375 1260 { … … 1377 1262 } 1378 1263 1379 static inline void 1264 static inline void 1380 1265 _CPU_cache_disable_instruction( void ) 1381 1266 { … … 1384 1269 } 1385 1270 1386 static inline void 1271 static inline void 1387 1272 _CPU_cache_flush_data_range( 1388 1273 const void *d_addr, … … 1391 1276 { 1392 1277 if ( n_bytes != 0 ) { 1393 arm_cache_l1_flush_data_range( 1278 arm_cache_l1_flush_data_range( 1394 1279 d_addr, 1395 1280 n_bytes … … 1402 1287 } 1403 1288 1404 static inline void 1289 static inline void 1405 1290 _CPU_cache_flush_entire_data( void ) 1406 1291 { … … 1409 1294 } 1410 1295 1411 static inline void 1412 _CPU_cache_invalidate_data_range( 1296 static inline void 1297 _CPU_cache_invalidate_data_range( 1413 1298 const void *addr_first, 1414 size_t n_bytes 1299 size_t n_bytes 1415 1300 ) 1416 1301 { … … 1423 1308 uint32_t block_end = 1424 1309 CACHE_MIN( ADDR_LAST, adx + CACHE_MAX_LOCKING_BYTES ); 1425 1310 1426 1311 /* We have to apply a lock. Thus we will operate only CACHE_MAX_LOCKING_BYTES 1427 1312 * at a time */ … … 1458 1343 } 1459 1344 1460 static inline void 1345 static inline void 1461 1346 _CPU_cache_invalidate_entire_data( void ) 1462 1347 { … … 1471 1356 } 1472 1357 1473 static inline void 1358 static inline void 1474 1359 _CPU_cache_freeze_data( void ) 1475 1360 { … … 1478 1363 } 1479 1364 1480 static inline void 1365 static inline void 1481 1366 _CPU_cache_unfreeze_data( void ) 1482 1367 { … … 1485 1370 } 1486 1371 1487 static inline void 1372 static inline void 1488 1373 _CPU_cache_invalidate_instruction_range( const void *i_addr, size_t n_bytes) 1489 1374 { … … 1491 1376 } 1492 1377 1493 static inline void 1378 static inline void 1494 1379 _CPU_cache_invalidate_entire_instruction( void ) 1495 1380 { … … 1497 1382 } 1498 1383 1499 static inline void 1384 static inline void 1500 1385 _CPU_cache_freeze_instruction( void ) 1501 1386 { … … 1504 1389 } 1505 1390 1506 static inline void 1391 static inline void 1507 1392 _CPU_cache_unfreeze_instruction( void ) 1508 1393 { … … 1515 1400 { 1516 1401 size_t size = 0; 1517 1402 1518 1403 switch( level ) 1519 1404 { … … 1536 1421 { 1537 1422 size_t size = 0; 1538 1423 1539 1424 switch( level ) 1540 1425 {
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