Changeset a9d6c20 in rtems


Ignore:
Timestamp:
Nov 19, 2014, 11:23:02 AM (5 years ago)
Author:
Sebastian Huber <sebastian.huber@…>
Branches:
4.11, master
Children:
13f1462f
Parents:
957c075
git-author:
Sebastian Huber <sebastian.huber@…> (11/19/14 11:23:02)
git-committer:
Sebastian Huber <sebastian.huber@…> (11/20/14 09:30:27)
Message:

bsps/arm: L2C 310 simplify and remove white space

File:
1 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/arm/shared/arm-l2c-310/cache_.h

    r957c075 ra9d6c20  
    55 *
    66 * @brief Cache definitions and functions.
    7  * 
     7 *
    88 * This file implements handling for the ARM L2C-310 cache controller
    99 */
     
    479479* Please see this document for more information on these erratas */
    480480static bool l2c_310_cache_errata_is_applicable_753970(
    481   void
     481  cache_l2c_310_rtl_release rtl_release
    482482)
    483483{
    484   volatile L2CC                  *l2cc          =
    485     (volatile L2CC *) BSP_ARM_L2C_310_BASE;
    486   const cache_l2c_310_rtl_release RTL_RELEASE   =
    487     l2cc->cache_id & CACHE_L2C_310_L2CC_ID_RTL_MASK;
    488   bool                            is_applicable = false;
    489  
    490   switch( RTL_RELEASE ) {
     484  bool is_applicable = false;
     485
     486  switch ( rtl_release ) {
    491487    case CACHE_L2C_310_RTL_RELEASE_R3_P3:
    492488    case CACHE_L2C_310_RTL_RELEASE_R3_P2:
     
    496492    case CACHE_L2C_310_RTL_RELEASE_R0_P0:
    497493      is_applicable = false;
    498     break;
     494      break;
    499495    case CACHE_L2C_310_RTL_RELEASE_R3_P0:
    500496      is_applicable = true;
    501     break;
     497      break;
    502498    default:
    503        assert(   RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P3
    504               || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P2
    505               || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P1
    506               || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P0
    507               || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R2_P0
    508               || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R1_P0
    509               || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R0_P0 );
     499      assert( 0 );
    510500      break;
    511501  }
     
    515505
    516506static bool l2c_310_cache_errata_is_applicable_727913(
    517   void
     507  cache_l2c_310_rtl_release rtl_release
    518508)
    519509{
    520   volatile L2CC                  *l2cc          =
    521     (volatile L2CC *) BSP_ARM_L2C_310_BASE;
    522   const cache_l2c_310_rtl_release RTL_RELEASE   =
    523     l2cc->cache_id & CACHE_L2C_310_L2CC_ID_RTL_MASK;
    524   bool                            is_applicable = false;
    525  
    526   switch( RTL_RELEASE ) {
     510  bool is_applicable = false;
     511
     512  switch ( rtl_release ) {
    527513    case CACHE_L2C_310_RTL_RELEASE_R3_P3:
    528514    case CACHE_L2C_310_RTL_RELEASE_R3_P2:
     
    532518    case CACHE_L2C_310_RTL_RELEASE_R0_P0:
    533519      is_applicable = false;
    534     break;
     520      break;
    535521    case CACHE_L2C_310_RTL_RELEASE_R3_P0:
    536522      is_applicable = true;
    537     break;
     523      break;
    538524    default:
    539        assert(   RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P3
    540               || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P2
    541               || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P1
    542               || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P0
    543               || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R2_P0
    544               || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R1_P0
    545               || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R0_P0 );
    546      break;
    547   }
    548  
     525      assert( 0 );
     526      break;
     527  }
     528
    549529  return is_applicable;
    550530}
    551531
    552532static bool l2c_310_cache_errata_is_applicable_727914(
    553   void
     533  cache_l2c_310_rtl_release rtl_release
    554534)
    555535{
    556   volatile L2CC                  *l2cc          =
    557     (volatile L2CC *) BSP_ARM_L2C_310_BASE;
    558   const cache_l2c_310_rtl_release RTL_RELEASE   =
    559     l2cc->cache_id & CACHE_L2C_310_L2CC_ID_RTL_MASK;
    560   bool                            is_applicable = false;
    561  
    562   switch( RTL_RELEASE ) {
     536  bool is_applicable = false;
     537
     538  switch ( rtl_release ) {
    563539    case CACHE_L2C_310_RTL_RELEASE_R3_P3:
    564540    case CACHE_L2C_310_RTL_RELEASE_R3_P2:
     
    568544    case CACHE_L2C_310_RTL_RELEASE_R0_P0:
    569545      is_applicable = false;
    570     break;
     546      break;
    571547    case CACHE_L2C_310_RTL_RELEASE_R3_P0:
    572548      is_applicable = true;
    573     break;
     549      break;
    574550    default:
    575        assert(   RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P3
    576               || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P2
    577               || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P1
    578               || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P0
    579               || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R2_P0
    580               || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R1_P0
    581               || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R0_P0 );
    582      break;
    583   }
    584  
     551      assert( 0 );
     552      break;
     553  }
     554
    585555  return is_applicable;
    586556}
    587557
    588558static bool l2c_310_cache_errata_is_applicable_727915(
    589   void
     559  cache_l2c_310_rtl_release rtl_release
    590560)
    591561{
    592   volatile L2CC                  *l2cc          =
    593     (volatile L2CC *) BSP_ARM_L2C_310_BASE;
    594   const cache_l2c_310_rtl_release RTL_RELEASE   =
    595     l2cc->cache_id & CACHE_L2C_310_L2CC_ID_RTL_MASK;
    596   bool                            is_applicable = false;
    597  
    598   switch( RTL_RELEASE ) {
     562  bool is_applicable = false;
     563
     564  switch ( rtl_release ) {
    599565    case CACHE_L2C_310_RTL_RELEASE_R3_P3:
    600566    case CACHE_L2C_310_RTL_RELEASE_R3_P2:
     
    603569    case CACHE_L2C_310_RTL_RELEASE_R0_P0:
    604570      is_applicable = false;
    605     break;
     571      break;
    606572    case CACHE_L2C_310_RTL_RELEASE_R3_P0:
    607573    case CACHE_L2C_310_RTL_RELEASE_R2_P0:
    608574      is_applicable = true;
    609     break;
     575      break;
    610576    default:
    611        assert(   RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P3
    612               || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P2
    613               || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P1
    614               || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P0
    615               || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R2_P0
    616               || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R1_P0
    617               || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R0_P0 );
    618      break;
    619   }
    620  
     577      assert( 0 );
     578      break;
     579  }
     580
    621581  return is_applicable;
    622582}
    623583
    624584static bool l2c_310_cache_errata_is_applicable_729806(
    625   void
     585  cache_l2c_310_rtl_release rtl_release
    626586)
    627587{
    628   volatile L2CC                  *l2cc          =
    629     (volatile L2CC *) BSP_ARM_L2C_310_BASE;
    630   const cache_l2c_310_rtl_release RTL_RELEASE   =
    631     l2cc->cache_id & CACHE_L2C_310_L2CC_ID_RTL_MASK;
    632   bool                            is_applicable = false;
    633  
    634   switch( RTL_RELEASE ) {
     588  bool is_applicable = false;
     589
     590  switch ( rtl_release ) {
    635591    case CACHE_L2C_310_RTL_RELEASE_R3_P3:
    636592    case CACHE_L2C_310_RTL_RELEASE_R3_P2:
     
    639595    case CACHE_L2C_310_RTL_RELEASE_R0_P0:
    640596      is_applicable = false;
    641     break;
     597      break;
    642598    case CACHE_L2C_310_RTL_RELEASE_R3_P1:
    643599    case CACHE_L2C_310_RTL_RELEASE_R3_P0:
    644600      is_applicable = true;
    645     break;
     601      break;
    646602    default:
    647        assert(   RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P3
    648               || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P2
    649               || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P1
    650               || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P0
    651               || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R2_P0
    652               || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R1_P0
    653               || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R0_P0 );
    654      break;
    655   }
    656  
     603      assert( 0 );
     604      break;
     605  }
     606
    657607  return is_applicable;
    658608}
    659609
    660610static bool l2c_310_cache_errata_is_applicable_729815(
    661   void
     611  cache_l2c_310_rtl_release rtl_release
    662612)
    663613{
    664   volatile L2CC                  *l2cc          =
    665     (volatile L2CC *) BSP_ARM_L2C_310_BASE;
    666   const cache_l2c_310_rtl_release RTL_RELEASE   =
    667     l2cc->cache_id & CACHE_L2C_310_L2CC_ID_RTL_MASK;
    668   bool                            is_applicable = false;
    669  
    670   switch( RTL_RELEASE ) {
     614  bool is_applicable = false;
     615
     616  switch ( rtl_release ) {
    671617    case CACHE_L2C_310_RTL_RELEASE_R3_P3:
    672618    case CACHE_L2C_310_RTL_RELEASE_R1_P0:
    673619    case CACHE_L2C_310_RTL_RELEASE_R0_P0:
    674620      is_applicable = false;
    675     break;
     621      break;
    676622    case CACHE_L2C_310_RTL_RELEASE_R3_P2:
    677623    case CACHE_L2C_310_RTL_RELEASE_R3_P1:
     
    679625    case CACHE_L2C_310_RTL_RELEASE_R2_P0:
    680626      is_applicable = true;
    681     break;
     627      break;
    682628    default:
    683        assert(   RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P3
    684               || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P2
    685               || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P1
    686               || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P0
    687               || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R2_P0
    688               || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R1_P0
    689               || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R0_P0 );
    690      break;
    691   }
    692  
     629      assert( 0 );
     630      break;
     631  }
     632
    693633  return is_applicable;
    694634}
    695635
    696636static bool l2c_310_cache_errata_is_applicable_742884(
    697   void
     637  cache_l2c_310_rtl_release rtl_release
    698638)
    699639{
    700   volatile L2CC                  *l2cc          =
    701     (volatile L2CC *) BSP_ARM_L2C_310_BASE;
    702   const cache_l2c_310_rtl_release RTL_RELEASE   =
    703     l2cc->cache_id & CACHE_L2C_310_L2CC_ID_RTL_MASK;
    704   bool                            is_applicable = false;
    705  
    706   switch( RTL_RELEASE ) {
     640  bool is_applicable = false;
     641
     642  switch ( rtl_release ) {
    707643    case CACHE_L2C_310_RTL_RELEASE_R3_P3:
    708644    case CACHE_L2C_310_RTL_RELEASE_R3_P2:
     
    712648    case CACHE_L2C_310_RTL_RELEASE_R0_P0:
    713649      is_applicable = false;
    714     break;
     650      break;
    715651    case CACHE_L2C_310_RTL_RELEASE_R3_P1:
    716652      is_applicable = true;
    717     break;
     653      break;
    718654    default:
    719        assert(   RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P3
    720               || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P2
    721               || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P1
    722               || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P0
    723               || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R2_P0
    724               || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R1_P0
    725               || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R0_P0 );
    726      break;
    727   }
    728  
     655      assert( 0 );
     656      break;
     657  }
     658
    729659  return is_applicable;
    730660}
    731661
    732662static bool l2c_310_cache_errata_is_applicable_752271(
    733   void
     663  cache_l2c_310_rtl_release rtl_release
    734664)
    735665{
    736   volatile L2CC                  *l2cc          =
    737     (volatile L2CC *) BSP_ARM_L2C_310_BASE;
    738   const cache_l2c_310_rtl_release RTL_RELEASE   =
    739     l2cc->cache_id & CACHE_L2C_310_L2CC_ID_RTL_MASK;
    740   bool                            is_applicable = false;
    741  
    742   switch( RTL_RELEASE ) {
     666  bool is_applicable = false;
     667
     668  switch ( rtl_release ) {
    743669    case CACHE_L2C_310_RTL_RELEASE_R3_P3:
    744670    case CACHE_L2C_310_RTL_RELEASE_R3_P2:
     
    747673    case CACHE_L2C_310_RTL_RELEASE_R0_P0:
    748674      is_applicable = false;
    749     break;
     675      break;
    750676    case CACHE_L2C_310_RTL_RELEASE_R3_P1:
    751677    case CACHE_L2C_310_RTL_RELEASE_R3_P0:
    752678      is_applicable = true;
    753     break;
     679      break;
    754680    default:
    755        assert(   RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P3
    756               || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P2
    757               || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P1
    758               || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P0
    759               || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R2_P0
    760               || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R1_P0
    761               || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R0_P0 );
    762      break;
    763   }
    764  
     681      assert( 0 );
     682      break;
     683  }
     684
    765685  return is_applicable;
    766686}
    767687
    768688static bool l2c_310_cache_errata_is_applicable_765569(
    769   void
     689  cache_l2c_310_rtl_release rtl_release
    770690)
    771691{
    772   volatile L2CC                  *l2cc          =
    773     (volatile L2CC *) BSP_ARM_L2C_310_BASE;
    774   const cache_l2c_310_rtl_release RTL_RELEASE   =
    775     l2cc->cache_id & CACHE_L2C_310_L2CC_ID_RTL_MASK;
    776   bool                            is_applicable = false;
    777  
    778   switch( RTL_RELEASE ) {
     692  bool is_applicable = false;
     693
     694  switch ( rtl_release ) {
     695    case CACHE_L2C_310_RTL_RELEASE_R3_P3:
     696    case CACHE_L2C_310_RTL_RELEASE_R3_P2:
     697    case CACHE_L2C_310_RTL_RELEASE_R3_P1:
     698    case CACHE_L2C_310_RTL_RELEASE_R3_P0:
     699    case CACHE_L2C_310_RTL_RELEASE_R2_P0:
     700    case CACHE_L2C_310_RTL_RELEASE_R1_P0:
     701    case CACHE_L2C_310_RTL_RELEASE_R0_P0:
     702      is_applicable = true;
     703      break;
     704    default:
     705      assert( 0 );
     706      break;
     707  }
     708
     709  return is_applicable;
     710}
     711
     712static bool l2c_310_cache_errata_is_applicable_769419(
     713  cache_l2c_310_rtl_release rtl_release
     714)
     715{
     716  bool is_applicable = false;
     717
     718  switch ( rtl_release ) {
     719    case CACHE_L2C_310_RTL_RELEASE_R3_P3:
     720    case CACHE_L2C_310_RTL_RELEASE_R3_P2:
     721      is_applicable = false;
     722      break;
     723    case CACHE_L2C_310_RTL_RELEASE_R3_P1:
     724    case CACHE_L2C_310_RTL_RELEASE_R3_P0:
     725    case CACHE_L2C_310_RTL_RELEASE_R2_P0:
     726    case CACHE_L2C_310_RTL_RELEASE_R1_P0:
     727    case CACHE_L2C_310_RTL_RELEASE_R0_P0:
     728      is_applicable = true;
     729      break;
     730    default:
     731      assert( 0 );
     732      break;
     733  }
     734
     735  return is_applicable;
     736}
     737
     738static bool l2c_310_cache_errata_is_applicable_588369(
     739  cache_l2c_310_rtl_release rtl_release
     740)
     741{
     742  bool is_applicable = false;
     743
     744  switch ( rtl_release ) {
     745    case CACHE_L2C_310_RTL_RELEASE_R3_P3:
     746    case CACHE_L2C_310_RTL_RELEASE_R3_P2:
     747    case CACHE_L2C_310_RTL_RELEASE_R3_P1:
     748    case CACHE_L2C_310_RTL_RELEASE_R3_P0:
     749    case CACHE_L2C_310_RTL_RELEASE_R2_P0:
     750      is_applicable = false;
     751      break;
     752    case CACHE_L2C_310_RTL_RELEASE_R1_P0:
     753    case CACHE_L2C_310_RTL_RELEASE_R0_P0:
     754      is_applicable = true;
     755      break;
     756    default:
     757      assert( 0 );
     758      break;
     759  }
     760
     761  return is_applicable;
     762}
     763
     764#ifdef CACHE_ERRATA_CHECKS_FOR_IMPLEMENTED_ERRATAS
     765static bool l2c_310_cache_errata_is_applicable_754670(
     766  cache_l2c_310_rtl_release rtl_release
     767)
     768{
     769  bool is_applicable = false;
     770
     771  switch ( rtl_release ) {
    779772    case CACHE_L2C_310_RTL_RELEASE_R3_P3:
    780773    case CACHE_L2C_310_RTL_RELEASE_R3_P2:
     
    787780    break;
    788781    default:
    789        assert(   RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P3
    790               || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P2
    791               || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P1
    792               || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P0
    793               || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R2_P0
    794               || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R1_P0
    795               || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R0_P0 );
    796      break;
    797   }
    798  
     782      assert( 0 );
     783      break;
     784  }
     785
    799786  return is_applicable;
    800787}
    801 
    802 static bool l2c_310_cache_errata_is_applicable_769419(
    803   void
    804 )
    805 {
    806   volatile L2CC                  *l2cc          =
    807     (volatile L2CC *) BSP_ARM_L2C_310_BASE;
    808   const cache_l2c_310_rtl_release RTL_RELEASE   =
    809     l2cc->cache_id & CACHE_L2C_310_L2CC_ID_RTL_MASK;
    810   bool                            is_applicable = false;
    811  
    812   switch( RTL_RELEASE ) {
    813     case CACHE_L2C_310_RTL_RELEASE_R3_P3:
    814     case CACHE_L2C_310_RTL_RELEASE_R3_P2:
    815       is_applicable = false;
    816     break;
    817     case CACHE_L2C_310_RTL_RELEASE_R3_P1:
    818     case CACHE_L2C_310_RTL_RELEASE_R3_P0:
    819     case CACHE_L2C_310_RTL_RELEASE_R2_P0:
    820     case CACHE_L2C_310_RTL_RELEASE_R1_P0:
    821     case CACHE_L2C_310_RTL_RELEASE_R0_P0:
    822       is_applicable = true;
    823     break;
    824     default:
    825        assert(   RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P3
    826               || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P2
    827               || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P1
    828               || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P0
    829               || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R2_P0
    830               || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R1_P0
    831               || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R0_P0 );
    832      break;
    833   }
    834  
    835   return is_applicable;
    836 }
    837 
    838 static bool l2c_310_cache_errata_is_applicable_588369(
    839   void
    840 )
    841 {
    842   volatile L2CC                  *l2cc          =
    843     (volatile L2CC *) BSP_ARM_L2C_310_BASE;
    844   const cache_l2c_310_rtl_release RTL_RELEASE   =
    845     l2cc->cache_id & CACHE_L2C_310_L2CC_ID_RTL_MASK;
    846   bool                            is_applicable = false;
    847  
    848   switch( RTL_RELEASE ) {
    849     case CACHE_L2C_310_RTL_RELEASE_R3_P3:
    850     case CACHE_L2C_310_RTL_RELEASE_R3_P2:
    851     case CACHE_L2C_310_RTL_RELEASE_R3_P1:
    852     case CACHE_L2C_310_RTL_RELEASE_R3_P0:
    853     case CACHE_L2C_310_RTL_RELEASE_R2_P0:
    854       is_applicable = false;
    855     break;
    856     case CACHE_L2C_310_RTL_RELEASE_R1_P0:
    857     case CACHE_L2C_310_RTL_RELEASE_R0_P0:
    858       is_applicable = true;
    859     break;
    860     default:
    861        assert(   RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P3
    862               || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P2
    863               || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P1
    864               || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P0
    865               || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R2_P0
    866               || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R1_P0
    867               || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R0_P0 );
    868      break;
    869   }
    870  
    871   return is_applicable;
    872 }
    873 
    874 #ifdef CACHE_ERRATA_CHECKS_FOR_IMPLEMENTED_ERRATAS
    875 static bool l2c_310_cache_errata_is_applicable_754670(
    876   void
    877 )
    878 {
    879   volatile L2CC                  *l2cc          =
    880     (volatile L2CC *) BSP_ARM_L2C_310_BASE;
    881   const cache_l2c_310_rtl_release RTL_RELEASE   =
    882     l2cc->cache_id & CACHE_L2C_310_L2CC_ID_RTL_MASK;
    883   bool                            is_applicable = false;
    884  
    885   switch( RTL_RELEASE ) {
    886     case CACHE_L2C_310_RTL_RELEASE_R3_P3:
    887     case CACHE_L2C_310_RTL_RELEASE_R3_P2:
    888     case CACHE_L2C_310_RTL_RELEASE_R3_P1:
    889     case CACHE_L2C_310_RTL_RELEASE_R3_P0:
    890     case CACHE_L2C_310_RTL_RELEASE_R2_P0:
    891     case CACHE_L2C_310_RTL_RELEASE_R1_P0:
    892     case CACHE_L2C_310_RTL_RELEASE_R0_P0:
    893       is_applicable = true;
    894     break;
    895     default:
    896        assert(   RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P3
    897               || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P2
    898               || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P1
    899               || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P0
    900               || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R2_P0
    901               || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R1_P0
    902               || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R0_P0 );
    903      break;
    904   }
    905  
    906   return is_applicable;
    907 }
    908788#endif /* CACHE_ERRATA_CHECKS_FOR_IMPLEMENTED_ERRATAS */
    909789
    910 /* The common workaround for this erratum would be to add a 
     790/* The common workaround for this erratum would be to add a
    911791 * data synchronization barrier to the beginning of the abort handler.
    912  * But for RTEMS a call of the abort handler means a fatal condition anyway. 
     792 * But for RTEMS a call of the abort handler means a fatal condition anyway.
    913793 * So there is no need to handle this erratum */
    914794#define CACHE_ARM_ERRATA_775420_HANDLER()                   \
     
    916796  }                                                         \
    917797
    918 static void l2c_310_cache_check_errata( void )
     798static void l2c_310_cache_check_errata( cache_l2c_310_rtl_release rtl_release )
    919799{
    920800  /* This erratum gets handled within the sources */
    921   /* Unhandled erratum present: 588369 Errata 588369 says that clean + inv may 
     801  /* Unhandled erratum present: 588369 Errata 588369 says that clean + inv may
    922802   * keep the cache line if it was clean. See ARMs documentation on the erratum
    923803   * for a workaround */
    924   /* assert( ! l2c_310_cache_errata_is_applicable_588369() ); */
    925 
    926   /* Unhandled erratum present: 727913 Prefetch dropping feature can cause 
    927    * incorrect behavior when PL310 handles reads that cross cache line 
     804  /* assert( ! l2c_310_cache_errata_is_applicable_588369( rtl_release ) ); */
     805
     806  /* Unhandled erratum present: 727913 Prefetch dropping feature can cause
     807   * incorrect behavior when PL310 handles reads that cross cache line
    928808   * boundary */
    929   assert( ! l2c_310_cache_errata_is_applicable_727913() );
    930 
    931   /* Unhandled erratum present: 727914 Double linefill feature can cause 
     809  assert( ! l2c_310_cache_errata_is_applicable_727913( rtl_release ) );
     810
     811  /* Unhandled erratum present: 727914 Double linefill feature can cause
    932812   * deadlock */
    933   assert( ! l2c_310_cache_errata_is_applicable_727914() );
    934  
    935   /* Unhandled erratum present: 727915 Background Clean and Invalidate by Way 
     813  assert( ! l2c_310_cache_errata_is_applicable_727914( rtl_release ) );
     814
     815  /* Unhandled erratum present: 727915 Background Clean and Invalidate by Way
    936816   * operation can cause data corruption */
    937   assert( ! l2c_310_cache_errata_is_applicable_727915() );
    938 
    939   /* Unhandled erratum present: 729806 Speculative reads from the Cortex-A9 
     817  assert( ! l2c_310_cache_errata_is_applicable_727915( rtl_release ) );
     818
     819  /* Unhandled erratum present: 729806 Speculative reads from the Cortex-A9
    940820   * MPCore processor can cause deadlock */
    941   assert( ! l2c_310_cache_errata_is_applicable_729806() );
    942 
    943   if( l2c_310_cache_errata_is_applicable_729815() )
     821  assert( ! l2c_310_cache_errata_is_applicable_729806( rtl_release ) );
     822
     823  if( l2c_310_cache_errata_is_applicable_729815( rtl_release ) )
    944824  {
    945825    volatile L2CC *l2cc = (volatile L2CC *) BSP_ARM_L2C_310_BASE;
     
    947827    assert( 0 == ( l2cc->aux_ctrl & CACHE_L2C_310_L2CC_AUX_HPSODRE_MASK ) );
    948828
    949     /* Erratum: 729815 The “High Priority for SO and Dev reads” feature can 
     829    /* Erratum: 729815 The “High Priority for SO and Dev reads” feature can
    950830     * cause Quality of Service issues to cacheable read transactions*/
    951831
    952832    /* Conditions
    953833       This problem occurs when the following conditions are met:
    954        1. Bit[10] “High Priority for SO and Dev reads enable” of the PL310 
     834       1. Bit[10] “High Priority for SO and Dev reads enable” of the PL310
    955835          Auxiliary Control Register is set to 1.
    956836       2. PL310 receives a cacheable read that misses in the L2 cache.
    957        3. PL310 receives a continuous flow of Strongly Ordered or Device 
     837       3. PL310 receives a continuous flow of Strongly Ordered or Device
    958838          reads that take all address slots in the master interface.
    959839       Workaround
    960        A workaround is only necessary in systems that are able to issue a 
    961        continuous flow of Strongly Ordered or Device reads. In such a case, 
    962        the workaround is to disable the “High Priority for SO and Dev reads” 
     840       A workaround is only necessary in systems that are able to issue a
     841       continuous flow of Strongly Ordered or Device reads. In such a case,
     842       the workaround is to disable the “High Priority for SO and Dev reads”
    963843       feature. This is the default behavior.*/
    964844  }
    965  
    966   /* Unhandled erratum present: 742884 Double linefill feature might introduce 
     845
     846  /* Unhandled erratum present: 742884 Double linefill feature might introduce
    967847   * circular dependency and deadlock */
    968   assert( ! l2c_310_cache_errata_is_applicable_742884() );
    969 
    970   /* Unhandled erratum present: 752271 Double linefill feature can cause data 
     848  assert( ! l2c_310_cache_errata_is_applicable_742884( rtl_release ) );
     849
     850  /* Unhandled erratum present: 752271 Double linefill feature can cause data
    971851   * corruption */
    972   assert( ! l2c_310_cache_errata_is_applicable_752271() );
    973 
    974   /* This erratum can not be worked around: 754670 A continuous write flow can 
     852  assert( ! l2c_310_cache_errata_is_applicable_752271( rtl_release ) );
     853
     854  /* This erratum can not be worked around: 754670 A continuous write flow can
    975855   * stall a read targeting the same memory area
    976856   * But this erratum does not lead to any data corruption */
    977857  /* assert( ! l2c_310_cache_errata_is_applicable_754670() ); */
    978858
    979   if( l2c_310_cache_errata_is_applicable_765569() )
     859  if( l2c_310_cache_errata_is_applicable_765569( rtl_release ) )
    980860  {
    981861    volatile L2CC *l2cc = (volatile L2CC *) BSP_ARM_L2C_310_BASE;
     
    986866                    == 23 ) ) );
    987867
    988     /* Unhandled erratum present: 765569 Prefetcher can cross 4KB boundary if 
     868    /* Unhandled erratum present: 765569 Prefetcher can cross 4KB boundary if
    989869     * offset is programmed with value 23 */
    990870
    991871    /* Conditions
    992872       This problem occurs when the following conditions are met:
    993        1. One of the Prefetch Enable bits (bits [29:28] of the Auxiliary or 
     873       1. One of the Prefetch Enable bits (bits [29:28] of the Auxiliary or
    994874          Prefetch Control Register) is set HIGH.
    995875       2. The prefetch offset bits are programmed with value 23 (5'b10111).
     
    999879  }
    1000880
    1001   /* Unhandled erratum present: 769419 No automatic Store Buffer drain, 
     881  /* Unhandled erratum present: 769419 No automatic Store Buffer drain,
    1002882   * visibility of written data requires an explicit Cache */
    1003   assert( ! l2c_310_cache_errata_is_applicable_769419() );
     883  assert( ! l2c_310_cache_errata_is_applicable_769419( rtl_release ) );
    1004884}
    1005885
     
    1008888{
    1009889  volatile L2CC *l2cc = (volatile L2CC *) BSP_ARM_L2C_310_BASE;
    1010 
    1011   if( l2c_310_cache_errata_is_applicable_753970() ) {
     890  cache_l2c_310_rtl_release rtl_release =
     891    l2cc->cache_id & CACHE_L2C_310_L2CC_ID_RTL_MASK;
     892
     893  if( l2c_310_cache_errata_is_applicable_753970( rtl_release ) ) {
    1012894    l2cc->dummy_cache_sync_reg = 0;
    1013895  } else {
     
    1050932  uint32_t       block_end         =
    1051933    CACHE_MIN( ADDR_LAST, adx + CACHE_MAX_LOCKING_BYTES );
     934  volatile L2CC *l2cc = (volatile L2CC *) BSP_ARM_L2C_310_BASE;
     935  cache_l2c_310_rtl_release rtl_release =
     936    l2cc->cache_id & CACHE_L2C_310_L2CC_ID_RTL_MASK;
    1052937  bool is_errata_588369_applicable =
    1053     l2c_310_cache_errata_is_applicable_588369();
     938    l2c_310_cache_errata_is_applicable_588369( rtl_release );
    1054939
    1055940  rtems_interrupt_lock_acquire( &l2c_310_cache_lock, &lock_context );
     
    11861071  uint32_t       way_size;
    11871072  uint32_t       num_ways;
    1188  
     1073
    11891074  way_size = (cache_type & CACHE_L2C_310_L2CC_TYPE_SIZE_D_WAYS_MASK)
    11901075    >> CACHE_L2C_310_L2CC_TYPE_SIZE_D_WAYS_SHIFT;
     
    12451130{
    12461131  volatile L2CC *l2cc = (volatile L2CC *) BSP_ARM_L2C_310_BASE;
    1247  
     1132  cache_l2c_310_rtl_release rtl_release =
     1133    l2cc->cache_id & CACHE_L2C_310_L2CC_ID_RTL_MASK;
     1134
    12481135  /* Only enable if L2CC is currently disabled */
    12491136  if( ( l2cc->ctrl & CACHE_L2C_310_L2CC_ENABLE_MASK ) == 0 ) {
     
    12571144      case CACHE_L2C_310_L2CC_ID_PART_L310:
    12581145      {
    1259         const cache_l2c_310_rtl_release RTL_RELEASE =
    1260           l2cc->cache_id & CACHE_L2C_310_L2CC_ID_RTL_MASK;
    12611146        /* If this assertion fails, you have a release of the
    12621147        * L2C-310 cache for which the l2c_310_cache_errata_is_applicable_ ...
    12631148        * methods are not yet implemented. This means you will get incorrect
    12641149        * errata handling */
    1265         assert(    RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P3
    1266                 || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P2
    1267                 || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P1
    1268                 || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P0
    1269                 || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R2_P0
    1270                 || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R1_P0
    1271                 || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R0_P0 );
     1150        assert(    rtl_release == CACHE_L2C_310_RTL_RELEASE_R3_P3
     1151                || rtl_release == CACHE_L2C_310_RTL_RELEASE_R3_P2
     1152                || rtl_release == CACHE_L2C_310_RTL_RELEASE_R3_P1
     1153                || rtl_release == CACHE_L2C_310_RTL_RELEASE_R3_P0
     1154                || rtl_release == CACHE_L2C_310_RTL_RELEASE_R2_P0
     1155                || rtl_release == CACHE_L2C_310_RTL_RELEASE_R1_P0
     1156                || rtl_release == CACHE_L2C_310_RTL_RELEASE_R0_P0 );
    12721157        if ( l2cc->aux_ctrl & ( 1 << 16 ) ) {
    12731158          ways = 16;
     
    13251210      l2cc->int_clr = l2cc->int_raw_status;
    13261211
    1327       l2c_310_cache_check_errata();
     1212      l2c_310_cache_check_errata( rtl_release );
    13281213
    13291214      /* Enable the L2CC */
     
    13331218}
    13341219
    1335 static inline void 
     1220static inline void
    13361221cache_l2c_310_disable( void )
    13371222{
     
    13581243}
    13591244
    1360 static inline void 
     1245static inline void
    13611246_CPU_cache_enable_data( void )
    13621247{
     
    13641249}
    13651250
    1366 static inline void 
     1251static inline void
    13671252_CPU_cache_disable_data( void )
    13681253{
     
    13711256}
    13721257
    1373 static inline void 
     1258static inline void
    13741259_CPU_cache_enable_instruction( void )
    13751260{
     
    13771262}
    13781263
    1379 static inline void 
     1264static inline void
    13801265_CPU_cache_disable_instruction( void )
    13811266{
     
    13841269}
    13851270
    1386 static inline void 
     1271static inline void
    13871272_CPU_cache_flush_data_range(
    13881273  const void *d_addr,
     
    13911276{
    13921277  if ( n_bytes != 0 ) {
    1393     arm_cache_l1_flush_data_range( 
     1278    arm_cache_l1_flush_data_range(
    13941279      d_addr,
    13951280      n_bytes
     
    14021287}
    14031288
    1404 static inline void 
     1289static inline void
    14051290_CPU_cache_flush_entire_data( void )
    14061291{
     
    14091294}
    14101295
    1411 static inline void 
    1412 _CPU_cache_invalidate_data_range( 
     1296static inline void
     1297_CPU_cache_invalidate_data_range(
    14131298  const void *addr_first,
    1414   size_t     n_bytes 
     1299  size_t     n_bytes
    14151300)
    14161301{
     
    14231308    uint32_t       block_end =
    14241309      CACHE_MIN( ADDR_LAST, adx + CACHE_MAX_LOCKING_BYTES );
    1425    
     1310
    14261311    /* We have to apply a lock. Thus we will operate only CACHE_MAX_LOCKING_BYTES
    14271312     * at a time */
     
    14581343}
    14591344
    1460 static inline void 
     1345static inline void
    14611346_CPU_cache_invalidate_entire_data( void )
    14621347{
     
    14711356}
    14721357
    1473 static inline void 
     1358static inline void
    14741359_CPU_cache_freeze_data( void )
    14751360{
     
    14781363}
    14791364
    1480 static inline void 
     1365static inline void
    14811366_CPU_cache_unfreeze_data( void )
    14821367{
     
    14851370}
    14861371
    1487 static inline void 
     1372static inline void
    14881373_CPU_cache_invalidate_instruction_range( const void *i_addr, size_t n_bytes)
    14891374{
     
    14911376}
    14921377
    1493 static inline void 
     1378static inline void
    14941379_CPU_cache_invalidate_entire_instruction( void )
    14951380{
     
    14971382}
    14981383
    1499 static inline void 
     1384static inline void
    15001385_CPU_cache_freeze_instruction( void )
    15011386{
     
    15041389}
    15051390
    1506 static inline void 
     1391static inline void
    15071392_CPU_cache_unfreeze_instruction( void )
    15081393{
     
    15151400{
    15161401  size_t size = 0;
    1517  
     1402
    15181403  switch( level )
    15191404  {
     
    15361421{
    15371422  size_t size = 0;
    1538  
     1423
    15391424  switch( level )
    15401425  {
Note: See TracChangeset for help on using the changeset viewer.