Changeset a902441a in rtems
- Timestamp:
- 03/16/99 02:26:50 (24 years ago)
- Branches:
- 4.10, 4.11, 4.8, 4.9, 5, master
- Children:
- 1c0a186b
- Parents:
- 6d0e13c
- Files:
-
- 8 edited
Legend:
- Unmodified
- Added
- Removed
-
c/src/lib/libbsp/m68k/efi332/console/console.c
r6d0e13c ra902441a 329 329 char *buffer; 330 330 int maximum; 331 int count = 0;331 int count; 332 332 333 333 rw_args = (rtems_libio_rw_args_t *) arg; -
c/src/lib/libbsp/m68k/efi332/include/efi332.h
r6d0e13c ra902441a 44 44 /* 45 45 * This prototype really should have the noreturn attribute but 46 * that causes a warning since it appears that the routine does 47 * return. 48 * 49 * void reboot(void) __attribute__ ((noreturn)); 46 * that causes a warning. Not sure how to fix that. 50 47 */ 51 52 void reboot(void); 48 /* static void reboot(void) __attribute__ ((noreturn)); */ 49 static void reboot(void); 50 __inline__ static void reboot() {asm("trap #15");} 53 51 54 52 #endif /* _EFI332_H_ */ -
c/src/lib/libbsp/m68k/efi332/start/start.c
r6d0e13c ra902441a 11 11 m68k_isr_entry vectors[256]; 12 12 char * const __argv[]= {"main", ""}; 13 char * const __env[]= {""}; 13 14 void boot_card(int argc, char * const argv[]); 14 15 15 16 /* 16 17 * This prototype really should have the noreturn attribute but 17 * that causes a warning since it appears that the routine does 18 * return. 19 * 20 * void dumby_start () __attribute__ ((noreturn)); 18 * that causes a warning. Not sure how to fix that. 21 19 */ 22 20 /* void dumby_start () __attribute__ ((noreturn)); */ 23 21 void dumby_start (); 22 24 23 void dumby_start() { 25 void boot_card();26 24 27 25 /* We need to by-pass the link instruction since the RAM chip- … … 37 35 addl " STACK_SIZE ",%d0; 38 36 movel %d0,%sp; 39 link %a6, #0"37 movel %d0,%a6" 40 38 ); 41 39 … … 92 90 (((0x080000 >> 8)&0xfff8) | BS_256K ); /* 256k bytes located at 0x80000 */ 93 91 *CSBAR2 = (unsigned short int) 94 (((0x080000 >> 8)&0xfff8) | BS_256K ); /* 256 bytes located at 0x80000 */92 (((0x080000 >> 8)&0xfff8) | BS_256K ); /* 256k bytes located at 0x80000 */ 95 93 *CSBAR3 = (unsigned short int) 94 (((0x0C0000 >> 8)&0xfff8) | BS_256K ); /* 256k bytes located at 0xC0000 */ 95 *CSBAR4 = (unsigned short int) 96 (((0x0C0000 >> 8)&0xfff8) | BS_256K ); /* 256 bytes located at 0xC0000 */ 97 *CSBAR5 = (unsigned short int) 96 98 (0xfff8 | BS_64K); /* AVEC interrupts */ 99 #ifdef EFI332_v040b 100 *CSBAR6 = (unsigned short int) 101 (((0x000000 >> 8)&0xfff8) | BS_512K ); /* 512k bytes located at 0x0000 */ 102 *CSBAR8 = (unsigned short int) /* PCMCIA IOCS */ 103 (((0x0c0000 >> 8)&0xfff8) | BS_64K ); /* 64k bytes located at 0xc0000 */ 104 *CSBAR9 = (unsigned short int) /* PCMCIA MEMCS */ 105 (((0x0D0000 >> 8)&0xfff8) | BS_64K ); /* 64k bytes located at 0xd0000 */ 106 #else /* EFI332_v040b */ 97 107 *CSBAR10 = (unsigned short int) 98 108 (((0x000000 >> 8)&0xfff8) | BS_512K ); /* 512k bytes located at 0x0000 */ 109 #endif /* EFI332_v040b */ 99 110 100 111 /* Chip-Select Options Registers */ 101 112 /* see section 7 of the SIM Reference Manual */ 113 #ifdef FLASHWRITE 102 114 *CSORBT = (unsigned short int) 103 ( BothBytes | ReadWrite | SyncAS | WaitStates_13 | UserSupSpace ); 115 ( BothBytes | ReadWrite | SyncAS | WaitStates_2 | UserSupSpace ); 116 #else /* FLASHWRITE */ 117 *CSORBT = (unsigned short int) 118 ( BothBytes | ReadOnly | SyncAS | WaitStates_2 | UserSupSpace ); 119 #endif /* FLASHWRITE */ 104 120 *CSOR0 = (unsigned short int) 105 121 ( BothBytes | ReadOnly | SyncAS | External | UserSupSpace ); … … 109 125 ( UpperByte | ReadWrite | SyncAS | FastTerm | UserSupSpace ); 110 126 *CSOR3 = (unsigned short int) 127 ( LowerByte | ReadWrite | SyncAS | FastTerm | UserSupSpace ); 128 *CSOR4 = (unsigned short int) 129 ( UpperByte | ReadWrite | SyncAS | FastTerm | UserSupSpace ); 130 *CSOR5 = (unsigned short int) 111 131 ( BothBytes | ReadWrite | SyncAS | CPUSpace | IPLevel_any | AVEC ); 132 #ifdef EFI332_v040b 133 *CSOR6 = (unsigned short int) 134 ( BothBytes | ReadOnly | SyncAS | External | UserSupSpace ); 135 *CSOR8 = (unsigned short int) 136 ( BothBytes | ReadWrite | SyncAS | External | UserSupSpace ); 137 *CSOR9 = (unsigned short int) 138 ( BothBytes | ReadWrite | SyncAS | External | UserSupSpace ); 139 #else /* EFI332_v040b */ 112 140 *CSOR10 = (unsigned short int) 113 141 ( BothBytes | ReadOnly | SyncAS | External | UserSupSpace ); 142 #endif /* EFI332_v040b */ 114 143 115 144 /* Chip Select Pin Assignment Register 0 */ 116 145 /* see section 7 of the SIM Reference Manual */ 117 146 *CSPAR0 = (unsigned short int)( 118 SAM(DisOut,CS_5,0x3000) | /* PC2*/119 SAM( DisOut,CS_4,0x0c00) | /* PC1*/120 SAM( DisOut,CS_3,0x0300) | /* AVEC (internally)*/121 SAM(CS16bit,CS_2,0x00c0)| /* RAM UDS */122 SAM(CS16bit,CS_1,0x0030)| /* RAM LDS */147 SAM(DisOut,CS_5,0x3000) | /* AVEC (internally) */ 148 SAM(CS16bit,CS_4,0x0c00) | /* RAM UDS, bank2 */ 149 SAM(CS16bit,CS_3,0x0300) | /* RAM LDS, bank2 */ 150 SAM(CS16bit,CS_2,0x00c0)| /* RAM UDS, bank1 */ 151 SAM(CS16bit,CS_1,0x0030)| /* RAM LDS, bank1 */ 123 152 SAM(CS16bit,CS_0,0x000c)| /* W/!R */ 124 SAM(CS16bit,CSBOOT,0x0003) /* ROM DS */153 SAM(CS16bit,CSBOOT,0x0003) /* ROM CS */ 125 154 ); 126 155 127 156 /* Chip Select Pin Assignment Register 1 */ 128 157 /* see section 7 of the SIM Reference Manual */ 158 #ifdef EFI332_v040b 129 159 *CSPAR1 = (unsigned short int)( 130 SAM(CS16bit,CS_10,0x300)| /* ECLK */ 160 SAM(DisOut,CS_10,0x300)| /* ECLK */ 161 SAM(CS16bit,CS_9,0x0c0) | /* PCMCIA MEMCS */ 162 SAM(CS16bit,CS_8,0x030) | /* PCMCIA IOCS */ 163 SAM(DisOut,CS_7,0x00c) | /* PC4 */ 164 SAM(CS16bit,CS_6,0x003) /* ROM !OE */ 165 ); 166 #else /* EFI332_v040b */ 167 *CSPAR1 = (unsigned short int)( 168 SAM(CS16bit,CS_10,0x300)| /* ROM !OE */ 131 169 SAM(DisOut,CS_9,0x0c0) | /* PC6 */ 132 170 SAM(DisOut,CS_8,0x030) | /* PC5 */ … … 134 172 SAM(DisOut,CS_6,0x003) /* PC3 */ 135 173 ); 174 #endif /* EFI332_v040b */ 136 175 137 176 /* Port E and F Data Register */ … … 180 219 181 220 /* 182 * Execute main with arguments argv and environment env 183 */ 184 /* main(1, __argv, __env); */ 185 186 boot_card(); 187 221 * Execute main with arguments argc and agrv. 222 */ 223 boot_card(1,__argv); 188 224 reboot(); 225 189 226 } 190 227 191 void reboot() {asm("trap #15");}192 -
c/src/lib/libbsp/m68k/efi332/start332/start332.c
r6d0e13c ra902441a 11 11 m68k_isr_entry vectors[256]; 12 12 char * const __argv[]= {"main", ""}; 13 char * const __env[]= {""}; 13 14 void boot_card(int argc, char * const argv[]); 14 15 15 16 /* 16 17 * This prototype really should have the noreturn attribute but 17 * that causes a warning since it appears that the routine does 18 * return. 19 * 20 * void dumby_start () __attribute__ ((noreturn)); 18 * that causes a warning. Not sure how to fix that. 21 19 */ 22 20 /* void dumby_start () __attribute__ ((noreturn)); */ 23 21 void dumby_start (); 22 24 23 void dumby_start() { 25 void boot_card();26 24 27 25 /* We need to by-pass the link instruction since the RAM chip- … … 37 35 addl " STACK_SIZE ",%d0; 38 36 movel %d0,%sp; 39 link %a6, #0"37 movel %d0,%a6" 40 38 ); 41 39 … … 92 90 (((0x080000 >> 8)&0xfff8) | BS_256K ); /* 256k bytes located at 0x80000 */ 93 91 *CSBAR2 = (unsigned short int) 94 (((0x080000 >> 8)&0xfff8) | BS_256K ); /* 256 bytes located at 0x80000 */92 (((0x080000 >> 8)&0xfff8) | BS_256K ); /* 256k bytes located at 0x80000 */ 95 93 *CSBAR3 = (unsigned short int) 94 (((0x0C0000 >> 8)&0xfff8) | BS_256K ); /* 256k bytes located at 0xC0000 */ 95 *CSBAR4 = (unsigned short int) 96 (((0x0C0000 >> 8)&0xfff8) | BS_256K ); /* 256 bytes located at 0xC0000 */ 97 *CSBAR5 = (unsigned short int) 96 98 (0xfff8 | BS_64K); /* AVEC interrupts */ 99 #ifdef EFI332_v040b 100 *CSBAR6 = (unsigned short int) 101 (((0x000000 >> 8)&0xfff8) | BS_512K ); /* 512k bytes located at 0x0000 */ 102 *CSBAR8 = (unsigned short int) /* PCMCIA IOCS */ 103 (((0x0c0000 >> 8)&0xfff8) | BS_64K ); /* 64k bytes located at 0xc0000 */ 104 *CSBAR9 = (unsigned short int) /* PCMCIA MEMCS */ 105 (((0x0D0000 >> 8)&0xfff8) | BS_64K ); /* 64k bytes located at 0xd0000 */ 106 #else /* EFI332_v040b */ 97 107 *CSBAR10 = (unsigned short int) 98 108 (((0x000000 >> 8)&0xfff8) | BS_512K ); /* 512k bytes located at 0x0000 */ 109 #endif /* EFI332_v040b */ 99 110 100 111 /* Chip-Select Options Registers */ 101 112 /* see section 7 of the SIM Reference Manual */ 113 #ifdef FLASHWRITE 102 114 *CSORBT = (unsigned short int) 103 ( BothBytes | ReadWrite | SyncAS | WaitStates_13 | UserSupSpace ); 115 ( BothBytes | ReadWrite | SyncAS | WaitStates_2 | UserSupSpace ); 116 #else /* FLASHWRITE */ 117 *CSORBT = (unsigned short int) 118 ( BothBytes | ReadOnly | SyncAS | WaitStates_2 | UserSupSpace ); 119 #endif /* FLASHWRITE */ 104 120 *CSOR0 = (unsigned short int) 105 121 ( BothBytes | ReadOnly | SyncAS | External | UserSupSpace ); … … 109 125 ( UpperByte | ReadWrite | SyncAS | FastTerm | UserSupSpace ); 110 126 *CSOR3 = (unsigned short int) 127 ( LowerByte | ReadWrite | SyncAS | FastTerm | UserSupSpace ); 128 *CSOR4 = (unsigned short int) 129 ( UpperByte | ReadWrite | SyncAS | FastTerm | UserSupSpace ); 130 *CSOR5 = (unsigned short int) 111 131 ( BothBytes | ReadWrite | SyncAS | CPUSpace | IPLevel_any | AVEC ); 132 #ifdef EFI332_v040b 133 *CSOR6 = (unsigned short int) 134 ( BothBytes | ReadOnly | SyncAS | External | UserSupSpace ); 135 *CSOR8 = (unsigned short int) 136 ( BothBytes | ReadWrite | SyncAS | External | UserSupSpace ); 137 *CSOR9 = (unsigned short int) 138 ( BothBytes | ReadWrite | SyncAS | External | UserSupSpace ); 139 #else /* EFI332_v040b */ 112 140 *CSOR10 = (unsigned short int) 113 141 ( BothBytes | ReadOnly | SyncAS | External | UserSupSpace ); 142 #endif /* EFI332_v040b */ 114 143 115 144 /* Chip Select Pin Assignment Register 0 */ 116 145 /* see section 7 of the SIM Reference Manual */ 117 146 *CSPAR0 = (unsigned short int)( 118 SAM(DisOut,CS_5,0x3000) | /* PC2*/119 SAM( DisOut,CS_4,0x0c00) | /* PC1*/120 SAM( DisOut,CS_3,0x0300) | /* AVEC (internally)*/121 SAM(CS16bit,CS_2,0x00c0)| /* RAM UDS */122 SAM(CS16bit,CS_1,0x0030)| /* RAM LDS */147 SAM(DisOut,CS_5,0x3000) | /* AVEC (internally) */ 148 SAM(CS16bit,CS_4,0x0c00) | /* RAM UDS, bank2 */ 149 SAM(CS16bit,CS_3,0x0300) | /* RAM LDS, bank2 */ 150 SAM(CS16bit,CS_2,0x00c0)| /* RAM UDS, bank1 */ 151 SAM(CS16bit,CS_1,0x0030)| /* RAM LDS, bank1 */ 123 152 SAM(CS16bit,CS_0,0x000c)| /* W/!R */ 124 SAM(CS16bit,CSBOOT,0x0003) /* ROM DS */153 SAM(CS16bit,CSBOOT,0x0003) /* ROM CS */ 125 154 ); 126 155 127 156 /* Chip Select Pin Assignment Register 1 */ 128 157 /* see section 7 of the SIM Reference Manual */ 158 #ifdef EFI332_v040b 129 159 *CSPAR1 = (unsigned short int)( 130 SAM(CS16bit,CS_10,0x300)| /* ECLK */ 160 SAM(DisOut,CS_10,0x300)| /* ECLK */ 161 SAM(CS16bit,CS_9,0x0c0) | /* PCMCIA MEMCS */ 162 SAM(CS16bit,CS_8,0x030) | /* PCMCIA IOCS */ 163 SAM(DisOut,CS_7,0x00c) | /* PC4 */ 164 SAM(CS16bit,CS_6,0x003) /* ROM !OE */ 165 ); 166 #else /* EFI332_v040b */ 167 *CSPAR1 = (unsigned short int)( 168 SAM(CS16bit,CS_10,0x300)| /* ROM !OE */ 131 169 SAM(DisOut,CS_9,0x0c0) | /* PC6 */ 132 170 SAM(DisOut,CS_8,0x030) | /* PC5 */ … … 134 172 SAM(DisOut,CS_6,0x003) /* PC3 */ 135 173 ); 174 #endif /* EFI332_v040b */ 136 175 137 176 /* Port E and F Data Register */ … … 180 219 181 220 /* 182 * Execute main with arguments argv and environment env 183 */ 184 /* main(1, __argv, __env); */ 185 186 boot_card(); 187 221 * Execute main with arguments argc and agrv. 222 */ 223 boot_card(1,__argv); 188 224 reboot(); 225 189 226 } 190 227 191 void reboot() {asm("trap #15");}192 -
c/src/lib/libbsp/m68k/efi332/startup/Makefile.in
r6d0e13c ra902441a 20 20 H_FILES= 21 21 22 SRCS=$(C_FILES) $(H_FILES) 23 OBJS=$(C_O_FILES) 22 # Assembly source names, if any, go here -- minus the .S 23 S_PIECES= except_vect_332_ROM 24 S_FILES=$(S_PIECES:%=%.S) 25 S_O_FILES=$(S_FILES:%.S=${ARCH}/%.o) 26 27 SRCS=$(C_FILES) $(H_FILES) $(S_FILES) 28 OBJS=$(C_O_FILES) $(S_O_FILES) 24 29 25 30 include $(RTEMS_ROOT)/make/custom/$(RTEMS_BSP).cfg … … 53 58 all: ${ARCH} $(SRCS) $(PGM) 54 59 $(INSTALL_CHANGE) $(srcdir)/linkcmds ${PROJECT_RELEASE}/lib 60 $(INSTALL_CHANGE) $(srcdir)/linkcmds_ROM ${PROJECT_RELEASE}/lib 61 $(INSTALL_CHANGE) ${ARCH}/except_vect_332_ROM.o ${PROJECT_RELEASE}/lib 55 62 56 63 # the .rel file built here will be put into libbsp.a by ../wrapup/Makefile -
c/src/lib/libbsp/m68k/efi332/startup/linkcmds
r6d0e13c ra902441a 33 33 MEMORY 34 34 { 35 ram : ORIGIN = 0x80000, LENGTH = 256K35 ram : ORIGIN = 0x80000, LENGTH = 512K 36 36 } 37 37 38 __end_of_ram = 0x c0000;38 __end_of_ram = 0x100000; 39 39 _copy_data_from_rom = 0; 40 40 … … 49 49 text_start = .; 50 50 _text_start = .; 51 51 52 *(.text) 52 53 . = ALIGN (16); 54 53 55 *(.eh_fram) 54 56 . = ALIGN (16); … … 69 71 *(.shdata) 70 72 _endtext = .; 73 } > ram 74 .gcc_exc : 75 { 76 *(.gcc_exc) 71 77 } > ram 72 78 .data : -
c/src/lib/libbsp/m68k/efi332/startup/linkcmds_ROM
r6d0e13c ra902441a 41 41 { 42 42 rom : ORIGIN = 0x00000, LENGTH = 256K 43 ram : ORIGIN = 0x80000, LENGTH = 256K43 ram : ORIGIN = 0x80000, LENGTH = 512K 44 44 } 45 45 46 __end_of_ram = 0x c0000;46 __end_of_ram = 0x100000; 47 47 _copy_data_from_rom = 1; 48 48 … … 58 58 _text_start = .; 59 59 *(.text) 60 . = ALIGN (16); 61 62 *(.eh_fram) 63 . = ALIGN (16); 64 60 65 etext = ALIGN(0x10); 61 66 _etext = .; … … 74 79 _endtext = .; 75 80 } > rom 81 .gcc_exc : 82 AT ( ADDR(.text) + SIZEOF( .text ) ) 83 { 84 *(.gcc_exc) 85 } > ram 76 86 .data : 77 AT ( ADDR(.text) + SIZEOF( .text ) )78 87 { 79 88 data_start = .; -
make/custom/efi332.cfg
r6d0e13c ra902441a 15 15 # This contains the compiler options necessary to select the CPU model 16 16 # and (hopefully) optimize for it. 17 # 18 # XXX JRS - my gas does not grok -m68332 19 #CPU_CFLAGS = -m68332 20 CPU_CFLAGS = -m68020 17 CPU_CFLAGS = -mcpu32 21 18 22 19 # optimize flag: typically -0, could use -O4 or -fast, -O4 is ok for RTEMS
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