Changeset a762dc2 in rtems


Ignore:
Timestamp:
Jan 23, 2012, 10:19:22 AM (8 years ago)
Author:
Sebastian Huber <sebastian.huber@…>
Branches:
4.11, master
Children:
f4491f94
Parents:
9bf3a868
Message:

Support for MPC5643L.

Rework of the start sequence to reduce the amount assembler code and to
support configuration tables which may be provided by the application.

Location:
c/src/lib
Files:
17 added
3 deleted
29 edited
5 moved

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/powerpc/mpc55xxevb/Makefile.am

    r9bf3a868 ra762dc2  
    3131dist_project_lib_DATA += startup/linkcmds.mpc5674fevb
    3232dist_project_lib_DATA += startup/linkcmds.mpc5674fevb_spe
     33dist_project_lib_DATA += startup/linkcmds.xkt564levb
    3334dist_project_lib_DATA += startup/linkcmds.phycore_mpc5554
    3435
     
    4243nodist_include_HEADERS = include/bspopts.h ../../shared/tod.h \
    4344    ../../shared/include/coverhd.h
    44 include_bsp_HEADERS = include/mpc55xxevb.h \
    45     include/smsc9218i.h \
    46     include/mpc55xx-config.h \
    47     ../../../libcpu/powerpc/mpc83xx/i2c/mpc83xx_i2cdrv.h \
    48     ../../shared/include/irq-generic.h \
    49     ../../shared/include/irq-info.h \
    50     ../../shared/include/utility.h \
    51     ../shared/include/linker-symbols.h \
    52     ../shared/include/start.h \
    53     ../shared/include/tictac.h
     45include_bsp_HEADERS =
     46include_bsp_HEADERS += ../../../libcpu/powerpc/mpc83xx/i2c/mpc83xx_i2cdrv.h
     47include_bsp_HEADERS += ../../shared/include/irq-generic.h
     48include_bsp_HEADERS += ../../shared/include/irq-info.h
     49include_bsp_HEADERS += ../../shared/include/utility.h
     50include_bsp_HEADERS += ../shared/include/linker-symbols.h
     51include_bsp_HEADERS += ../shared/include/start.h
     52include_bsp_HEADERS += ../shared/include/tictac.h
     53include_bsp_HEADERS += include/mpc55xx-config.h
     54include_bsp_HEADERS += include/mpc55xxevb.h
     55include_bsp_HEADERS += include/smsc9218i.h
     56include_bsp_HEADERS += include/console-esci.h
     57include_bsp_HEADERS += include/console-generic.h
     58include_bsp_HEADERS += include/console-linflex.h
    5459
    5560# startup
     
    5964libbsp_a_SOURCES += ../../shared/bsppost.c
    6065libbsp_a_SOURCES += ../../shared/bsppredriverhook.c
    61 libbsp_a_SOURCES += ../../shared/bsppretaskinghook.c
    6266libbsp_a_SOURCES += ../../shared/bspgetworkarea.c
    6367libbsp_a_SOURCES += ../shared/src/bsp-start-zero.S
     
    6670libbsp_a_SOURCES += ../shared/startup/bspidle.c
    6771libbsp_a_SOURCES += startup/bspstart.c
    68 libbsp_a_SOURCES += startup/fmpll-syncr-vals.c
    6972libbsp_a_SOURCES += startup/exc-vector-base.S
    70 libbsp_a_SOURCES += startup/ebi-cs-config.c
    71 libbsp_a_SOURCES += startup/ebi-cal-cs-config.c
    72 libbsp_a_SOURCES += startup/mmu-config.c
    73 libbsp_a_SOURCES += startup/siu-pcr-config.c
    74 libbsp_a_SOURCES += startup/early-init.c
     73libbsp_a_SOURCES += startup/get-system-clock.c
    7574libbsp_a_SOURCES += startup/reset.c
     75libbsp_a_SOURCES += startup/start-config-clock.c
     76libbsp_a_SOURCES += startup/start-config-ebi-cs.c
     77libbsp_a_SOURCES += startup/start-config-ebi-cs-cal.c
     78libbsp_a_SOURCES += startup/start-config-mmu.c
     79libbsp_a_SOURCES += startup/start-config-mmu-early.c
     80libbsp_a_SOURCES += startup/start-config-siu-pcr.c
     81libbsp_a_SOURCES += startup/start-early.c
     82libbsp_a_SOURCES += startup/start-cache.S
     83libbsp_a_SOURCES += startup/start-clock.c
     84libbsp_a_SOURCES += startup/start-flash.S
     85libbsp_a_SOURCES += startup/start-watchdog.c
    7686
    7787# clock
    7888libbsp_a_SOURCES += clock/clock-config.c
     89
     90# console
     91libbsp_a_SOURCES += console/console-config.c
     92libbsp_a_SOURCES += console/console-esci.c
     93libbsp_a_SOURCES += console/console-generic.c
     94libbsp_a_SOURCES += console/console-linflex.c
    7995
    8096# irq_generic
     
    108124    ../../../libcpu/@RTEMS_CPU@/@RTEMS_CPU_MODEL@/emios.rel \
    109125    ../../../libcpu/@RTEMS_CPU@/@RTEMS_CPU_MODEL@/dspi.rel \
    110     ../../../libcpu/@RTEMS_CPU@/@RTEMS_CPU_MODEL@/esci.rel \
    111126    ../../../libcpu/@RTEMS_CPU@/@exceptions@/rtems-cpu.rel \
    112127    ../../../libcpu/@RTEMS_CPU@/@exceptions@/exc_bspsupport.rel \
  • c/src/lib/libbsp/powerpc/mpc55xxevb/README

    r9bf3a868 ra762dc2  
    1 OVERVIEW
    2 ========
     1Supported MCUs:
    32
    4 BSP NAME:           mpc55xxevb
    5 BOARD:              Freescale MPC5566 evaluation board MPC5566EVB
    6 BUS:                N/A
    7 CPU FAMILY:         ppc
    8 CPU:                PowerPC e200z6
    9 COPROCESSORS:       N/A
    10 MODE:               32 bit mode
     3 o MPC5516
     4 o MPC5554
     5 o MPC5566
     6 o MPC5643L
     7 o MPC5674F
    118
    12 PERIPHERALS
    13 ===========
     9Supported boards:
    1410
    15 TIMERS:             not yet supported
    16   RESOLUTION:       not yet supported
    17 SERIAL PORTS:       2 internal eSCI
    18 REAL-TIME CLOCK:    N/A
    19 DMA:                eDMA
    20 VIDEO:              N/A
    21 SCSI:               N/A
    22 NETWORKING:         FEC (not yet supported)
    23                     SMSC9218I (external)
    24 SPI:                DSPI
    25 
    26 DRIVER INFORMATION
    27 ==================
    28 
    29 CLOCK DRIVER:       EMIOS channel 23
    30 IOSUPP DRIVER:      N/A
    31 SHMSUPP:            N/A
    32 TIMER DRIVER:       not yet supported
    33 TTY DRIVER:         BSP
    34 
    35 STDIO
    36 =====
    37 
    38 PORT:               ESCI A
    39 ELECTRICAL:         N/A
    40 BAUD:               115200
    41 BITS PER CHARACTER: 8
    42 PARITY:             N
    43 STOP BITS:          1
    44 
    45 NOTES
    46 =====
    47 
    48 BUS WIDTH:          32 bit Flash, 32 bit SDRAM
    49 FLASH:              3 MByte
    50 INTERNAL RAM:       128 kByte SDRAM
    51 EXTERNAL RAM:       512 kByte SDRAM
    52 
    53 
    54 DEBUGGING / CODE LOADING
    55 ========================
    56 
    57 Tested using the Lauterbach TRACE32 ICD debugger.
    58 
    59 ISSUES
    60 ======
    61 
    62 The memory blocks allocated by LibBlock are in general not cache aligned so we
    63 cannot use DMA transfers.  This is suboptimal in combination with a SD Card and
    64 SPI.
     11 o embedded brains GmbH GWLCFM
     12 o phyCORE MPC5554
     13 o Freescale MPC5566EVB
     14 o Freescale XKT564L KIT
     15 o Axiom MPC567XADAT516 / MPC567XEVBFXMB
  • c/src/lib/libbsp/powerpc/mpc55xxevb/clock/clock-config.c

    r9bf3a868 ra762dc2  
    88
    99/*
    10  * Copyright (c) 2009
    11  * embedded brains GmbH
    12  * Obere Lagerstr. 30
    13  * D-82178 Puchheim
    14  * Germany
    15  * <rtems@embedded-brains.de>
     10 * Copyright (c) 2009-2011 embedded brains GmbH.  All rights reserved.
     11 *
     12 *  embedded brains GmbH
     13 *  Obere Lagerstr. 30
     14 *  82178 Puchheim
     15 *  Germany
     16 *  <rtems@embedded-brains.de>
    1617 *
    1718 * The license and distribution terms for this file may be
     
    2021 */
    2122
    22 #include <mpc55xx/regs.h>
    23 #include <mpc55xx/emios.h>
    24 
    25 #include <rtems.h>
    26 
    2723#include <bsp.h>
    2824#include <bsp/irq.h>
    2925
    30 #define RTEMS_STATUS_CHECKS_USE_PRINTK
    31 
    32 #include <rtems/status-checks.h>
    33 
    34 /* This is defined in clockdrv_shell.h */
    35 rtems_isr Clock_isr( rtems_vector_number vector);
    36 
    37 #define Clock_driver_support_at_tick() \
    38  do { \
    39     union EMIOS_CSR_tag csr = MPC55XX_ZERO_FLAGS; \
    40     csr.B.FLAG = 1; \
    41     EMIOS.CH [MPC55XX_CLOCK_EMIOS_CHANNEL].CSR.R = csr.R; \
    42  } while (0)
     26#include <mpc55xx/regs.h>
    4327
    4428static uint64_t mpc55xx_clock_factor;
    4529
    46 static void mpc55xx_clock_handler_install( rtems_isr_entry isr,
    47                                            rtems_isr_entry *old_isr)
     30#if defined(MPC55XX_CLOCK_EMIOS_CHANNEL)
     31
     32#include <mpc55xx/emios.h>
     33
     34static void mpc55xx_clock_at_tick(void)
     35{
     36  union EMIOS_CSR_tag csr = MPC55XX_ZERO_FLAGS;
     37  csr.B.FLAG = 1;
     38  EMIOS.CH [MPC55XX_CLOCK_EMIOS_CHANNEL].CSR.R = csr.R;
     39}
     40
     41static void mpc55xx_clock_handler_install(rtems_isr_entry isr)
    4842{
    4943  rtems_status_code sc = RTEMS_SUCCESSFUL;
    5044
    5145  sc = mpc55xx_interrupt_handler_install(
    52     MPC55XX_IRQ_EMIOS( MPC55XX_CLOCK_EMIOS_CHANNEL),
     46    MPC55XX_IRQ_EMIOS(MPC55XX_CLOCK_EMIOS_CHANNEL),
    5347    "clock",
    5448    RTEMS_INTERRUPT_UNIQUE,
     
    5751    NULL
    5852  );
    59  *old_isr = NULL;
    60   RTEMS_CHECK_SC_VOID( sc, "install clock interrupt handler");
    61 }
    62 
    63 static void mpc55xx_clock_initialize( void)
     53  if (sc != RTEMS_SUCCESSFUL) {
     54    rtems_fatal_error_occurred(0xdeadbeef);
     55  }
     56}
     57
     58static void mpc55xx_clock_initialize(void)
    6459{
    6560  volatile struct EMIOS_CH_tag *regs = &EMIOS.CH [MPC55XX_CLOCK_EMIOS_CHANNEL];
     
    6762  union EMIOS_CSR_tag csr = MPC55XX_ZERO_FLAGS;
    6863  unsigned prescaler = mpc55xx_emios_global_prescaler();
    69   uint64_t interval = ((uint64_t) bsp_clock_speed
    70     * (uint64_t) rtems_configuration_get_microseconds_per_tick()) / 1000000;
    71 
    72   mpc55xx_clock_factor = (1000000000ULL << 32) / bsp_clock_speed;
     64  uint64_t reference_clock = bsp_clock_speed;
     65  uint64_t us_per_tick = rtems_configuration_get_microseconds_per_tick();
     66  uint64_t interval = (reference_clock * us_per_tick) / 1000000;
     67
     68  mpc55xx_clock_factor = (1000000000ULL << 32) / reference_clock;
    7369
    7470  /* Apply prescaler */
     
    7672    interval /= (uint64_t) prescaler;
    7773  } else {
    78     RTEMS_SYSLOG_ERROR( "unexpected global eMIOS prescaler\n");
     74    rtems_fatal_error_occurred(0xdeadbeef);
    7975  }
    8076
    8177  /* Check interval */
    8278  if (interval == 0 || interval > MPC55XX_EMIOS_VALUE_MAX) {
    83     interval = MPC55XX_EMIOS_VALUE_MAX;
    84     RTEMS_SYSLOG_ERROR( "clock timer interval out of range\n");
     79    rtems_fatal_error_occurred(0xdeadbeef);
    8580  }
    8681
     
    10499
    105100  /* Set control register */
    106 #if MPC55XX_CHIP_TYPE / 10 == 551
    107   ccr.B.MODE = MPC55XX_EMIOS_MODE_MCB_UP_INT_CLK;
    108 #else
    109   ccr.B.MODE = MPC55XX_EMIOS_MODE_MC_UP_INT_CLK;
    110 #endif
     101  #if MPC55XX_CHIP_TYPE / 10 == 551
     102    ccr.B.MODE = MPC55XX_EMIOS_MODE_MCB_UP_INT_CLK;
     103  #else
     104    ccr.B.MODE = MPC55XX_EMIOS_MODE_MC_UP_INT_CLK;
     105  #endif
    111106  ccr.B.UCPREN = 1;
    112107  ccr.B.FEN = 1;
     
    115110}
    116111
    117 static void mpc55xx_clock_cleanup( void)
    118 {
    119   rtems_status_code sc = RTEMS_SUCCESSFUL;
     112static void mpc55xx_clock_cleanup(void)
     113{
    120114  volatile struct EMIOS_CH_tag *regs = &EMIOS.CH [MPC55XX_CLOCK_EMIOS_CHANNEL];
    121115  union EMIOS_CCR_tag ccr = MPC55XX_ZERO_FLAGS;
     
    124118  ccr.B.MODE = MPC55XX_EMIOS_MODE_GPIO_INPUT;
    125119  regs->CCR.R = ccr.R;
    126 
    127   /* Remove interrupt handler */
    128   sc = rtems_interrupt_handler_remove(
    129     MPC55XX_IRQ_EMIOS( MPC55XX_CLOCK_EMIOS_CHANNEL),
    130     (rtems_interrupt_handler) Clock_isr,
    131     NULL
    132   );
    133   RTEMS_CHECK_SC_VOID( sc, "remove clock interrupt handler");
    134 }
    135 
    136 static uint32_t mpc55xx_clock_nanoseconds_since_last_tick( void)
     120}
     121
     122static uint32_t mpc55xx_clock_nanoseconds_since_last_tick(void)
    137123{
    138124  volatile struct EMIOS_CH_tag *regs = &EMIOS.CH [MPC55XX_CLOCK_EMIOS_CHANNEL];
     
    148134}
    149135
    150 #define Clock_driver_support_initialize_hardware() mpc55xx_clock_initialize()
    151 
    152 #define Clock_driver_support_install_isr( isr, old_isr) \
    153   mpc55xx_clock_handler_install(isr,&old_isr)
    154 
    155 #define Clock_driver_support_shutdown_hardware() mpc55xx_clock_cleanup()
    156 
     136#elif defined(MPC55XX_CLOCK_PIT_CHANNEL)
     137
     138static void mpc55xx_clock_at_tick(void)
     139{
     140  volatile PIT_RTI_CHANNEL_tag *channel =
     141    &PIT_RTI.CHANNEL [MPC55XX_CLOCK_PIT_CHANNEL];
     142  PIT_RTI_TFLG_32B_tag tflg = { .B = { .TIF = 1 } };
     143
     144  channel->TFLG.R = tflg.R;
     145}
     146
     147static void mpc55xx_clock_handler_install(rtems_isr_entry isr)
     148{
     149  rtems_status_code sc = RTEMS_SUCCESSFUL;
     150
     151  sc = mpc55xx_interrupt_handler_install(
     152    MPC55XX_IRQ_PIT_CHANNEL(MPC55XX_CLOCK_PIT_CHANNEL),
     153    "clock",
     154    RTEMS_INTERRUPT_UNIQUE,
     155    MPC55XX_INTC_MIN_PRIORITY,
     156    (rtems_interrupt_handler) isr,
     157    NULL
     158  );
     159  if (sc != RTEMS_SUCCESSFUL) {
     160    rtems_fatal_error_occurred(0xdeadbeef);
     161  }
     162}
     163
     164static void mpc55xx_clock_initialize(void)
     165{
     166  volatile PIT_RTI_CHANNEL_tag *channel =
     167    &PIT_RTI.CHANNEL [MPC55XX_CLOCK_PIT_CHANNEL];
     168  uint64_t reference_clock = bsp_clock_speed;
     169  uint64_t us_per_tick = rtems_configuration_get_microseconds_per_tick();
     170  uint64_t interval = (reference_clock * us_per_tick) / 1000000;
     171  PIT_RTI_PITMCR_32B_tag pitmcr = { .B = { .FRZ = 1 } };
     172  PIT_RTI_TCTRL_32B_tag tctrl = { .B = { .TIE = 1, .TEN = 1 } };
     173
     174  mpc55xx_clock_factor = (1000000000ULL << 32) / reference_clock;
     175
     176  PIT_RTI.PITMCR.R = pitmcr.R;
     177  channel->LDVAL.R = interval;
     178  channel->TCTRL.R = tctrl.R;
     179}
     180
     181static void mpc55xx_clock_cleanup(void)
     182{
     183  volatile PIT_RTI_CHANNEL_tag *channel =
     184    &PIT_RTI.CHANNEL [MPC55XX_CLOCK_PIT_CHANNEL];
     185
     186  channel->TCTRL.R = 0;
     187}
     188
     189static uint32_t mpc55xx_clock_nanoseconds_since_last_tick(void)
     190{
     191  volatile PIT_RTI_CHANNEL_tag *channel =
     192    &PIT_RTI.CHANNEL [MPC55XX_CLOCK_PIT_CHANNEL];
     193  uint32_t c = channel->CVAL.R;
     194  uint32_t i = channel->LDVAL.R;
     195  uint64_t k = mpc55xx_clock_factor;
     196
     197  if (channel->TFLG.B.TIF != 0) {
     198    c = channel->CVAL.R - i;
     199  }
     200
     201  return (uint32_t) (((i - c) * k) >> 32);
     202}
     203
     204#endif
     205
     206#define Clock_driver_support_at_tick() \
     207  mpc55xx_clock_at_tick()
     208#define Clock_driver_support_initialize_hardware() \
     209  mpc55xx_clock_initialize()
     210#define Clock_driver_support_install_isr(isr, old_isr) \
     211  do { \
     212    mpc55xx_clock_handler_install(isr); \
     213    old_isr = NULL; \
     214  } while (0)
     215#define Clock_driver_support_shutdown_hardware() \
     216  mpc55xx_clock_cleanup()
    157217#define Clock_driver_nanoseconds_since_last_tick \
    158218  mpc55xx_clock_nanoseconds_since_last_tick
  • c/src/lib/libbsp/powerpc/mpc55xxevb/configure.ac

    r9bf3a868 ra762dc2  
    2525
    2626RTEMS_BSPOPTS_SET_DATA_CACHE_ENABLED([gwlcfm],[])
     27RTEMS_BSPOPTS_SET_DATA_CACHE_ENABLED([xkt564levb],[])
    2728RTEMS_BSPOPTS_SET_DATA_CACHE_ENABLED([mpc5566evb*],[1])
    2829RTEMS_BSPOPTS_SET_DATA_CACHE_ENABLED([mpc5674fevb*],[1])
     
    3738
    3839RTEMS_BSPOPTS_SET([BSP_INTERRUPT_HANDLER_TABLE_SIZE],[mpc5674fevb*],[255])
     40RTEMS_BSPOPTS_SET([BSP_INTERRUPT_HANDLER_TABLE_SIZE],[xkt564levb*],[127])
    3941RTEMS_BSPOPTS_SET([BSP_INTERRUPT_HANDLER_TABLE_SIZE],[mpc5566evb*],[127])
    4042RTEMS_BSPOPTS_SET([BSP_INTERRUPT_HANDLER_TABLE_SIZE],[*],[63])
     
    5153
    5254RTEMS_BSPOPTS_SET([MPC55XX_FMPLL_REF_CLOCK],[gwlcfm],[40000000])
     55RTEMS_BSPOPTS_SET([MPC55XX_FMPLL_REF_CLOCK],[xkt564levb*],[40000000])
    5356RTEMS_BSPOPTS_SET([MPC55XX_FMPLL_REF_CLOCK],[mpc5674fevb*],[40000000])
    5457RTEMS_BSPOPTS_SET([MPC55XX_FMPLL_REF_CLOCK],[*]     ,[8000000])
     
    7578[Must be defined to be the PLL multiplication factor for clock generation])
    7679
     80RTEMS_BSPOPTS_SET([MPC55XX_EMIOS_PRESCALER],[xkt564levb*],[])
    7781RTEMS_BSPOPTS_SET([MPC55XX_EMIOS_PRESCALER],[gwlcfm],[66])
    7882RTEMS_BSPOPTS_SET([MPC55XX_EMIOS_PRESCALER],[*]     ,[1])
     
    97101
    98102RTEMS_BSPOPTS_SET([MPC55XX_CLOCK_EMIOS_CHANNEL],[mpc5674fevb*],[31])
     103RTEMS_BSPOPTS_SET([MPC55XX_CLOCK_EMIOS_CHANNEL],[xkt564levb*],[])
    99104RTEMS_BSPOPTS_SET([MPC55XX_CLOCK_EMIOS_CHANNEL],[*],[23])
    100105RTEMS_BSPOPTS_HELP([MPC55XX_CLOCK_EMIOS_CHANNEL],
    101106[selects the eMIOS channel for the RTEMS system tick (the default is the last channel)])
    102107
     108RTEMS_BSPOPTS_SET([MPC55XX_CLOCK_PIT_CHANNEL],[xkt564levb*],[3])
     109RTEMS_BSPOPTS_SET([MPC55XX_CLOCK_PIT_CHANNEL],[*],[])
     110RTEMS_BSPOPTS_HELP([MPC55XX_CLOCK_PIT_CHANNEL],
     111[selects the PIT channel for the RTEMS system tick (the default is the last channel)])
     112
    103113RTEMS_BSPOPTS_SET([MPC55XX_CHIP_TYPE],[mpc5674fevb*],[5674])
     114RTEMS_BSPOPTS_SET([MPC55XX_CHIP_TYPE],[xkt564levb*],[5643])
    104115RTEMS_BSPOPTS_SET([MPC55XX_CHIP_TYPE],[mpc5566evb*],[5566])
    105116RTEMS_BSPOPTS_SET([MPC55XX_CHIP_TYPE],[gwlcfm]    ,[5516])
     
    107118RTEMS_BSPOPTS_HELP([MPC55XX_CHIP_TYPE],
    108119[specifies the chip type in use (e.g. 5554 for MPC5554)])
     120
     121RTEMS_BSPOPTS_SET([MPC55XX_EARLY_STACK_SIZE],[*],[1024])
     122RTEMS_BSPOPTS_HELP([MPC55XX_EARLY_STACK_SIZE],
     123[size of the early initialization stack in bytes])
    109124
    110125RTEMS_BSPOPTS_SET([MPC55XX_BOOTFLAGS],[*],[])
     
    114129RTEMS_BSPOPTS_SET([MPC55XX_BOARD_MPC5674FEVB],[mpc5674fevb*],[1])
    115130RTEMS_BSPOPTS_HELP([MPC55XX_BOARD_MPC5674FEVB],[if defined, use custom settings for MPC5674FEVB board])
     131
     132RTEMS_BSPOPTS_SET([MPC55XX_BOARD_XKT564LEVB],[xkt564levb*],[1])
     133RTEMS_BSPOPTS_HELP([MPC55XX_BOARD_XKT564LEVB],[if defined, use custom settings for XKT564LEVB board])
    116134
    117135RTEMS_BSPOPTS_SET([MPC55XX_BOARD_MPC5566EVB],[mpc5566evb*],[1])
  • c/src/lib/libbsp/powerpc/mpc55xxevb/include/mpc55xx-config.h

    r9bf3a868 ra762dc2  
    44 * @ingroup mpc55xx
    55 *
    6  * @brief MPC55XX low-level configuration.
     6 * @brief Low-level configuration.
    77 */
    88
     
    2828#include <stddef.h>
    2929
     30#include <libcpu/powerpc-utility.h>
     31
     32#include <bsp/start.h>
     33
    3034#include <mpc55xx/regs.h>
    3135#include <mpc55xx/regs-mmu.h>
     
    3943  uint16_t count;
    4044  union SIU_PCR_tag pcr;
    41 } mpc55xx_siu_pcr_config_entry;
     45} mpc55xx_siu_pcr_config;
    4246
    43 extern const mpc55xx_siu_pcr_config_entry mpc55xx_siu_pcr_config [];
     47extern const mpc55xx_siu_pcr_config mpc55xx_start_config_siu_pcr [];
    4448
    45 extern const size_t mpc55xx_siu_pcr_config_count [];
     49extern const size_t mpc55xx_start_config_siu_pcr_count [];
    4650
    47 extern const struct MMU_tag mpc55xx_mmu_config [];
     51extern const struct MMU_tag mpc55xx_start_config_mmu_early [];
    4852
    49 extern const size_t mpc55xx_mmu_config_count [];
     53extern const size_t mpc55xx_start_config_mmu_early_count [];
    5054
    51 extern const struct EBI_CS_tag mpc55xx_ebi_cs_config [];
     55extern const struct MMU_tag mpc55xx_start_config_mmu [];
    5256
    53 extern const size_t mpc55xx_ebi_cs_config_count [];
     57extern const size_t mpc55xx_start_config_mmu_count [];
    5458
    55 extern const struct EBI_CAL_CS_tag mpc55xx_ebi_cal_cs_config [];
     59#ifdef MPC55XX_HAS_FMPLL
     60  typedef struct {
     61    union FMPLL_SYNCR_tag syncr_tmp;
     62    union FMPLL_SYNCR_tag syncr_final;
     63  } mpc55xx_clock_config;
     64#endif
    5665
    57 extern const size_t mpc55xx_ebi_cal_cs_config_count [];
     66#ifdef MPC55XX_HAS_FMPLL_ENHANCED
     67  typedef struct {
     68    union FMPLL_ESYNCR2_tag esyncr2_tmp;
     69    union FMPLL_ESYNCR2_tag esyncr2_final;
     70    union FMPLL_ESYNCR1_tag esyncr1_final;
     71  } mpc55xx_clock_config;
     72#endif
    5873
    59 void mpc55xx_early_init(void);
     74#ifdef MPC55XX_HAS_MODE_CONTROL
     75  typedef struct {
     76    struct {
     77      PLLD_CR_32B_tag cr;
     78      PLLD_MR_32B_tag mr;
     79    } fmpll [2];
     80    CGM_OC_EN_32B_tag oc_en;
     81    CGM_OCDS_SC_32B_tag ocds_sc;
     82    CGM_SC_DC0_3_32B_tag sc_dc0_3;
     83    CGM_AUXCLK_tag auxclk [5];
     84  } mpc55xx_clock_config;
     85#endif
     86
     87extern const mpc55xx_clock_config mpc55xx_start_config_clock [];
     88
     89#ifdef MPC55XX_HAS_EBI
     90  extern const struct EBI_CS_tag mpc55xx_start_config_ebi_cs [];
     91
     92  extern const size_t mpc55xx_start_config_ebi_cs_count [];
     93
     94  extern const struct EBI_CAL_CS_tag mpc55xx_start_config_ebi_cal_cs [];
     95
     96  extern const size_t mpc55xx_start_config_ebi_cal_cs_count [];
     97#endif
     98
     99void mpc55xx_start_early(void);
     100
     101void mpc55xx_start_flash(void);
     102
     103void mpc55xx_start_cache(void);
     104
     105void mpc55xx_start_clock(void);
     106
     107void mpc55xx_start_watchdog(void);
     108
     109void mpc55xx_start_mmu_apply_config(const struct MMU_tag *config, size_t count);
     110
     111uint32_t mpc55xx_get_system_clock(void);
     112
     113LINKER_SYMBOL(bsp_ram_start)
     114LINKER_SYMBOL(bsp_ram_end)
     115LINKER_SYMBOL(bsp_ram_size)
     116
     117LINKER_SYMBOL(bsp_ram_1_start)
     118LINKER_SYMBOL(bsp_ram_1_end)
     119LINKER_SYMBOL(bsp_ram_1_size)
     120
     121LINKER_SYMBOL(bsp_rom_start)
     122LINKER_SYMBOL(bsp_rom_end)
     123LINKER_SYMBOL(bsp_rom_size)
     124
     125#ifdef MPC55XX_BOOTFLAGS
     126  extern uint32_t mpc55xx_bootflag_0 [];
     127#endif
    60128
    61129#ifdef __cplusplus
  • c/src/lib/libbsp/powerpc/mpc55xxevb/network/smsc9218i.c

    r9bf3a868 ra762dc2  
    2323 */
    2424
     25#include <rtems.h>
     26
     27#ifdef RTEMS_NETWORKING
     28
    2529#define __INSIDE_RTEMS_BSD_TCPIP_STACK__ 1
    2630#define __BSD_VISIBLE 1
     
    3539#include <inttypes.h>
    3640
    37 #include <rtems.h>
    3841#include <rtems/rtems_bsdnet.h>
    3942#include <rtems/rtems_mii_ioctl.h>
     
    19101913  return 0;
    19111914}
     1915
     1916#endif /* RTEMS_NETWORKING */
  • c/src/lib/libbsp/powerpc/mpc55xxevb/preinstall.am

    r9bf3a868 ra762dc2  
    7878PREINSTALL_FILES += $(PROJECT_LIB)/linkcmds.mpc5674fevb_spe
    7979
     80$(PROJECT_LIB)/linkcmds.xkt564levb: startup/linkcmds.xkt564levb $(PROJECT_LIB)/$(dirstamp)
     81        $(INSTALL_DATA) $< $(PROJECT_LIB)/linkcmds.xkt564levb
     82PREINSTALL_FILES += $(PROJECT_LIB)/linkcmds.xkt564levb
     83
    8084$(PROJECT_LIB)/linkcmds.phycore_mpc5554: startup/linkcmds.phycore_mpc5554 $(PROJECT_LIB)/$(dirstamp)
    8185        $(INSTALL_DATA) $< $(PROJECT_LIB)/linkcmds.phycore_mpc5554
     
    101105        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/coverhd.h
    102106PREINSTALL_FILES += $(PROJECT_INCLUDE)/coverhd.h
    103 
    104 $(PROJECT_INCLUDE)/bsp/mpc55xxevb.h: include/mpc55xxevb.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
    105         $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/mpc55xxevb.h
    106 PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/mpc55xxevb.h
    107 
    108 $(PROJECT_INCLUDE)/bsp/smsc9218i.h: include/smsc9218i.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
    109         $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/smsc9218i.h
    110 PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/smsc9218i.h
    111 
    112 $(PROJECT_INCLUDE)/bsp/mpc55xx-config.h: include/mpc55xx-config.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
    113         $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/mpc55xx-config.h
    114 PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/mpc55xx-config.h
    115107
    116108$(PROJECT_INCLUDE)/bsp/mpc83xx_i2cdrv.h: ../../../libcpu/powerpc/mpc83xx/i2c/mpc83xx_i2cdrv.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
     
    142134PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/tictac.h
    143135
     136$(PROJECT_INCLUDE)/bsp/mpc55xx-config.h: include/mpc55xx-config.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
     137        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/mpc55xx-config.h
     138PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/mpc55xx-config.h
     139
     140$(PROJECT_INCLUDE)/bsp/mpc55xxevb.h: include/mpc55xxevb.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
     141        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/mpc55xxevb.h
     142PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/mpc55xxevb.h
     143
     144$(PROJECT_INCLUDE)/bsp/smsc9218i.h: include/smsc9218i.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
     145        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/smsc9218i.h
     146PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/smsc9218i.h
     147
     148$(PROJECT_INCLUDE)/bsp/console-esci.h: include/console-esci.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
     149        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/console-esci.h
     150PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/console-esci.h
     151
     152$(PROJECT_INCLUDE)/bsp/console-generic.h: include/console-generic.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
     153        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/console-generic.h
     154PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/console-generic.h
     155
     156$(PROJECT_INCLUDE)/bsp/console-linflex.h: include/console-linflex.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
     157        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/console-linflex.h
     158PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/console-linflex.h
     159
  • c/src/lib/libbsp/powerpc/mpc55xxevb/startup/bspstart.c

    r9bf3a868 ra762dc2  
    4444#include <bsp/mpc55xx-config.h>
    4545
     46extern Heap_Control *RTEMS_Malloc_Heap;
     47
    4648/* Symbols defined in linker command file */
    47 LINKER_SYMBOL(bsp_ram_start);
    48 LINKER_SYMBOL(bsp_ram_end);
    49 LINKER_SYMBOL(bsp_external_ram_start);
    50 LINKER_SYMBOL(bsp_external_ram_size);
    5149LINKER_SYMBOL(mpc55xx_exc_vector_base);
    5250
     
    148146
    149147        mpc55xx_edma_init();
    150         mpc55xx_emios_initialize(MPC55XX_EMIOS_PRESCALER);
     148        #ifdef MPC55XX_EMIOS_PRESCALER
     149                mpc55xx_emios_initialize(MPC55XX_EMIOS_PRESCALER);
     150        #endif
    151151}
     152
     153void bsp_pretasking_hook(void)
     154{
     155        #if MPC55XX_CHIP_TYPE / 10 == 564
     156                _Heap_Extend(
     157                        RTEMS_Malloc_Heap,
     158                        bsp_section_rwextra_end,
     159                        (uintptr_t) bsp_ram_end
     160                                - (uintptr_t) bsp_section_rwextra_end,
     161                        NULL
     162                );
     163        #endif
     164}
  • c/src/lib/libbsp/powerpc/mpc55xxevb/startup/reset.c

    r9bf3a868 ra762dc2  
    3232{
    3333  while (true) {
    34     SIU.SRCR.R = 0x1;
     34    #if MPC55XX_CHIP_TYPE / 10 == 564
     35      /* TODO */
     36    #else
     37      SIU.SRCR.R = 1U << (31 - 0);
     38    #endif
    3539  }
    3640}
  • c/src/lib/libbsp/powerpc/mpc55xxevb/startup/sd-card-init.c

    r9bf3a868 ra762dc2  
    2929#include <rtems/status-checks.h>
    3030
     31#ifdef MPC55XX_BOARD_MPC5566EVB
     32
    3133static rtems_status_code mpc55xx_dspi_init(void)
    3234{
     
    3941        RTEMS_CHECK_RV_SC( rv, "rtems_libi2c_initialize");
    4042
    41 #if MPC55XX_CHIP_TYPE / 10 != 551
    4243        /* DSPI D inputs are taken from DSPI C */
    4344        SIU.DISR.R = 0x000000FC;
    44 #endif
    4545
    4646        /* DSPI A signals */
     
    159159        return RTEMS_SUCCESSFUL;
    160160}
     161
     162#endif /* MPC55XX_BOARD_MPC5566EVB */
  • c/src/lib/libbsp/powerpc/mpc55xxevb/startup/start-config-ebi-cs-cal.c

    r9bf3a868 ra762dc2  
    44 * @ingroup mpc55xx
    55 *
    6  * @brief MPC55XX EBI calibration chip-select configuration.
     6 * @brief EBI calibration chip-select configuration.
    77 */
    88
     
    2020 * http://www.rtems.com/license/LICENSE.
    2121 *
    22  * $Id$
     22 * $Id: ebi-cal-cs-config.c,v 1.1 2011/08/31 16:03:09 sh Exp $
    2323 */
    2424
     
    2727#include <bsp.h>
    2828
    29 const BSP_START_TEXT_SECTION struct EBI_CAL_CS_tag
    30 mpc55xx_ebi_cal_cs_config [] = {
     29#ifdef MPC55XX_HAS_EBI
     30
     31BSP_START_TEXT_SECTION const struct EBI_CAL_CS_tag
     32  mpc55xx_start_config_ebi_cal_cs [] = {
    3133#if defined(MPC55XX_BOARD_MPC5674FEVB)
     34  /* External SRAM */
    3235  {
    3336    .BR = {
     
    5154      }
    5255    }
     56  },
     57  /* External Ethernet controller */
     58  {
     59    .BR = {
     60      .B = {
     61        .BA = 0x3fff8000 >> 15,
     62        .PS = 0,
     63        .AD_MUX = 1,
     64        .BL = 0,
     65        .WEBS = 0,
     66        .TBDIP = 0,
     67        .SETA = 0,
     68        .BI = 1,
     69        .V = 1
     70      }
     71    },
     72    .OR = {
     73      .B = {
     74        .AM = 0xfff80000 >> 15,
     75        .SCY = 1,
     76        .BSCY = 0
     77      }
     78    }
    5379  }
    5480#endif
    5581};
    5682
    57 const BSP_START_TEXT_SECTION size_t mpc55xx_ebi_cal_cs_config_count [] = {
    58   sizeof(mpc55xx_ebi_cal_cs_config) / sizeof(mpc55xx_ebi_cal_cs_config [0])
     83BSP_START_TEXT_SECTION const size_t mpc55xx_start_config_ebi_cal_cs_count [] = {
     84  sizeof(mpc55xx_start_config_ebi_cal_cs) / sizeof(mpc55xx_start_config_ebi_cal_cs [0])
    5985};
     86
     87#endif /* MPC55XX_HAS_EBI */
  • c/src/lib/libbsp/powerpc/mpc55xxevb/startup/start-config-ebi-cs.c

    r9bf3a868 ra762dc2  
    44 * @ingroup mpc55xx
    55 *
    6  * @brief MPC55XX EBI chip-select configuration.
     6 * @brief EBI chip-select configuration.
    77 */
    88
     
    2020 * http://www.rtems.com/license/LICENSE.
    2121 *
    22  * $Id$
     22 * $Id: ebi-cs-config.c,v 1.1 2011/08/31 16:03:09 sh Exp $
    2323 */
    2424
     
    2727#include <bsp.h>
    2828
    29 const BSP_START_TEXT_SECTION struct EBI_CS_tag
    30 mpc55xx_ebi_cs_config [] = {
     29#ifdef MPC55XX_HAS_EBI
     30
     31BSP_START_TEXT_SECTION const struct EBI_CS_tag
     32  mpc55xx_start_config_ebi_cs [] = {
    3133#if defined(MPC55XX_BOARD_GWLCFM)
    3234        /* CS0: External SRAM (16 bit, 1 wait states, 512kB, no burst) */
     
    8890            .B.WEBS = 0,
    8991            .B.TBDIP = 0,
    90             .B.BI = 1, 
     92            .B.BI = 1,
    9193            .B.V = 1
    9294        },
     
    138140            .B.BSCY = 0
    139141        }
    140     }, 
     142    },
    141143    { { .R = 0 }, { .R = 0 } },   /* CS1: Unused. */
    142144    { { .R = 0 }, { .R = 0 } },   /* CS2: Unused. */
     
    161163};
    162164
    163 const BSP_START_TEXT_SECTION size_t mpc55xx_ebi_cs_config_count [] = {
    164   sizeof(mpc55xx_ebi_cs_config) / sizeof(mpc55xx_ebi_cs_config [0])
     165BSP_START_TEXT_SECTION const size_t mpc55xx_start_config_ebi_cs_count [] = {
     166  sizeof(mpc55xx_start_config_ebi_cs) / sizeof(mpc55xx_start_config_ebi_cs [0])
    165167};
     168
     169#endif /* MPC55XX_HAS_EBI */
  • c/src/lib/libbsp/powerpc/mpc55xxevb/startup/start-config-mmu.c

    r9bf3a868 ra762dc2  
    44 * @ingroup mpc55xx
    55 *
    6  * @brief MPC55XX MMU configuration.
     6 * @brief MMU configuration.
    77 */
    88
     
    1919 * found in the file LICENSE in this distribution or at
    2020 * http://www.rtems.com/license/LICENSE.
    21  *
    22  * $Id$
    2321 */
    2422
     23#include <bsp.h>
     24#include <bsp/start.h>
    2525#include <bsp/mpc55xx-config.h>
    26 #include <bsp/start.h>
    27 #include <bsp.h>
    2826
    29 const BSP_START_TEXT_SECTION struct MMU_tag
    30 mpc55xx_mmu_config [] = {
     27BSP_START_TEXT_SECTION const struct MMU_tag
     28  mpc55xx_start_config_mmu [] = {
    3129#if defined(MPC55XX_BOARD_GWLCFM)
    3230  /* External Ethernet Controller 64k */
    33   MPC55XX_MMU_TAG_INITIALIZER(5, 0x3fff8000, 6, 0, 1, 1, 1)
     31  MPC55XX_MMU_TAG_INITIALIZER(5, 0x3fff8000, MPC55XX_MMU_64K, 0, 1, 1, 1)
    3432#elif defined(MPC55XX_BOARD_PHYCORE_MPC5554)
    35     /* XXX I'm not using TLB1 entry 2 the same way as 
     33    /* XXX I'm not using TLB1 entry 2 the same way as
    3634         * in the BAM.
    3735     */
     
    8886#elif defined(MPC55XX_BOARD_MPC5566EVB)
    8987  /* Internal flash 3M */
    90   MPC55XX_MMU_TAG_INITIALIZER(1, 0x00000000, 6, 1, 0, 1, 0),
    91   MPC55XX_MMU_TAG_INITIALIZER(5, 0x00010000, 6, 1, 0, 1, 0),
    92   MPC55XX_MMU_TAG_INITIALIZER(6, 0x00020000, 6, 1, 0, 1, 0),
    93   MPC55XX_MMU_TAG_INITIALIZER(7, 0x00030000, 6, 1, 0, 1, 0),
    94   MPC55XX_MMU_TAG_INITIALIZER(8, 0x00040000, 8, 1, 0, 1, 0),
    95   MPC55XX_MMU_TAG_INITIALIZER(9, 0x00080000, 8, 1, 0, 1, 0),
    96   MPC55XX_MMU_TAG_INITIALIZER(10, 0x000c0000, 8, 1, 0, 1, 0),
    97   MPC55XX_MMU_TAG_INITIALIZER(11, 0x00100000, 10, 1, 0, 1, 0),
    98   MPC55XX_MMU_TAG_INITIALIZER(12, 0x00200000, 10, 1, 0, 1, 0),
     88  MPC55XX_MMU_TAG_INITIALIZER(1, 0x00000000, MPC55XX_MMU_64K, 1, 0, 1, 0),
     89  MPC55XX_MMU_TAG_INITIALIZER(5, 0x00010000, MPC55XX_MMU_64K, 1, 0, 1, 0),
     90  MPC55XX_MMU_TAG_INITIALIZER(6, 0x00020000, MPC55XX_MMU_64K, 1, 0, 1, 0),
     91  MPC55XX_MMU_TAG_INITIALIZER(7, 0x00030000, MPC55XX_MMU_64K, 1, 0, 1, 0),
     92  MPC55XX_MMU_TAG_INITIALIZER(8, 0x00040000, MPC55XX_MMU_256K, 1, 0, 1, 0),
     93  MPC55XX_MMU_TAG_INITIALIZER(9, 0x00080000, MPC55XX_MMU_256K, 1, 0, 1, 0),
     94  MPC55XX_MMU_TAG_INITIALIZER(10, 0x000c0000, MPC55XX_MMU_256K, 1, 0, 1, 0),
     95  MPC55XX_MMU_TAG_INITIALIZER(11, 0x00100000, MPC55XX_MMU_1M, 1, 0, 1, 0),
     96  MPC55XX_MMU_TAG_INITIALIZER(12, 0x00200000, MPC55XX_MMU_1M, 1, 0, 1, 0),
    9997  /* External SRAM 512k */
    100   MPC55XX_MMU_TAG_INITIALIZER(2, 0x20000000, 8, 0, 1, 1, 0),
    101   MPC55XX_MMU_TAG_INITIALIZER(13, 0x20040000, 8, 0, 1, 1, 0),
     98  MPC55XX_MMU_TAG_INITIALIZER(2, 0x20000000, MPC55XX_MMU_256K, 0, 1, 1, 0),
     99  MPC55XX_MMU_TAG_INITIALIZER(13, 0x20040000, MPC55XX_MMU_256K, 0, 1, 1, 0),
    102100  /* Internal SRAM 128k */
    103   MPC55XX_MMU_TAG_INITIALIZER(3, 0x40010000, 6, 0, 1, 1, 0),
    104   MPC55XX_MMU_TAG_INITIALIZER(14, 0x40000000, 6, 0, 1, 1, 0),
     101  MPC55XX_MMU_TAG_INITIALIZER(3, 0x40010000, MPC55XX_MMU_64K, 0, 1, 1, 0),
     102  MPC55XX_MMU_TAG_INITIALIZER(14, 0x40000000, MPC55XX_MMU_64K, 0, 1, 1, 0),
    105103  /* External Ethernet Controller 64k */
    106   MPC55XX_MMU_TAG_INITIALIZER(15, 0x3fff8000, 6, 0, 1, 1, 1)
     104  MPC55XX_MMU_TAG_INITIALIZER(15, 0x3fff8000, MPC55XX_MMU_64K, 0, 1, 1, 1)
    107105#elif defined(MPC55XX_BOARD_MPC5674FEVB)
    108106  /* Internal flash 4M */
    109   MPC55XX_MMU_TAG_INITIALIZER(1, 0x00000000, 6, 1, 0, 1, 0),
    110   MPC55XX_MMU_TAG_INITIALIZER(5, 0x00010000, 6, 1, 0, 1, 0),
    111   MPC55XX_MMU_TAG_INITIALIZER(6, 0x00020000, 7, 1, 0, 1, 0),
    112   MPC55XX_MMU_TAG_INITIALIZER(7, 0x00040000, 8, 1, 0, 1, 0),
    113   MPC55XX_MMU_TAG_INITIALIZER(8, 0x00080000, 9, 1, 0, 1, 0),
    114   MPC55XX_MMU_TAG_INITIALIZER(9, 0x00100000, 10, 1, 0, 1, 0),
    115   MPC55XX_MMU_TAG_INITIALIZER(10, 0x00200000, 11, 1, 0, 1, 0),
     107  MPC55XX_MMU_TAG_INITIALIZER(1, 0x00000000, MPC55XX_MMU_64K, 1, 0, 1, 0),
     108  MPC55XX_MMU_TAG_INITIALIZER(5, 0x00010000, MPC55XX_MMU_64K, 1, 0, 1, 0),
     109  MPC55XX_MMU_TAG_INITIALIZER(6, 0x00020000, MPC55XX_MMU_128K, 1, 0, 1, 0),
     110  MPC55XX_MMU_TAG_INITIALIZER(7, 0x00040000, MPC55XX_MMU_256K, 1, 0, 1, 0),
     111  MPC55XX_MMU_TAG_INITIALIZER(8, 0x00080000, MPC55XX_MMU_512K, 1, 0, 1, 0),
     112  MPC55XX_MMU_TAG_INITIALIZER(9, 0x00100000, MPC55XX_MMU_1M, 1, 0, 1, 0),
     113  MPC55XX_MMU_TAG_INITIALIZER(10, 0x00200000, MPC55XX_MMU_2M, 1, 0, 1, 0),
    116114  /* External SRAM 512k */
    117   MPC55XX_MMU_TAG_INITIALIZER(2, 0x20000000, 9, 0, 1, 1, 0),
     115  MPC55XX_MMU_TAG_INITIALIZER(2, 0x20000000, MPC55XX_MMU_512K, 0, 1, 1, 0),
    118116  /* Internal SRAM 256k */
    119   MPC55XX_MMU_TAG_INITIALIZER(3, 0x40000000, 8, 0, 1, 1, 0)
     117  MPC55XX_MMU_TAG_INITIALIZER(3, 0x40000000, MPC55XX_MMU_256K, 0, 1, 1, 0),
     118  /* External Ethernet controller */
     119  MPC55XX_MMU_TAG_INITIALIZER(15, 0x3fff8000, MPC55XX_MMU_64K, 0, 1, 1, 1)
     120#elif MPC55XX_CHIP_TYPE / 10 == 564
     121  /* Internal flash 1M */
     122  MPC55XX_MMU_TAG_INITIALIZER(0, 0x00000000, MPC55XX_MMU_1M, 1, 0, 1, 0),
     123  /* IO */
     124  MPC55XX_MMU_TAG_INITIALIZER(1, 0xffe00000, MPC55XX_MMU_2M, 0, 1, 1, 1),
     125  MPC55XX_MMU_TAG_INITIALIZER(2, 0xc3f00000, MPC55XX_MMU_1M, 0, 1, 1, 1),
     126  /* Internal SRAM 64k + 64k */
     127  MPC55XX_MMU_TAG_INITIALIZER(3, 0x40000000, MPC55XX_MMU_64K, 0, 1, 1, 0),
     128  MPC55XX_MMU_TAG_INITIALIZER(4, 0x50000000, MPC55XX_MMU_64K, 0, 1, 1, 0)
    120129#endif
    121130};
    122131
    123 const BSP_START_TEXT_SECTION size_t mpc55xx_mmu_config_count [] = {
    124   sizeof(mpc55xx_mmu_config) / sizeof(mpc55xx_mmu_config [0])
     132BSP_START_TEXT_SECTION const size_t mpc55xx_start_config_mmu_count [] = {
     133  sizeof(mpc55xx_start_config_mmu) / sizeof(mpc55xx_start_config_mmu [0])
    125134};
  • c/src/lib/libbsp/powerpc/mpc55xxevb/startup/start-config-siu-pcr.c

    r9bf3a868 ra762dc2  
    44 * @ingroup mpc55xx
    55 *
    6  * @brief MPC55XX SIU PCR configuration.
     6 * @brief SIU PCR configuration.
    77 */
    88
     
    2020 * http://www.rtems.com/license/LICENSE.
    2121 *
    22  * $Id$
     22 * $Id: siu-pcr-config.c,v 1.1 2011/08/31 16:03:10 sh Exp $
    2323 */
    2424
     
    2727#include <bsp.h>
    2828
    29 const BSP_START_TEXT_SECTION mpc55xx_siu_pcr_config_entry
    30 mpc55xx_siu_pcr_config [] = {
     29BSP_START_TEXT_SECTION const mpc55xx_siu_pcr_config
     30  mpc55xx_start_config_siu_pcr [] = {
    3131#if defined(MPC55XX_BOARD_GWLCFM)
    3232  {  0,16,{.B.PA = 1,           .B.WPE = 0}}, /* PA[ 0..15] analog input */
     
    5757  { 54, 1,{.B.PA = 1,.B.OBE = 1,.B.WPE = 0}}, /* PD[ 6    ] HS_CAN_TX out */
    5858  { 55, 1,{.B.PA = 1,.B.IBE = 1,.B.WPE = 0}}, /* PD[ 7    ] HS_CAN_RX in  */
    59   { 56, 1,{.B.PA = 2,.B.IBE = 1,.B.OBE = 1,.B.WPE = 0}}, 
     59  { 56, 1,{.B.PA = 2,.B.IBE = 1,.B.OBE = 1,.B.WPE = 0}},
    6060  /* PD[ 8    ] I2C_SCL in/out */
    61   { 57, 1,{.B.PA = 2,.B.IBE = 1,.B.OBE = 1,.B.WPE = 0}}, 
     61  { 57, 1,{.B.PA = 2,.B.IBE = 1,.B.OBE = 1,.B.WPE = 0}},
    6262  /* PD[ 9    ] I2C_SDA in/out */
    63  
     63
    6464  { 58, 1,{.B.PA = 0,.B.OBE = 1,.B.WPE = 0}}, /* PD[10] LS_CAN_EN     out*/
    65   { 59, 3,{.B.PA = 0,.B.IBE = 1,.B.WPE = 0}}, 
     65  { 59, 3,{.B.PA = 0,.B.IBE = 1,.B.WPE = 0}},
    6666  /* PD[11..13] PWO1_OC, MOCO_INT in */
    67  
     67
    6868  { 62, 4,{.B.PA = 0,.B.IBE = 1,.B.WPE = 0}}, /* PD[14..15] USB_FLGA/B    in */
    6969
     
    100100  {  4,24,{.B.PA = 1,.B.DSC = 1                  }}, /* ADDR [8 : 31] */
    101101  { 28,16,{.B.PA = 1,.B.DSC = 1                  }}, /* DATA [0 : 15] */
    102   { 62, 8,{.B.PA = 1,.B.DSC = 1,.B.WPE=1,.B.WPS=1}}, /* RD_!WR, BDIP, 
     102  { 62, 8,{.B.PA = 1,.B.DSC = 1,.B.WPE=1,.B.WPS=1}}, /* RD_!WR, BDIP,
    103103                                                        !WE, !OE, !TS */
    104104  { 89, 2,{.B.PA = 1                             }} /* ESCI_B        */
     
    111111  { 278, 16, { .B = { .PA = 1, .DSC = 1 } } }, /* D_ADD_DAT0 .. D_ADD_DAT15 */
    112112  { 294,  6, { .B = { .PA = 1, .DSC = 1 } } }, /* D_RD_WR, D_WE0, D_WE1, D_OE, D_TS, D_ALE */
     113  { 301,  1, { .B = { .PA = 1, .DSC = 1 } } }, /* D_CS1 */
    113114  { 302,  6, { .B = { .PA = 1, .DSC = 1 } } } /* D_BDIP, D_WE2, D_WE3, D_ADD9 .. D_ADD11 */
    114115#endif
    115116};
    116117
    117 const BSP_START_TEXT_SECTION size_t mpc55xx_siu_pcr_config_count [] = {
    118   sizeof(mpc55xx_siu_pcr_config) / sizeof(mpc55xx_siu_pcr_config [0])
     118BSP_START_TEXT_SECTION const size_t mpc55xx_start_config_siu_pcr_count [] = {
     119  sizeof(mpc55xx_start_config_siu_pcr) / sizeof(mpc55xx_start_config_siu_pcr [0])
    119120};
  • c/src/lib/libbsp/powerpc/mpc55xxevb/startup/start-flash.S

    r9bf3a868 ra762dc2  
    2020 * http://www.rtems.com/license/LICENSE.
    2121 *
    22  * $Id$
     22 * $Id: flash.S,v 1.2 2011/08/31 15:50:30 sh Exp $
    2323 */
    2424
     
    2626#include <mpc55xx/reg-defs.h>
    2727
    28 .section ".bsp_start_text", "ax"
     28        .section        ".bsp_start_text", "ax"
    2929
    3030/* Optimized flash configurations (Table 13-15 [MPC5567 Microcontroller Reference Manual]) */
     
    3636
    3737/**
    38  * @fn void mpc55xx_flash_init()
     38 * @fn void mpc55xx_start_flash()
    3939 * @brief Optimized flash configuration.
    40  * @warning Code will be copied and executed on the stack.  The stack pointer
    41  * will not be updated, since this function has to work before memory
    42  * initialization.
     40 * @warning Code will be copied and executed on the stack.
    4341 */
    44 GLOBAL_FUNCTION mpc55xx_flash_init
    45         mflr r31
     42GLOBAL_FUNCTION mpc55xx_start_flash
     43#if MPC55XX_CHIP_TYPE / 10 == 564
     44        blr
     45#else
     46        .equ    stack_size, 20
     47        .equ    lr_offset, 28
     48
     49        /* Reserve stack frame */
     50        stwu    r1, -stack_size(r1)
     51        mflr    r0
     52        stw     r0, lr_offset(r1)
    4653
    4754        /* Flash settings dependent on system clock */
    48         bl mpc55xx_get_system_clock
    49         LWI r4, 82000000
    50         cmpw r3, r4
    51         ble clock_82
    52         LWI r4, 102000000
    53         cmpw r3, r4
    54         ble clock_102
    55         LWI r4, 132000000
    56         cmpw r3, r4
    57         ble clock_132
    58         LWI r4, 264000000
    59         cmpw r3, r4
    60         ble clock_264
    61         LWI r30, FLASH_SETTINGS_RESET
    62         b settings_done
     55        bl      mpc55xx_get_system_clock
     56        LWI     r4, 82000000
     57        cmpw    r3, r4
     58        ble     clock_82
     59        LWI     r4, 102000000
     60        cmpw    r3, r4
     61        ble     clock_102
     62        LWI     r4, 132000000
     63        cmpw    r3, r4
     64        ble     clock_132
     65        LWI     r4, 264000000
     66        cmpw    r3, r4
     67        ble     clock_264
     68        LWI     r3, FLASH_SETTINGS_RESET
     69        b       settings_done
    6370clock_82:
    64         LWI r30, FLASH_SETTINGS_82
    65         b settings_done
     71        LWI     r3, FLASH_SETTINGS_82
     72        b       settings_done
    6673clock_102:
    67         LWI r30, FLASH_SETTINGS_102
    68         b settings_done
     74        LWI     r3, FLASH_SETTINGS_102
     75        b       settings_done
    6976clock_132:
    70         LWI r30, FLASH_SETTINGS_132
     77        LWI     r3, FLASH_SETTINGS_132
    7178        b settings_done
    7279clock_264:
    73         LWI r30, FLASH_SETTINGS_264
    74         b settings_done
     80        LWI     r3, FLASH_SETTINGS_264
     81        b       settings_done
    7582settings_done:
    7683
    7784        /* Copy store code on the stack */
    78         LA r3, store_start
    79         LA r5, store_end
    80         subf r5, r3, r5
    81         subf r4, r5, r1
    82 
    83         /* Assert: Proper alignment of destination start */
    84         andi. r6, r4, 0x7
    85         bne twiddle
    86 
    87         /* Copy */
    88         bl mpc55xx_copy_8
    89 
    90         LA r6, FLASH_BIUCR
     85        LA      r4, store_start
     86        lwz     r6, 0(r4)
     87        lwz     r7, 4(r4)
     88        lwz     r8, 8(r4)
     89        stw     r6, 8(r1)
     90        stw     r7, 12(r1)
     91        stw     r8, 16(r1)
    9192
    9293        /* Execute store code */
    93         mtctr r4
     94        LA      r4, FLASH_BIUCR
     95        addi    r5, r1, 8
     96        mtctr   r5
    9497        bctrl
    9598
    96         mtlr r31
     99        /* Return */
     100        lwz     r0, lr_offset(r1)
     101        addi    r1, r1, stack_size
     102        mtlr    r0
    97103        blr
    98104
     
    101107 */
    102108
    103         .align 3
    104         .set store_start, .
    105         stw r30, 0(r6)
     109store_start:
     110
     111        stw     r3, 0(r4)
    106112        isync
    107113        blr
    108         .align 3
    109         .set store_end, .
    110114
    111 twiddle:
    112         b twiddle
     115#endif
  • c/src/lib/libbsp/powerpc/mpc55xxevb/startup/start.S

    r9bf3a868 ra762dc2  
    1919 * found in the file LICENSE in this distribution or at
    2020 * http://www.rtems.com/license/LICENSE.
    21  *
    22  * $Id$
    2321 */
    2422
    25 /**
    26  * @defgroup mpc55xx_asm Assembler files
    27  *
    28  * @ingroup mpc55xx
    29  */
    30 
    3123#include <bspopts.h>
    3224
    3325#include <libcpu/powerpc-utility.h>
    3426
    35 #include <mpc55xx/reg-defs.h>
    36 
    37 #include <bsp/vectors.h>
    38 
    39 #define HAS_CACHE (BSP_DATA_CACHE_ENABLED || BSP_INSTRUCTION_CACHE_ENABLED)
    40 
    41         .extern mpc55xx_fmpll_config
    42         .extern mpc55xx_fmpll_init
    43         .extern mpc55xx_flash_init
    44         .extern mpc55xx_early_init
    45         .extern bsp_start_zero
    46         .extern bsp_ram_start
    47         .extern bsp_ram_size
    48         .extern bsp_ram_end
    49         .extern __eabi
    50         .extern boot_card
    51 
    52         .globl _start
    53        
     27#if MPC55XX_CHIP_TYPE / 10 != 551
     28  #define HAS_SPE
     29#endif
     30
     31#if MPC55XX_CHIP_TYPE / 10 == 564
     32  #define INIT_REGISTERS_FOR_LSM
     33#endif
     34
     35#ifdef HAS_SPE
     36  #define ZERO_GPR(reg) evxor   reg, reg, reg
     37#else
     38  #define ZERO_GPR(reg) xor     reg, reg, reg
     39#endif
     40
     41        .extern __eabi
     42        .extern boot_card
     43        .extern bsp_ram_start
     44        .extern bsp_section_data_begin
     45        .extern bsp_section_data_load_begin
     46        .extern bsp_section_data_size
     47        .extern bsp_section_fast_data_begin
     48        .extern bsp_section_fast_data_load_begin
     49        .extern bsp_section_fast_data_size
     50        .extern bsp_section_fast_text_begin
     51        .extern bsp_section_fast_text_load_begin
     52        .extern bsp_section_fast_text_size
     53        .extern mpc55xx_start_config_mmu_early
     54        .extern mpc55xx_start_config_mmu_early_count
     55        .extern mpc55xx_start_early
     56
     57        .globl  _start
     58        .globl  mpc55xx_start_mmu_apply_config
     59
    5460#ifdef MPC55XX_BOOTFLAGS
    55         .globl mpc55xx_bootflag_0
    56         .globl mpc55xx_bootflag_1
    57 #endif
    58 
    59         .section ".bsp_start_text", "ax"
     61        .globl  mpc55xx_bootflag_0
     62        .globl  mpc55xx_bootflag_1
     63#endif
     64
     65        .section        ".bsp_start_text", "ax"
    6066
    6167        /* BAM: RCHW */
    62         .int 0x005a0000
     68        .int    0x005a0000
    6369
    6470        /* BAM: Address of start instruction */
    65         .int _start
     71        .int    _start
    6672
    6773#ifdef MPC55XX_BOOTFLAGS
    68         /*
    69         * We skip over the next two boot flag words to the next 64-bit
    70         * aligned start address. It is 64-bit aligned to play well with
    71         * FLASH programming.  These boot flags can be set by debuggers
    72         * and emulators to customize boot.  Currently bit0 of
    73         * bootflag_0 means to "skip setting up the MMU", allowing
    74         * external MMU setup in a debugger before branching to 0x10.
    75         * This can be used e.g., to map FLASH into RAM.
    76         */
     74        /*
     75        * We skip over the next two boot flag words to the next 64-bit
     76        * aligned start address. It is 64-bit aligned to play well with
     77        * FLASH programming.  These boot flags can be set by debuggers
     78        * and emulators to customize boot.  Currently bit0 of
     79        * bootflag_0 means to "skip setting up the MMU", allowing
     80        * external MMU setup in a debugger before branching to 0x10.
     81        * This can be used e.g., to map FLASH into RAM.
     82        */
    7783mpc55xx_bootflag_0:
    78         .int 0xffffffff
     84        .int    0xffffffff
    7985mpc55xx_bootflag_1:
    80         .int 0xffffffff
     86        .int    0xffffffff
    8187#endif
    8288
    8389_start:
    8490
     91        /* Enable SPE */
     92#ifdef HAS_SPE
     93        mfmsr   r3
     94        oris    r3, r3, MSR_SPE >> 16
     95        mtmsr   r3
     96        isync
     97#endif
     98
     99        /*
     100         * Initialization of core registers according to "e200z4 Power
     101         * Architecture Core Reference Manual" section 2.6 "Reset Settings"
     102         * table 2-16 "Reset Settings of e200 Resources".  This is necessary
     103         * for lock step mode (LSM).
     104         */
     105        ZERO_GPR(r0)
     106#ifdef INIT_REGISTERS_FOR_LSM
     107        ZERO_GPR(r1)
     108        ZERO_GPR(r2)
     109        ZERO_GPR(r4)
     110        ZERO_GPR(r5)
     111        ZERO_GPR(r6)
     112        ZERO_GPR(r7)
     113        ZERO_GPR(r8)
     114        ZERO_GPR(r9)
     115        ZERO_GPR(r10)
     116        ZERO_GPR(r11)
     117        ZERO_GPR(r12)
     118        ZERO_GPR(r13)
     119        ZERO_GPR(r14)
     120        ZERO_GPR(r15)
     121        ZERO_GPR(r16)
     122        ZERO_GPR(r17)
     123        ZERO_GPR(r18)
     124        ZERO_GPR(r19)
     125        ZERO_GPR(r20)
     126        ZERO_GPR(r21)
     127        ZERO_GPR(r22)
     128        ZERO_GPR(r23)
     129        ZERO_GPR(r24)
     130        ZERO_GPR(r25)
     131        ZERO_GPR(r26)
     132        ZERO_GPR(r27)
     133        ZERO_GPR(r28)
     134        ZERO_GPR(r29)
     135        ZERO_GPR(r30)
     136        ZERO_GPR(r31)
     137        mtcrf   0xff, r0
     138        mtcsrr0 r0
     139        mtcsrr1 r0
     140        mtctr   r0
     141        mtspr   FSL_EIS_DBCNT, r0
     142        mtspr   DEAR_BOOKE, r0
     143        mtdec   r0
     144        mtspr   BOOKE_DECAR, r0
     145        mtspr   FSL_EIS_DSRR0, r0
     146        mtspr   FSL_EIS_DSRR1, r0
     147        mtspr   BOOKE_DVC1, r0
     148        mtspr   BOOKE_DVC2, r0
     149        mtspr   BOOKE_IVPR, r0
     150        mtlr    r0
     151        mtspr   FSL_EIS_MCAR, r0
     152        mtmcsrr0        r0
     153        mtmcsrr1        r0
     154        mtspr   SPRG0, r0
     155        mtspr   SPRG1, r0
     156        mtspr   SPRG2, r0
     157        mtspr   SPRG3, r0
     158        mtspr   SPRG4, r0
     159        mtspr   SPRG5, r0
     160        mtspr   SPRG6, r0
     161        mtspr   SPRG7, r0
     162        mtspr   FSL_EIS_SPRG8, r0
     163        mtspr   FSL_EIS_SPRG9, r0
     164        mtsrr0  r0
     165        mtsrr1  r0
     166        mtspr   USPRG0, r0
     167#ifdef HAS_SPE
     168        evmra   r0, r0
     169#endif
     170#endif /* INIT_REGISTERS_FOR_LSM */
     171        mtspr   TBWL, r0
     172        mtspr   TBWU, r0
     173
    85174        /* Enable time base */
    86         li      r0, 0
    87         mtspr   TBWU, r0
    88         mtspr   TBWL, r0
    89         mfspr   r2, HID0
    90         ori     r2, r2, 0x4000
    91         mtspr   HID0, r2
    92 
    93         /* FMPLL setup */
    94         LWI     r3, mpc55xx_fmpll_config
    95         bl      mpc55xx_fmpll_init
     175        mfspr   r3, HID0
     176        ori     r3, r3, 0x4000
     177        mtspr   HID0, r3
    96178
    97179        /* Enable branch prediction */
    98         LWI     r2, BUCSR_BBFI | BUCSR_BPEN
    99         mtspr   BUCSR, r2
    100 
    101         /* Set intermediate stack start to end of internal SRAM */
    102         LA      r1, bsp_ram_end
    103         subi    r1, r1, 16
    104 
    105         /* Enable SPE */
    106         mfmsr   r2
    107         oris    r2, r2, 0x200
    108         mtmsr   r2
    109 
    110         /* Config internal flash */
    111         bl      mpc55xx_flash_init
    112 
    113 #if HAS_CACHE
    114         bl config_cache
    115 
    116         /* Enable cache in the MMU for the internal SRAM */
    117         LWI     r3, 0x10030000
    118         mtspr   FSL_EIS_MAS0, r3
    119         tlbre
    120         LWI     r4, ~0x00000008
    121         mfspr   r3, FSL_EIS_MAS2
    122         and     r3, r3, r4
    123         mtspr   FSL_EIS_MAS2, r3
    124         tlbwe
    125 #endif
    126 
    127         /* Zero internal SRAM (needed to get proper ECC) */
     180        LWI     r3, FSL_EIS_BUCSR_BBFI | FSL_EIS_BUCSR_BPEN
     181        mtspr   FSL_EIS_BUCSR, r3
     182
     183        /* MMU early initialization */
     184        LA      r3, mpc55xx_start_config_mmu_early
     185        LW      r4, mpc55xx_start_config_mmu_early_count
     186        bl      mpc55xx_start_mmu_apply_config
     187
     188        /* Initialize intermediate stack (ECC) */
     189
    128190        LA      r3, bsp_ram_start
    129         LA      r4, bsp_ram_size
    130         bl      bsp_start_zero
    131 
    132         /* Initialize intermediate start stack */
    133         li      r0, 0
    134         stw     r0, 0(r1)
    135         stw     r0, 4(r1)
    136 
    137         /* Do early initialization */
    138         bl      mpc55xx_early_init
    139 
    140         /* Set up EABI and SYSV environment */
    141         bl      __eabi
     191        addi    r4, r3, MPC55XX_EARLY_STACK_SIZE
     192
     193zero_intermediate_stack_loop:
     194
     195#ifdef HAS_SPE
     196        evstdd  r0, 0(r3)
     197        evstdd  r0, 8(r3)
     198        evstdd  r0, 16(r3)
     199        evstdd  r0, 24(r3)
     200#else
     201        stw     r0, 0(r3)
     202        stw     r0, 4(r3)
     203        stw     r0, 8(r3)
     204        stw     r0, 12(r3)
     205        stw     r0, 16(r3)
     206        stw     r0, 20(r3)
     207        stw     r0, 24(r3)
     208        stw     r0, 28(r3)
     209#endif
     210        addi    r3, r3, 32
     211        cmpw    cr7, r3, r4
     212        bne     cr7, zero_intermediate_stack_loop
     213        subi    r1, r3, 16
     214
     215        /* Next steps in C */
     216        bl      mpc55xx_start_early
    142217
    143218        /* Initialize start stack */
    144         LWI     r1, start_stack_end
     219        LA      r1, start_stack_end
    145220        subi    r1, r1, 16
    146221        li      r0, 0
    147222        stw     r0, 0(r1)
    148223
     224        /* Load sections */
     225        LA      r3, bsp_section_fast_text_begin
     226        LA      r4, bsp_section_fast_text_load_begin
     227        LA      r5, bsp_section_fast_text_size
     228        bl      load_section
     229        LA      r3, bsp_section_fast_data_begin
     230        LA      r4, bsp_section_fast_data_load_begin
     231        LA      r5, bsp_section_fast_data_size
     232        bl      load_section
     233        LA      r3, bsp_section_data_begin
     234        LA      r4, bsp_section_data_load_begin
     235        LA      r5, bsp_section_data_size
     236        bl      load_section
     237
     238        /* Set up EABI and SYSV environment */
     239        bl      __eabi
     240
    149241        /* Clear command line */
    150242        li      r3, 0
     
    155247        /* Spin around */
    156248twiddle:
     249
    157250        b       twiddle
    158251
    159 #if HAS_CACHE
    160 config_cache:
    161 
    162         /* Load zero, CINV, and CABT) */
    163         li      r0, 0
    164         li      r3, 0x2
    165         li      r4, 0x4
    166 
    167 #if MPC55XX_CHIP_TYPE / 10 == 567
    168 start_instruction_cache_invalidation:
    169 
    170         /* Clear instruction cache invalidation abort */
    171         mtspr   FSL_EIS_L1CSR1, r0
    172 
    173         /* Start instruction cache invalidation */
    174         mtspr   FSL_EIS_L1CSR1, r3
    175 
    176 get_instruction_cache_invalidation_status:
    177 
    178         /* Get instruction cache invalidation status */
    179         mfspr   r5, FSL_EIS_L1CSR1
    180 
    181         /* Check CABT */
    182         and.    r6, r5, r4
    183         bne     start_instruction_cache_invalidation
    184 
    185         /* Check CINV */
    186         and.    r6, r5, r3
    187         bne     get_instruction_cache_invalidation_status
    188 
    189         /* Save instruction cache settings */
    190         LWI     r6, 0x00010001
    191         isync
    192         msync
    193         mtspr   FSL_EIS_L1CSR1, r6
    194 #endif /* MPC55XX_CHIP_TYPE / 10 == 567 */
    195 
    196 start_data_cache_invalidation:
    197 
    198         /* Clear data cache invalidation abort */
    199         mtspr   FSL_EIS_L1CSR0, r0
    200 
    201         /* Start data cache invalidation */
    202         mtspr   FSL_EIS_L1CSR0, r3
    203 
    204 get_data_cache_invalidation_status:
    205 
    206         /* Get data cache invalidation status */
    207         mfspr   r5, FSL_EIS_L1CSR0
    208 
    209         /* Check CABT */
    210         and.    r6, r5, r4
    211         bne     start_data_cache_invalidation
    212 
    213         /* Check CINV */
    214         and.    r6, r5, r3
    215         bne     get_data_cache_invalidation_status
    216 
    217         /* Save data cache settings */
    218 #if MPC55XX_CHIP_TYPE / 10 != 567
    219         /* FIXME: CORG??? 0x00180011 */
    220         LWI     r6, 0x00100001
    221 #else
    222         LWI     r6, 0x00190001
    223 #endif
    224         isync
    225         msync
    226         mtspr   FSL_EIS_L1CSR0, r6
    227 
    228         /* Return */
     252mpc55xx_start_mmu_apply_config:
     253
     254        cmpwi   cr7, r4, r0
     255        beqlr   cr7
     256        mtctr   r4
     257
     258mmu_init_loop:
     259
     260        lwz     r4, 0(r3)
     261        lwz     r5, 4(r3)
     262        lwz     r6, 8(r3)
     263        lwz     r7, 12(r3)
     264        mtspr   FSL_EIS_MAS0, r4
     265        mtspr   FSL_EIS_MAS1, r5
     266        mtspr   FSL_EIS_MAS2, r6
     267        mtspr   FSL_EIS_MAS3, r7
     268        tlbwe
     269        addi    r3, r3, 16
     270        bdnz    mmu_init_loop
    229271        blr
    230 #endif /* HAS_CACHE */
     272
     273load_section:
     274        cmpw    cr7, r3, r4
     275        beqlr   cr7
     276        b       memcpy
    231277
    232278        /* Start stack area */
    233         .section ".bsp_rwextra", "aw", @nobits
    234         .align 4
    235         .space 4096
     279
     280        .section        ".bsp_rwextra", "aw", @nobits
     281        .align  4
     282        .space  4096
     283
    236284start_stack_end:
  • c/src/lib/libcpu/powerpc/Makefile.am

    r9bf3a868 ra762dc2  
    419419include_mpc55xx_HEADERS += mpc55xx/include/emios.h
    420420include_mpc55xx_HEADERS += mpc55xx/include/mpc55xx.h
    421 include_mpc55xx_HEADERS += mpc55xx/include/esci.h
    422421include_mpc55xx_HEADERS += mpc55xx/include/siu.h
    423422include_mpc55xx_HEADERS += mpc55xx/include/irq.h
     
    426425include_mpc55xx_HEADERS += mpc55xx/include/fsl-mpc555x.h
    427426include_mpc55xx_HEADERS += mpc55xx/include/fsl-mpc556x.h
     427include_mpc55xx_HEADERS += mpc55xx/include/fsl-mpc564xL.h
    428428include_mpc55xx_HEADERS += mpc55xx/include/fsl-mpc567x.h
    429429include_mpc55xx_HEADERS += mpc55xx/include/regs-edma.h
     
    463463mpc55xx_siu_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
    464464
    465 # eSCI
    466 noinst_PROGRAMS += mpc55xx/esci.rel
    467 mpc55xx_esci_rel_SOURCES = mpc55xx/esci/esci.c
    468 mpc55xx_esci_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
    469 
    470465# DSPI
    471466noinst_PROGRAMS += mpc55xx/dspi.rel
     
    476471noinst_PROGRAMS += mpc55xx/misc.rel
    477472mpc55xx_misc_rel_SOURCES = mpc55xx/misc/copy.S \
    478         mpc55xx/misc/fmpll.S \
    479         mpc55xx/misc/flash.S \
    480473        mpc55xx/misc/flash_support.c
    481474mpc55xx_misc_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
  • c/src/lib/libcpu/powerpc/mpc55xx/dspi/dspi.c

    r9bf3a868 ra762dc2  
    748748                .idle_char = 0xffffffff,
    749749                .baud = 0
     750#ifdef DSPI_D
    750751        }, {
    751752                /* DSPI D */
     
    776777                .idle_char = 0xffffffff,
    777778                .baud = 0
     779#endif
    778780        }
    779781};
  • c/src/lib/libcpu/powerpc/mpc55xx/edma/edma.c

    r9bf3a868 ra762dc2  
    88
    99/*
    10  * Copyright (c) 2008
    11  * Embedded Brains GmbH
    12  * Obere Lagerstr. 30
    13  * D-82178 Puchheim
    14  * Germany
    15  * rtems@embedded-brains.de
     10 * Copyright (c) 2008-2011 embedded brains GmbH.  All rights reserved.
    1611 *
    17  * The license and distribution terms for this file may be found in the file
    18  * LICENSE in this distribution or at http://www.rtems.com/license/LICENSE.
     12 *  embedded brains GmbH
     13 *  Obere Lagerstr. 30
     14 *  82178 Puchheim
     15 *  Germany
     16 *  <rtems@embedded-brains.de>
     17 *
     18 * The license and distribution terms for this file may be
     19 * found in the file LICENSE in this distribution or at
     20 * http://www.rtems.com/license/LICENSE.
    1921 */
    2022
     
    2931
    3032#if MPC55XX_CHIP_TYPE / 10 == 551
     33  #define EDMA_CHANNEL_COUNT 16U
     34#elif MPC55XX_CHIP_TYPE / 10 == 564
    3135  #define EDMA_CHANNEL_COUNT 16U
    3236#elif MPC55XX_CHIP_TYPE / 10 == 567
  • c/src/lib/libcpu/powerpc/mpc55xx/emios/emios.c

    r9bf3a868 ra762dc2  
    88
    99/*
    10  * Copyright (c) 2009
    11  * embedded brains GmbH
    12  * Obere Lagerstr. 30
    13  * D-82178 Puchheim
    14  * Germany
    15  * <rtems@embedded-brains.de>
     10 * Copyright (c) 2009-2011 embedded brains GmbH.  All rights reserved.
     11 *
     12 *  embedded brains GmbH
     13 *  Obere Lagerstr. 30
     14 *  82178 Puchheim
     15 *  Germany
     16 *  <rtems@embedded-brains.de>
    1617 *
    1718 * The license and distribution terms for this file may be
     
    2021 */
    2122
    22 #include <mpc55xx/regs.h>
    2323#include <mpc55xx/emios.h>
    24 #include <mpc55xx/mpc55xx.h>
    2524
    26 #include <bsp/irq.h>
    27 #include <bsp/utility.h>
    28 
    29 #define RTEMS_STATUS_CHECKS_USE_PRINTK
    30 
    31 #include <rtems/status-checks.h>
     25#ifdef MPC55XX_HAS_EMIOS
    3226
    3327/**
     
    108102  EMIOS.MCR.R = mcr.R;
    109103}
     104
     105#endif /* MPC55XX_HAS_EMIOS */
  • c/src/lib/libcpu/powerpc/mpc55xx/include/emios.h

    r9bf3a868 ra762dc2  
    88
    99/*
    10  * Copyright (c) 2009
    11  * embedded brains GmbH
    12  * Obere Lagerstr. 30
    13  * D-82178 Puchheim
    14  * Germany
    15  * <rtems@embedded-brains.de>
     10 * Copyright (c) 2009-2011 embedded brains GmbH.  All rights reserved.
     11 *
     12 *  embedded brains GmbH
     13 *  Obere Lagerstr. 30
     14 *  82178 Puchheim
     15 *  Germany
     16 *  <rtems@embedded-brains.de>
    1617 *
    1718 * The license and distribution terms for this file may be
     
    2324#define LIBCPU_POWERPC_MPC55XX_EMIOS_H
    2425
    25 #include <stdbool.h>
    26 #include <stdint.h>
    27 
    28 #include <rtems.h>
    29 #include <rtems/chain.h>
    30 
    31 #include <bspopts.h>
     26#include <mpc55xx/regs.h>
    3227
    3328#ifdef __cplusplus
    3429extern "C" {
    3530#endif /* __cplusplus */
     31
     32#ifdef MPC55XX_HAS_EMIOS
    3633
    3734/**
     
    192189void mpc55xx_emios_set_global_prescaler( unsigned prescaler);
    193190
     191#endif /* MPC55XX_HAS_EMIOS */
     192
    194193#ifdef __cplusplus
    195194}
  • c/src/lib/libcpu/powerpc/mpc55xx/include/fsl-mpc551x.h

    r9bf3a868 ra762dc2  
    5252#ifndef _MPC5510_H_
    5353#define _MPC5510_H_
     54
     55#ifndef ASM
    5456
    5557#include <stdint.h>
     
    39703972}
    39713973#endif
     3974#endif /* ASM */
    39723975#endif                          /* ifdef _MPC5510_H */
    39733976/*********************************************************************
  • c/src/lib/libcpu/powerpc/mpc55xx/include/fsl-mpc555x.h

    r9bf3a868 ra762dc2  
    104104#define _MPC5554_H_
    105105
     106#ifndef ASM
     107
    106108#include <stdint.h>
    107109
     
    33483350}
    33493351#endif
     3352#endif /* ASM */
    33503353#endif                          /* ifdef _MPC5554_H */
    33513354/*********************************************************************
  • c/src/lib/libcpu/powerpc/mpc55xx/include/fsl-mpc556x.h

    r9bf3a868 ra762dc2  
    7070#ifndef _MPC5567_H_
    7171#define _MPC5567_H_
     72
     73#ifndef ASM
    7274
    7375#include <stdint.h>
     
    45284530}
    45294531#endif
     4532#endif /* ASM */
    45304533#endif                          /* ifdef _MPC5567_H */
    45314534/*********************************************************************
  • c/src/lib/libcpu/powerpc/mpc55xx/include/fsl-mpc567x.h

    r9bf3a868 ra762dc2  
    6060#ifndef _MPC5674F_H_
    6161#define _MPC5674F_H_
     62
     63#ifndef ASM
    6264
    6365#include <stdint.h>
     
    65936595}
    65946596#endif
     6597#endif /* ASM */
    65956598#endif                          /* ifdef _MPC5674_H */
    65966599/*********************************************************************
  • c/src/lib/libcpu/powerpc/mpc55xx/include/irq.h

    r9bf3a868 ra762dc2  
    88
    99/*
    10  * Copyright (c) 2008, 2010
    11  * Embedded Brains GmbH
    12  * Obere Lagerstr. 30
    13  * D-82178 Puchheim
    14  * Germany
    15  * rtems@embedded-brains.de
     10 * Copyright (c) 2008-2011 embedded brains GmbH.  All rights reserved.
    1611 *
    17  * The license and distribution terms for this file may be found in the file
    18  * LICENSE in this distribution or at http://www.rtems.com/license/LICENSE.
     12 *  embedded brains GmbH
     13 *  Obere Lagerstr. 30
     14 *  82178 Puchheim
     15 *  Germany
     16 *  <rtems@embedded-brains.de>
     17 *
     18 * The license and distribution terms for this file may be
     19 * found in the file LICENSE in this distribution or at
     20 * http://www.rtems.com/license/LICENSE.
    1921 */
    2022
     
    110112  #define MPC55XX_IRQ_FLEXRAY_BASE(mod) \
    111113    ((mod) == 0 ? 284U : MPC55XX_IRQ_INVALID)
     114#elif MPC55XX_CHIP_TYPE / 10 == 564
     115  #define MPC55XX_IRQ_MAX 255U
     116
     117  /* eDMA */
     118  #define MPC55XX_IRQ_EDMA_ERROR(group) \
     119    ((group) == 0 ? 10U : MPC55XX_IRQ_INVALID)
     120  #define MPC55XX_IRQ_EDMA(ch) \
     121    ((unsigned) (ch) < 16U ? 11U + (ch) : MPC55XX_IRQ_INVALID)
     122
     123  /* SWT */
     124  #define MPC55XX_IRQ_SWT_0 28U
     125  #define MPC55XX_IRQ_SWT_1 29U
     126
     127  /* STM */
     128  #define MPC55XX_IRQ_STM_CHANNEL(ch) ((ch) + 30U)
     129
     130  /* ECSM */
     131  #define MPC55XX_IRQ_ECSM_FAS 9U
     132  #define MPC55XX_IRQ_ECSM_NCE 35U
     133  #define MPC55XX_IRQ_ECSM_COR 36U
     134
     135  /* MC */
     136  #define MPC55XX_IRQ_MC_ME_SAFE_MODE 51U
     137  #define MPC55XX_IRQ_MC_ME_MODE_TRANSITION 52U
     138  #define MPC55XX_IRQ_MC_ME_INVALID_MODE 53U
     139  #define MPC55XX_IRQ_MC_ME_INVALID_CONFIG 54U
     140  #define MPC55XX_IRQ_MC_RGM_FRAE 56U
     141
     142  /* XOSC */
     143  #define MPC55XX_IRQ_XOSC 57U
     144
     145  /* PIT */
     146  #define MPC55XX_IRQ_PIT_CHANNEL(ch) \
     147    ((ch) == 3 ? 127U : ((ch) + 59U))
     148
     149  /* SIU external interrupts */
     150  #define MPC55XX_IRQ_SIU_EXTERNAL_0 41U
     151  #define MPC55XX_IRQ_SIU_EXTERNAL_1 42U
     152  #define MPC55XX_IRQ_SIU_EXTERNAL_2 43U
     153  #define MPC55XX_IRQ_SIU_EXTERNAL_3 44U
     154
     155  /* ADC */
     156  #define MPC55XX_IRQ_ADC_BASE(mod) \
     157    ((mod) == 0 ? 62U : \
     158      ((mod) == 1 ? 82U : MPC55XX_IRQ_INVALID))
     159
     160  /* DSPI */
     161  #define MPC55XX_IRQ_DSPI_BASE(mod) \
     162    ((mod) == 0 ? 74U : \
     163      ((mod) == 1 ? 94U : \
     164        ((mod) == 2 ? 114U : MPC55XX_IRQ_INVALID)))
     165
     166  /* FlexCAN */
     167  #define MPC55XX_IRQ_CAN_BASE(mod) \
     168    ((mod) == 0 ? 65U : \
     169      ((mod) == 1 ? 85U : MPC55XX_IRQ_INVALID))
     170
     171  /* FlexPWM */
     172  #define MPC55XX_IRQ_FLEXPWM_BASE(mod) \
     173    ((mod) == 0 ? 179U : \
     174      ((mod) == 1 ? 233U : MPC55XX_IRQ_INVALID))
     175
     176  /* FlexRay */
     177  #define MPC55XX_IRQ_FLEXRAY_BASE(mod) \
     178    ((mod) == 0 ? 131U : MPC55XX_IRQ_INVALID)
     179
     180  /* LINFlexD */
     181  #define MPC55XX_IRQ_LINFLEX_BASE(mod) \
     182    ((mod) == 0 ? 79U : \
     183      ((mod) == 1 ? 99U : MPC55XX_IRQ_INVALID))
     184
     185  /* eTimer */
     186  #define MPC55XX_IRQ_ETIMER_BASE(mod) \
     187    ((mod) == 0 ? 157U : \
     188      ((mod) == 1 ? 168U : \
     189        ((mod) == 2 ? 222U : MPC55XX_IRQ_INVALID)))
     190
     191  /* CTU */
     192  #define MPC55XX_IRQ_CTU_MRS 193U
     193  #define MPC55XX_IRQ_CTU_T(idx) ((idx) + 194U)
     194  #define MPC55XX_IRQ_CTU_FIFO(idx) ((idx) + 202U)
     195  #define MPC55XX_IRQ_CTU_ADC 206U
     196  #define MPC55XX_IRQ_CTU_ERR 207U
     197
     198  /* SEMA */
     199  #define MPC55XX_IRQ_SEMA_0 247U
     200  #define MPC55XX_IRQ_SEMA_1 248U
     201
     202  /* FCCU */
     203  #define MPC55XX_IRQ_FCCU_ALRM 250U
     204  #define MPC55XX_IRQ_FCCU_CFG_TO 251U
     205  #define MPC55XX_IRQ_FCCU_SC_RCC0_F 252U
     206  #define MPC55XX_IRQ_FCCU_SC_RCC1_F 253U
     207
     208  /* PMU */
     209  #define MPC55XX_IRQ_PMU 254U
     210
     211  /* SWG */
     212  #define MPC55XX_IRQ_SWG 255U
    112213#else
    113214  #if MPC55XX_CHIP_TYPE / 10 == 555
     
    188289
    189290#define MPC55XX_IRQ_NUMBER (MPC55XX_IRQ_MAX + 1U)
     291
     292/* ADC */
     293#define MPC55XX_IRQ_ADC_EOC(mod) \
     294  (MPC55XX_IRQ_ADC_BASE(mod) + 0U)
     295#define MPC55XX_IRQ_ADC_ER(mod) \
     296  (MPC55XX_IRQ_ADC_BASE(mod) + 1U)
     297#define MPC55XX_IRQ_ADC_WD(mod) \
     298  (MPC55XX_IRQ_ADC_BASE(mod) + 2U)
     299
     300/* eTimer */
     301#define MPC55XX_IRQ_ETIMER_TC(mod, ch) \
     302  (MPC55XX_IRQ_ETIMER_BASE(mod) + (ch))
     303#define MPC55XX_IRQ_ETIMER_WTIF(mod) \
     304  (MPC55XX_IRQ_ETIMER_BASE(mod) + 8U)
     305#define MPC55XX_IRQ_ETIMER_RCF(mod) \
     306  (MPC55XX_IRQ_ETIMER_BASE(mod) + 10U)
    190307
    191308/* eTPU */
     
    220337
    221338/* FlexCAN */
    222 #define MPC55XX_IRQ_CAN_BOFF_TWRN_RWRN(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 0U)
    223 #define MPC55XX_IRQ_CAN_ERR(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 1U)
    224 #define MPC55XX_IRQ_CAN_BUF_0(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 3U)
    225 #define MPC55XX_IRQ_CAN_BUF_1(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 4U)
    226 #define MPC55XX_IRQ_CAN_BUF_2(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 5U)
    227 #define MPC55XX_IRQ_CAN_BUF_3(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 6U)
    228 #define MPC55XX_IRQ_CAN_BUF_4(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 7U)
    229 #define MPC55XX_IRQ_CAN_BUF_5(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 8U)
    230 #define MPC55XX_IRQ_CAN_BUF_6(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 9U)
    231 #define MPC55XX_IRQ_CAN_BUF_7(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 10U)
    232 #define MPC55XX_IRQ_CAN_BUF_8(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 12U)
    233 #define MPC55XX_IRQ_CAN_BUF_9(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 12U)
    234 #define MPC55XX_IRQ_CAN_BUF_10(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 13U)
    235 #define MPC55XX_IRQ_CAN_BUF_11(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 14U)
    236 #define MPC55XX_IRQ_CAN_BUF_12(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 15U)
    237 #define MPC55XX_IRQ_CAN_BUF_13(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 16U)
    238 #define MPC55XX_IRQ_CAN_BUF_14(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 17U)
    239 #define MPC55XX_IRQ_CAN_BUF_15(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 18U)
    240 #define MPC55XX_IRQ_CAN_BUF_16_31(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 19U)
    241 #define MPC55XX_IRQ_CAN_BUF_32_63(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 20U)
     339#if MPC55XX_CHIP_TYPE / 10 == 564
     340  #define MPC55XX_IRQ_CAN_ERR(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 0U)
     341  #define MPC55XX_IRQ_CAN_BOFF_TWRN_RWRN(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 1U)
     342  #define MPC55XX_IRQ_CAN_BUF_0_3(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 3U)
     343  #define MPC55XX_IRQ_CAN_BUF_4_7(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 4U)
     344  #define MPC55XX_IRQ_CAN_BUF_8_11(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 5U)
     345  #define MPC55XX_IRQ_CAN_BUF_12_15(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 6U)
     346  #define MPC55XX_IRQ_CAN_BUF_16_31(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 7U)
     347#else
     348  #define MPC55XX_IRQ_CAN_BOFF_TWRN_RWRN(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 0U)
     349  #define MPC55XX_IRQ_CAN_ERR(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 1U)
     350  #define MPC55XX_IRQ_CAN_BUF_0(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 3U)
     351  #define MPC55XX_IRQ_CAN_BUF_1(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 4U)
     352  #define MPC55XX_IRQ_CAN_BUF_2(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 5U)
     353  #define MPC55XX_IRQ_CAN_BUF_3(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 6U)
     354  #define MPC55XX_IRQ_CAN_BUF_4(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 7U)
     355  #define MPC55XX_IRQ_CAN_BUF_5(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 8U)
     356  #define MPC55XX_IRQ_CAN_BUF_6(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 9U)
     357  #define MPC55XX_IRQ_CAN_BUF_7(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 10U)
     358  #define MPC55XX_IRQ_CAN_BUF_8(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 12U)
     359  #define MPC55XX_IRQ_CAN_BUF_9(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 12U)
     360  #define MPC55XX_IRQ_CAN_BUF_10(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 13U)
     361  #define MPC55XX_IRQ_CAN_BUF_11(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 14U)
     362  #define MPC55XX_IRQ_CAN_BUF_12(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 15U)
     363  #define MPC55XX_IRQ_CAN_BUF_13(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 16U)
     364  #define MPC55XX_IRQ_CAN_BUF_14(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 17U)
     365  #define MPC55XX_IRQ_CAN_BUF_15(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 18U)
     366  #define MPC55XX_IRQ_CAN_BUF_16_31(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 19U)
     367  #define MPC55XX_IRQ_CAN_BUF_32_63(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 20U)
     368#endif
     369
     370/* FlexPWM */
     371#define MPC55XX_IRQ_FLEXPWM_RF(mod, ch) (MPC55XX_IRQ_FLEXPWM_BASE(mod) + 3U * (ch) + 0U)
     372#define MPC55XX_IRQ_FLEXPWM_COF(mod, ch) (MPC55XX_IRQ_FLEXPWM_BASE(mod) + 3U * (ch) + 1U)
     373#define MPC55XX_IRQ_FLEXPWM_CAF(mod, ch) (MPC55XX_IRQ_FLEXPWM_BASE(mod) + 3U * (ch) + 2U)
     374#define MPC55XX_IRQ_FLEXPWM_FFLAG(mod) (MPC55XX_IRQ_FLEXPWM_BASE(mod) + 12U)
     375#define MPC55XX_IRQ_FLEXPWM_REF(mod) (MPC55XX_IRQ_FLEXPWM_BASE(mod) + 13U)
    242376
    243377/* FlexRay */
    244 #define MPC55XX_IRQ_FLEXRAY_MIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 0U)
    245 #define MPC55XX_IRQ_FLEXRAY_PRIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 1U)
    246 #define MPC55XX_IRQ_FLEXRAY_CHIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 2U)
    247 #define MPC55XX_IRQ_FLEXRAY_WUP_IF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 3U)
    248 #define MPC55XX_IRQ_FLEXRAY_FBNE_F(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 4U)
    249 #define MPC55XX_IRQ_FLEXRAY_FANE_F(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 5U)
    250 #define MPC55XX_IRQ_FLEXRAY_RBIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 6U)
    251 #define MPC55XX_IRQ_FLEXRAY_TBIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 7U)
     378#if MPC55XX_CHIP_TYPE / 10 == 564
     379  #define MPC55XX_IRQ_FLEXRAY_LRNEIF_DRNEIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 0U)
     380  #define MPC55XX_IRQ_FLEXRAY_LRCEIF_DRCEIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 1U)
     381  #define MPC55XX_IRQ_FLEXRAY_FAFAIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 2U)
     382  #define MPC55XX_IRQ_FLEXRAY_FAFVIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 3U)
     383  #define MPC55XX_IRQ_FLEXRAY_WUPIEF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 4U)
     384  #define MPC55XX_IRQ_FLEXRAY_PRIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 5U)
     385  #define MPC55XX_IRQ_FLEXRAY_CHIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 6U)
     386  #define MPC55XX_IRQ_FLEXRAY_TBIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 7U)
     387  #define MPC55XX_IRQ_FLEXRAY_RBIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 8U)
     388  #define MPC55XX_IRQ_FLEXRAY_MIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 9U)
     389#else
     390  #define MPC55XX_IRQ_FLEXRAY_MIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 0U)
     391  #define MPC55XX_IRQ_FLEXRAY_PRIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 1U)
     392  #define MPC55XX_IRQ_FLEXRAY_CHIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 2U)
     393  #define MPC55XX_IRQ_FLEXRAY_WUP_IF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 3U)
     394  #define MPC55XX_IRQ_FLEXRAY_FBNE_F(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 4U)
     395  #define MPC55XX_IRQ_FLEXRAY_FANE_F(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 5U)
     396  #define MPC55XX_IRQ_FLEXRAY_RBIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 6U)
     397  #define MPC55XX_IRQ_FLEXRAY_TBIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 7U)
     398#endif
     399
     400/* LINFlexD */
     401#define MPC55XX_IRQ_LINFLEX_RXI(mod) (MPC55XX_IRQ_LINFLEX_BASE(mod) + 0U)
     402#define MPC55XX_IRQ_LINFLEX_TXI(mod) (MPC55XX_IRQ_LINFLEX_BASE(mod) + 1U)
     403#define MPC55XX_IRQ_LINFLEX_ERR(mod) (MPC55XX_IRQ_LINFLEX_BASE(mod) + 2U)
    252404
    253405/* Checks */
  • c/src/lib/libcpu/powerpc/mpc55xx/include/mpc55xx.h

    r9bf3a868 ra762dc2  
    4747#include <stddef.h>
    4848#include <stdint.h>
    49 
    50 /* Defined in fmpll.S */
    51 int mpc55xx_get_system_clock(void);
    52 
    53 /* Defined in fmpll.S */
    54 void mpc55xx_system_reset(void);
    5549
    5650int mpc55xx_flash_copy(void *dest, const void *src, size_t nbytes);
  • c/src/lib/libcpu/powerpc/mpc55xx/include/reg-defs.h

    r9bf3a868 ra762dc2  
    2727
    2828#include <bspopts.h>
    29 /*
    30  * Register addresses
    31  */
    32 #if ((MPC55XX_CHIP_TYPE >= 5510) && (MPC55XX_CHIP_TYPE <= 5517))
    3329
    34 #define FMPLL_SYNSR   0xFFFF0004
    35 #define FMPLL_ESYNCR1 0xFFFF0008
    36 #define FMPLL_ESYNCR2 0xFFFF000C
    37 #define FLASH_BIUCR   0xFFFF801C
    38 #define SIU_ECCR      0xFFFE8984
    39 #define SIU_SYSCLK    0xFFFE89A0
    40 #define SIU_SRCR      0xFFFE8010
    41 
    42 /*
    43  * Definitions for SIU_SYSCLK
    44  */
    45 #define SIU_SYSCLK_SYSCLKSEL_MASK 0xC0000000
    46 #define SIU_SYSCLK_SYSCLKSEL_IRC  0x00000000
    47 #define SIU_SYSCLK_SYSCLKSEL_XOSC 0x40000000
    48 #define SIU_SYSCLK_SYSCLKSEL_PLL  0x80000000
    49 
    50 #else /* ((MPC55XX_CHIP_TYPE >= 5510) && (MPC55XX_CHIP_TYPE <= 5517))*/
    51 
    52 #define FMPLL_SYNCR 0xC3F80000
    53 #define FMPLL_SYNSR 0xC3F80004
    54 #define FMPLL_ESYNCR1 0XC3F80008
    55 #define FMPLL_ESYNCR2 0XC3F8000C
    56 #define FLASH_BIUCR 0xC3F8801C
    57 #define SIU_ECCR 0xC3F90984
    58 #define SIU_SRCR 0xC3F90010
    59 #define SIU_SYSDIV 0xC3F909A0
    60 
    61 #endif /*((MPC55XX_CHIP_TYPE >= 5510) && (MPC55XX_CHIP_TYPE <= 5517))*/
    62 /*
    63  * Special purpose registers
    64  */
    65 
    66 #define BUCSR 1013
    67 
    68 /*
    69  * Branch Unit Control and Status Register (BUCSR)
    70  */
    71 
    72 #define BUCSR_BBFI 0x00000200
    73 #define BUCSR_BPEN 0x00000001
    74 
    75 /*
    76  * Definitions for FMPLL_SYNCR (FMPLL Synthesizer Control Register)
    77  */
    78 
    79 /* Fields used for PREDIV (Pre-Divider bits [1:3]) */
    80 #define FMPLL_SYNCR_PREDIV_0 0x00000000
    81 
    82 /* Fields used for MFD (Muliplication Factor Divider bits [4:8]) */
    83 #define FMPLL_SYNCR_MFD_0 0x00000000
    84 #define FMPLL_SYNCR_MFD_2 0x01000000
    85 #define FMPLL_SYNCR_MFD_4 0x02000000
    86 #define FMPLL_SYNCR_MFD_6 0x03000000
    87 #define FMPLL_SYNCR_MFD_8 0x04000000
    88 #define FMPLL_SYNCR_MFD_10 0x05000000
    89 #define FMPLL_SYNCR_MFD_12 0x06000000
    90 
    91 /* Fields used for RFD (Reduced Frequency Divider bits [10:12]) */
    92 #define FMPLL_SYNCR_RFD_0 0x00000000
    93 #define FMPLL_SYNCR_RFD_1 0x00080000
    94 #define FMPLL_SYNCR_RFD_2 0x00100000
    95 #define FMPLL_SYNCR_RFD_3 0x00180000
    96 #define FMPLL_SYNCR_RFD_4 0x00200000
    97 #define FMPLL_SYNCR_RFD_5 0x00280000
    98 #define FMPLL_SYNCR_RFD_6 0x00300000
    99 #define FMPLL_SYNCR_RFD_7 0x00380000
    100 
    101 /* Fields for LOCEN (Loss-of-clock enable bit [13]) */
    102 #define FMPLL_SYNCR_LOCEN 0x00040000
    103 
    104 /* Fields for LOLRE (Loss-of-lock reset enable bit [14]) */
    105 #define FMPLL_SYNCR_LOLRE 0x00020000
    106 
    107 /* Fields for LOCRE (Loss-of-clock reset enable bit [15]) */
    108 #define FMPLL_SYNCR_LOCRE 0x00010000
    109 
    110 /* Fields for DISCLK (Disable CLKOUT bit [16]) */
    111 #define FMPLL_SYNCR_DISCLK 0x00008000
    112 
    113 /* Fields for LOLIRQ (Loss-of-lock interrupt request bit [17]) */
    114 #define FMPLL_SYNCR_LOLIRQ 0x00004000
    115 
    116 /* Fields for LOCIRQ (Loss-of-clock interrupt request bit [18]) */
    117 #define FMPLL_SYNCR_LOCIRQ 0x00002000
    118 
    119 /* Fields for RATE (Modulation rate bit [19]) */
    120 #define FMPLL_SYNCR_RATE_FREF 0x00001000
    121 
    122 /* Fields for DEPTH (Modulation depth percentage bits [20:21]) */
    123 #define FMPLL_SYNCR_DEPTH_0 0x00000000
    124 #define FMPLL_SYNCR_DEPTH_1 0x00000400
    125 #define FMPLL_SYNCR_DEPTH_2 0x00000800
    126 
    127 /* Fields for EXP (Expected difference bits [22:31]) */
    128 #define FMPLL_SYNCR_EXP_0 0x00000000
    129 
    130 /*
    131  * Definitions for the FMPLL_SYNSR (Synthesizer Status Register)
    132  */
    133 
    134 /* Fields for LOLF (Loss-of-lock flag bit [22]) */
    135 #define FMPLL_SYNSR_LOLF 0x00000200
    136 
    137 /* Fields for LOCK (Lock status bit [28]) */
    138 #define FMPLL_SYNSR_LOCK 0x00000008
    139 
    140 /* Fields for LOCF (Loss-of-clock flag bit [29]) */
    141 #define FMPLL_SYNSR_LOCF 0x00000004
    142 
    143 /*
    144  * Definitions for the SIU_SRCR (System Reset Control Register)
    145  */
    146 
    147 /* Fields for SSR (software system reset bit [0]) */
    148 #define SIU_SRCR_SSR 0x80000000
    149 
    150 /* Fields for SER (external system reset bit [1]) */
    151 #define SIU_SRCR_SER 0x40000000
    152 
    153 /* Fields for CRE (checkstop reset enable bit [16]) */
    154 #define SIU_SRCR_CRE 0x00008000
     30#if MPC55XX_CHIP_TYPE / 10 == 551
     31  #define FLASH_BIUCR   0xFFFF801C
     32#else
     33  #define FLASH_BIUCR 0xC3F8801C
     34#endif
    15535
    15636/*
  • c/src/lib/libcpu/powerpc/mpc55xx/include/regs-mmu.h

    r9bf3a868 ra762dc2  
    166166  }
    167167
     168#define MPC55XX_MMU_1K 0
     169#define MPC55XX_MMU_2K 1
     170#define MPC55XX_MMU_4K 2
     171#define MPC55XX_MMU_8K 3
     172#define MPC55XX_MMU_16K 4
     173#define MPC55XX_MMU_32K 5
     174#define MPC55XX_MMU_64K 6
     175#define MPC55XX_MMU_128K 7
     176#define MPC55XX_MMU_256K 8
     177#define MPC55XX_MMU_512K 9
     178#define MPC55XX_MMU_1M 10
     179#define MPC55XX_MMU_2M 11
     180#define MPC55XX_MMU_4M 12
     181#define MPC55XX_MMU_8M 13
     182#define MPC55XX_MMU_16M 14
     183#define MPC55XX_MMU_32M 15
     184#define MPC55XX_MMU_64M 16
     185#define MPC55XX_MMU_128M 17
     186#define MPC55XX_MMU_256M 18
     187#define MPC55XX_MMU_512M 19
     188#define MPC55XX_MMU_1G 20
     189#define MPC55XX_MMU_2G 21
     190#define MPC55XX_MMU_4G 22
     191
    168192#ifdef  __cplusplus
    169193}
  • c/src/lib/libcpu/powerpc/mpc55xx/include/regs.h

    r9bf3a868 ra762dc2  
    3131#if MPC55XX_CHIP_TYPE / 10 == 551
    3232  #include <mpc55xx/fsl-mpc551x.h>
     33  #define MPC55XX_HAS_EBI
     34  #define MPC55XX_HAS_ESCI
     35  #define MPC55XX_HAS_EMIOS
     36  #define MPC55XX_HAS_FMPLL_ENHANCED
    3337#elif MPC55XX_CHIP_TYPE / 10 == 555
    3438  #include <mpc55xx/fsl-mpc555x.h>
     39  #define MPC55XX_HAS_EBI
     40  #define MPC55XX_HAS_ESCI
     41  #define MPC55XX_HAS_EMIOS
     42  #define MPC55XX_HAS_FMPLL
     43  #define MPC55XX_HAS_UNIFIED_CACHE
    3544#elif MPC55XX_CHIP_TYPE / 10 == 556
    3645  #include <mpc55xx/fsl-mpc556x.h>
     46  #define MPC55XX_HAS_EBI
     47  #define MPC55XX_HAS_ESCI
     48  #define MPC55XX_HAS_EMIOS
     49  #define MPC55XX_HAS_FMPLL
     50  #define MPC55XX_HAS_UNIFIED_CACHE
     51#elif MPC55XX_CHIP_TYPE / 10 == 564
     52  #include <mpc55xx/fsl-mpc564xL.h>
     53  #define MPC55XX_HAS_STM
     54  #define MPC55XX_HAS_SWT
     55  #define MPC55XX_HAS_MODE_CONTROL
     56  #define MPC55XX_HAS_INSTRUCTION_CACHE
     57  #define MPC55XX_HAS_LINFLEX
     58  #define MPC55XX_HAS_SECOND_INTERNAL_RAM_AREA
    3759#elif MPC55XX_CHIP_TYPE / 10 == 567
    3860  #include <mpc55xx/fsl-mpc567x.h>
     61  #define MPC55XX_HAS_EBI
     62  #define MPC55XX_HAS_ESCI
     63  #define MPC55XX_HAS_EMIOS
     64  #define MPC55XX_HAS_FMPLL_ENHANCED
     65  #define MPC55XX_HAS_INSTRUCTION_CACHE
     66  #define MPC55XX_HAS_DATA_CACHE
    3967#else
    4068  #error "unsupported chip type"
  • c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_categories.c

    r9bf3a868 ra762dc2  
    275275    case PPC_e200z0:
    276276    case PPC_e200z1:
     277    case PPC_e200z4:
    277278    case PPC_e200z6:
    278279    case PPC_e200z7:
  • c/src/lib/libcpu/powerpc/preinstall.am

    r9bf3a868 ra762dc2  
    271271PREINSTALL_FILES += $(PROJECT_INCLUDE)/mpc55xx/mpc55xx.h
    272272
    273 $(PROJECT_INCLUDE)/mpc55xx/esci.h: mpc55xx/include/esci.h $(PROJECT_INCLUDE)/mpc55xx/$(dirstamp)
    274         $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/mpc55xx/esci.h
    275 PREINSTALL_FILES += $(PROJECT_INCLUDE)/mpc55xx/esci.h
    276 
    277273$(PROJECT_INCLUDE)/mpc55xx/siu.h: mpc55xx/include/siu.h $(PROJECT_INCLUDE)/mpc55xx/$(dirstamp)
    278274        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/mpc55xx/siu.h
     
    298294        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/mpc55xx/fsl-mpc556x.h
    299295PREINSTALL_FILES += $(PROJECT_INCLUDE)/mpc55xx/fsl-mpc556x.h
     296
     297$(PROJECT_INCLUDE)/mpc55xx/fsl-mpc564xL.h: mpc55xx/include/fsl-mpc564xL.h $(PROJECT_INCLUDE)/mpc55xx/$(dirstamp)
     298        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/mpc55xx/fsl-mpc564xL.h
     299PREINSTALL_FILES += $(PROJECT_INCLUDE)/mpc55xx/fsl-mpc564xL.h
    300300
    301301$(PROJECT_INCLUDE)/mpc55xx/fsl-mpc567x.h: mpc55xx/include/fsl-mpc567x.h $(PROJECT_INCLUDE)/mpc55xx/$(dirstamp)
  • c/src/lib/libcpu/powerpc/shared/include/cpuIdent.c

    r9bf3a868 ra762dc2  
    5454    case PPC_e200z0:            return "e200z0";
    5555    case PPC_e200z1:            return "e200z1";
     56    case PPC_e200z4:            return "e200z4";
    5657    case PPC_e200z6:            return "e200z6";
    5758    case PPC_e200z7:            return "e200z7";
     
    7374    PPC_e200z0,
    7475    PPC_e200z1,
     76    PPC_e200z4,
    7577    PPC_e200z6,
    7678    PPC_e200z7
     
    123125    case PPC_e200z0:
    124126    case PPC_e200z1:
     127    case PPC_e200z4:
    125128    case PPC_e200z6:
    126129    case PPC_e200z7:
     
    183186        case PPC_e200z0:
    184187        case PPC_e200z1:
     188        case PPC_e200z4:
    185189        case PPC_e200z6:
    186190        case PPC_e200z7:
  • c/src/lib/libcpu/powerpc/shared/include/cpuIdent.h

    r9bf3a868 ra762dc2  
    5959  PPC_e200z0  = 0x8170,
    6060  PPC_e200z1  = 0x8140,
     61  PPC_e200z4  = 0x8155,
    6162  PPC_e200z6  = 0x8110,
    6263  PPC_e200z7  = 0x8160,
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