Changeset a6c5a6d1 in rtems
- Timestamp:
- Nov 9, 2006, 11:10:50 AM (14 years ago)
- Branches:
- 4.10, 4.11, 4.8, 4.9, 5, master
- Children:
- 4df1b2e
- Parents:
- 1cb0a9b4
- Location:
- cpukit/score/cpu/bfin/rtems/bfin
- Files:
-
- 2 edited
Legend:
- Unmodified
- Added
- Removed
-
cpukit/score/cpu/bfin/rtems/bfin/bf533.h
r1cb0a9b4 ra6c5a6d1 52 52 53 53 /* SPORT0 Controller */ 54 #define SPORT0_TCR1 0xFFC00800 54 #define SPORT0_TCR1 0xFFC00800 55 55 #define SPORT0_TCR2 0xFFC00804 56 56 #define SPORT0_TCLKDIV 0xFFC00808 … … 360 360 #define EBIU_SDSTAT 0xFFC00A1C 361 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 362 #ifdef __cplusplus 381 363 } -
cpukit/score/cpu/bfin/rtems/bfin/bfin.h
r1cb0a9b4 ra6c5a6d1 3 3 * This file defines Macros for MMR register common to all Blackfin 4 4 * Processors. 5 * 5 * 6 6 * COPYRIGHT (c) 2006 by Atos Automacao Industrial Ltda. 7 7 * modified by Alain Schaefer <alain.schaefer@easc.ch> … … 24 24 25 25 /* Scratchpad SRAM */ 26 26 27 27 #define SCRATCH 0xFFB00000 28 28 #define SCRATCH_SIZE 0x1000 … … 41 41 /* Event Vector Table Chapter 4 */ 42 42 43 #define EVT0 0xFFE02000 44 #define EVT1 0xFFE02004 45 #define EVT2 0xFFE02008 46 #define EVT3 0xFFE0200C 47 #define EVT4 0xFFE02010 48 #define EVT5 0xFFE02014 49 #define EVT6 0xFFE02018 50 #define EVT7 0xFFE0201C 51 #define EVT8 0xFFE02020 52 #define EVT9 0xFFE02024 53 #define EVT10 0xFFE02028 54 #define EVT11 0xFFE0202C 55 #define EVT12 0xFFE02030 56 #define EVT13 0xFFE02034 57 #define EVT14 0xFFE02038 58 #define EVT15 0xFFE0203C 59 #define IMASK 0xFFE02104 60 #define IPEND 0xFFE02108 61 #define ILAT 0xFFE0210C 62 #define IPRIO 0xFFE02110 63 64 /* Core Timer Chapter 15 */ 43 #define EVT0 0xFFE02000 44 #define EVT1 0xFFE02004 45 #define EVT2 0xFFE02008 46 #define EVT3 0xFFE0200C 47 #define EVT4 0xFFE02010 48 #define EVT5 0xFFE02014 49 #define EVT6 0xFFE02018 50 #define EVT7 0xFFE0201C 51 #define EVT8 0xFFE02020 52 #define EVT9 0xFFE02024 53 #define EVT10 0xFFE02028 54 #define EVT11 0xFFE0202C 55 #define EVT12 0xFFE02030 56 #define EVT13 0xFFE02034 57 #define EVT14 0xFFE02038 58 #define EVT15 0xFFE0203C 59 #define IMASK 0xFFE02104 60 #define IPEND 0xFFE02108 61 #define ILAT 0xFFE0210C 62 #define IPRIO 0xFFE02110 63 64 65 65 #define TCNTL 0xFFE03000 66 66 #define TPERIOD 0xFFE03004 … … 69 69 70 70 /* Masks for Timer Control */ 71 #define TMPWR 0x00000001 72 #define TMREN 0x00000002 73 #define TAUTORLD 0x00000004 74 #define TINT 0x00000008 71 #define TMPWR 0x00000001 72 #define TMREN 0x00000002 73 #define TAUTORLD 0x00000004 74 #define TINT 0x00000008 75 75 76 76 /* Event Bit Positions */
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