Changeset a68347d in rtems


Ignore:
Timestamp:
May 13, 2010, 7:22:46 PM (9 years ago)
Author:
Joel Sherrill <joel.sherrill@…>
Branches:
4.10, 4.11, master
Children:
5813123a
Parents:
84208c67
Message:

2010-05-13 Joel Sherrill <joel.sherrill@…>

  • shared/irq/exception.S: rbtx4925, rbtx4938, and hurricane had very similar versions of exception. Now all use shared/irq/exception.S
Location:
c/src/lib/libbsp/mips
Files:
2 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/mips/ChangeLog

    r84208c67 ra68347d  
     12010-05-13      Joel Sherrill <joel.sherrill@oarcorp.com>
     2
     3        * shared/irq/exception.S: rbtx4925, rbtx4938, and hurricane had very
     4        similar versions of exception. Now all use shared/irq/exception.S
     5
    162010-05-13      Joel Sherrill <joel.sherrill@oarcorp.com>
    27
  • c/src/lib/libbsp/mips/shared/irq/exception.S

    r84208c67 ra68347d  
    2424 *  Derived from c/src/exec/score/cpu/no_cpu/cpu_asm.s:
    2525 *
    26  *  COPYRIGHT (c) 1989-1999.
     26 *  COPYRIGHT (c) 1989-2010.
    2727 *  On-Line Applications Research Corporation (OAR).
    2828 *
     
    3333 *  $Id$
    3434 */
    35 /* @(#)exception.S       7/27/04     1.00 */
    36 
     35
     36#include <bspopts.h>
     37#include <rtems/asm.h>
    3738#include <rtems/mips/iregdef.h>
    3839#include <rtems/mips/idtcpu.h>
    39 
    40 
    41 #define FRAME(name,frm_reg,offset,ret_reg)      \
    42         .globl  name;                           \
    43         .ent    name;                           \
    44 name:;                                          \
    45         .frame  frm_reg,offset,ret_reg
    46 #define ENDFRAME(name)                          \
    47         .end name
    48 
     40#if BSP_HAS_USC320
     41  #include <usc.h>
     42#endif
    4943
    5044#if __mips == 3
     
    149143        sw      k1,(k0)
    150144#endif
    151 
    152145        mfc0 k0,C0_CAUSE        /* Determine if an interrupt generated this exception */
    153146        nop
     
    164157        nop
    165158        and k0,k1
     159#if HAS_RM52xx
     160        and k0,CAUSE_IPMASK
     161#elif HAS_TX49xx
    166162        and k0,(SR_IBIT1 | SR_IBIT2 | SR_IBIT3)
    167         beq k0,zero,_ISR_Handler_quick_exit /* external interrupt not enabled, ignore */
     163#endif
     164        /* external interrupt not enabled, ignore */
     165        beq k0,zero,_ISR_Handler_quick_exit
    168166        nop
    169167
     
    251249        sw      t1,_Thread_Dispatch_disable_level
    252250
    253 
    254         /* DEBUG - Add the following code to disable interrupts and clear EXL in status register, this will
    255                 allow memory exceptions to occur while servicing the current interrupt */
     251        /* DEBUG - Add the following code to disable interrupts and clear
     252         *         EXL in status register, this will allow memory
     253         *         exceptions to occur while servicing the current interrupt
     254         */
    256255#if 0
    257         li t0,~CAUSE_IP2_MASK   /* Disable interrupts from internal interrupt controller */
     256        /* Disable interrupts from internal interrupt controller */
     257        li t0,~CAUSE_IP2_MASK
    258258        mfc0 t1,C0_SR
    259259        nop
     
    261261        mtc0 t1,C0_SR
    262262        nop
    263         li t0,~SR_EXL           /* Clear EXL in status register to allow memory exceptions to occur */
     263        /* Clear EXL in status register to allow memory exceptions to occur */
     264        li t0,~SR_EXL
    264265        mfc0 t1,C0_SR
    265266        nop
     
    285286        mtc0 t1,C0_SR
    286287        nop
    287         li t0,CAUSE_IP2_MASK    /* Enable interrupts from internal interrupt controller */
     288        /* Enable interrupts from internal interrupt controller */
     289        li t0,CAUSE_IP2_MASK
    288290        mfc0 t1,C0_SR
    289291        nop
     
    386388        mtc0    t0, C0_SR
    387389        NOP
    388 
    389390
    390391  /*
     
    438439
    439440
     441#if BSP_HAS_USC320
     442        /* Interrupts from USC320 are serviced here */
     443        .global USC_isr
     444        .extern Clock_isr
     445USC_isr:
     446        /* check if it's a USC320 heartbeat interrupt */
     447        la      k0,INT_STAT     /* read INT_STAT register */
     448        lw      k0,(k0)
     449        nop                     /* reading from external device */
     450        sll     k0,(31-21)      /* test bit 21 (HBI) */
     451
     452        bgez    k0,USC_isr2     /* branch if not a heartbeat interrupt */
     453        NOP
     454
     455        /* clear the heartbeat interrupt */
     456        la      k0,INT_STAT
     457        li      t0,HBI_MASK
     458        sw      t0,(k0)
     459        /* wait for interrupt to clear */
     460USC_isr1:
     461        la      k0,INT_STAT     /* read INT_STAT register */
     462        lw      k0,(k0)
     463        nop                     /* reading from external device */
     464        sll     k0,(31-21)      /* test bit 21 (HBI) */
     465        bltz    k0,USC_isr1     /* branch if bit set */
     466        nop
     467        j       Clock_isr       /* Jump to clock isr */
     468        nop
     469USC_isr2:
     470        j       ra              /* no serviceable interrupt, return without doing anything */
     471        nop
     472#endif
     473
    440474#if 0
    441475        .global int7_isr
     
    468502        .set noreorder
    469503
    470 #ifdef USC
     504#if BSP_HAS_USC320
    471505        la      k0,INT_CFG3     /* Disable heartbeat interrupt in USC320, it interferes with PMON exception handler */
    472506        lw      k1,(k0)
Note: See TracChangeset for help on using the changeset viewer.