Changeset a48c052 in rtems


Ignore:
Timestamp:
Jul 15, 2016, 2:21:12 PM (4 years ago)
Author:
Pavel Pisa <pisa@…>
Branches:
5, master
Children:
33381218
Parents:
c2a4b8bf
git-author:
Pavel Pisa <pisa@…> (07/15/16 14:21:12)
git-committer:
Pavel Pisa <pisa@…> (07/20/16 14:46:04)
Message:

arm/raspberrypi: cache manager can be used for mailbox synchronization now. Remove workarounds.

Signed-off-by: Pavel Pisa <pisa@…>

File:
1 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/arm/raspberrypi/misc/vc.c

    rc2a4b8bf ra48c052  
    5757)
    5858{
    59   uint32_t sctlr_val;
    60 
    61   sctlr_val = arm_cp15_get_control();
    62 
    63   RTEMS_COMPILER_MEMORY_BARRIER();
    64   arm_cp15_drain_write_buffer();
    65 
    66   if ( sctlr_val & ( ARM_CP15_CTRL_C | ARM_CP15_CTRL_M ) ) {
    67 #if 0
    68     /*
    69        These architecture independent RTEMS API functions should be
    70        used there but CPU_DATA_CACHE_ALIGNMENT is not defined
    71        for ARM architecture version used on RPi and functions
    72        are dummy for now and do not provide required synchronization
    73      */
    74     rtems_cache_flush_multiple_data_lines( buf, size );
    75     rtems_cache_invalidate_multiple_data_lines( buf, size );
    76 #elif 0
    77     /* Flush complete data cache, does not work on RPi2 for some reason */
    78     arm_cp15_data_cache_clean_and_invalidate();
    79 #else
    80     /*
    81      * This is temporal workaround for missing cache meanager
    82      * which works on RPi2
    83      */
    84     size += (uintptr_t)buf & ~63;
    85     size = (size + 63) & ~63;
    86     while ( size ) {
    87       size -= 32;
    88       arm_cp15_data_cache_clean_and_invalidate_line(buf);
    89     }
    90 #endif
    91   }
     59  rtems_cache_flush_multiple_data_lines( buf, size );
     60  rtems_cache_invalidate_multiple_data_lines( buf, size );
    9261}
    9362
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