- Timestamp:
- 06/07/11 09:14:06 (13 years ago)
- Branches:
- 4.11, 5, master
- Children:
- 95fe2fd
- Parents:
- 1343dfa3
- Location:
- c/src/lib/libbsp/powerpc/mpc55xxevb
- Files:
-
- 6 edited
Legend:
- Unmodified
- Added
- Removed
-
c/src/lib/libbsp/powerpc/mpc55xxevb/ChangeLog
r1343dfa3 ra4475277 1 2011-06-07 Sebastian Huber <sebastian.huber@embedded-brains.de> 2 3 * clock/clock-config.c: Fixes to pass psnsext01. 4 * startup/bspstart.c: Workaround for GCC 4.6 bug. 5 * include/smsc9218i.h, network/smsc9218i.c, Makefile.am: Changes 6 throughout. 7 1 8 2011-02-11 Ralf Corsépius <ralf.corsepius@rtems.org> 2 9 -
c/src/lib/libbsp/powerpc/mpc55xxevb/Makefile.am
r1343dfa3 ra4475277 71 71 # Network 72 72 if HAS_NETWORKING 73 noinst_PROGRAMS += network.rel 74 network_rel_SOURCES = network/smsc9218i.c 75 network_rel_CPPFLAGS = $(AM_CPPFLAGS) -D__INSIDE_RTEMS_BSD_TCPIP_STACK__ -D__BSD_VISIBLE 76 network_rel_LDFLAGS = $(RTEMS_RELLDFLAGS) 73 libbsp_a_SOURCES += network/smsc9218i.c 77 74 endif 78 75 … … 92 89 ../../../libcpu/@RTEMS_CPU@/@exceptions@/exc_bspsupport.rel \ 93 90 ../../../libcpu/@RTEMS_CPU@/@RTEMS_CPU_MODEL@/timer.rel 94 if HAS_NETWORKING95 libbsp_a_LIBADD += network.rel96 endif97 91 98 92 include $(srcdir)/preinstall.am -
c/src/lib/libbsp/powerpc/mpc55xxevb/clock/clock-config.c
r1343dfa3 ra4475277 44 44 } while (0) 45 45 46 static void mpc55xx_clock_handler_install( rtems_isr_entry isr, 46 static uint64_t mpc55xx_clock_factor; 47 48 static void mpc55xx_clock_handler_install( rtems_isr_entry isr, 47 49 rtems_isr_entry *old_isr) 48 50 { … … 69 71 uint64_t interval = ((uint64_t) bsp_clock_speed 70 72 * (uint64_t) rtems_configuration_get_microseconds_per_tick()) / 1000000; 73 74 mpc55xx_clock_factor = (1000000000ULL << 32) / bsp_clock_speed; 71 75 72 76 /* Apply prescaler */ … … 132 136 static uint32_t mpc55xx_clock_nanoseconds_since_last_tick( void) 133 137 { 134 uint64_t clicks = EMIOS.CH [MPC55XX_CLOCK_EMIOS_CHANNEL].CCNTR.R; 135 uint64_t clock = bsp_clock_speed; 136 uint64_t ns = (clicks * 1000000000) / clock; 138 volatile struct EMIOS_CH_tag *regs = &EMIOS.CH [MPC55XX_CLOCK_EMIOS_CHANNEL]; 139 uint64_t c = regs->CCNTR.R; 140 union EMIOS_CSR_tag csr = { .R = regs->CSR.R }; 141 uint64_t k = mpc55xx_clock_factor; 137 142 138 return (uint32_t) ns; 143 if (csr.B.FLAG != 0) { 144 c = regs->CCNTR.R + regs->CADR.R + 1; 145 } 146 147 return (uint32_t) ((c * k) >> 32); 139 148 } 140 149 -
c/src/lib/libbsp/powerpc/mpc55xxevb/include/smsc9218i.h
r1343dfa3 ra4475277 190 190 191 191 /** 192 * @name Interrupt Status 193 * @{ 194 */ 195 196 #define SMSC9218I_INT_STS_SW SMSC9218I_FLAG(31) 197 #define SMSC9218I_INT_STS_TXSTOP SMSC9218I_FLAG(25) 198 #define SMSC9218I_INT_STS_RXSTOP SMSC9218I_FLAG(24) 199 #define SMSC9218I_INT_STS_RXDFH SMSC9218I_FLAG(23) 200 #define SMSC9218I_INT_STS_TIOC SMSC9218I_FLAG(21) 201 #define SMSC9218I_INT_STS_RXD SMSC9218I_FLAG(20) 202 #define SMSC9218I_INT_STS_GPT SMSC9218I_FLAG(19) 203 #define SMSC9218I_INT_STS_PHY SMSC9218I_FLAG(18) 204 #define SMSC9218I_INT_STS_PME SMSC9218I_FLAG(17) 205 #define SMSC9218I_INT_STS_TXSO SMSC9218I_FLAG(16) 206 #define SMSC9218I_INT_STS_RWT SMSC9218I_FLAG(15) 207 #define SMSC9218I_INT_STS_RXE SMSC9218I_FLAG(14) 208 #define SMSC9218I_INT_STS_TXE SMSC9218I_FLAG(13) 209 #define SMSC9218I_INT_STS_TDFO SMSC9218I_FLAG(10) 210 #define SMSC9218I_INT_STS_TDFA SMSC9218I_FLAG(9) 211 #define SMSC9218I_INT_STS_TSFF SMSC9218I_FLAG(8) 212 #define SMSC9218I_INT_STS_TSFL SMSC9218I_FLAG(7) 213 #define SMSC9218I_INT_STS_RSFF SMSC9218I_FLAG(4) 214 #define SMSC9218I_INT_STS_RSFL SMSC9218I_FLAG(3) 215 #define SMSC9218I_INT_STS_GPIO2 SMSC9218I_FLAG(2) 216 #define SMSC9218I_INT_STS_GPIO1 SMSC9218I_FLAG(1) 217 #define SMSC9218I_INT_STS_GPIO0 SMSC9218I_FLAG(0) 218 219 /** @} */ 220 221 /** 222 * @name Interrupt Enable 223 * @{ 224 */ 225 226 #define SMSC9218I_INT_EN_SW SMSC9218I_FLAG(31) 227 #define SMSC9218I_INT_EN_TXSTOP SMSC9218I_FLAG(25) 228 #define SMSC9218I_INT_EN_RXSTOP SMSC9218I_FLAG(24) 229 #define SMSC9218I_INT_EN_RXDFH SMSC9218I_FLAG(23) 230 #define SMSC9218I_INT_EN_TIOC SMSC9218I_FLAG(21) 231 #define SMSC9218I_INT_EN_RXD SMSC9218I_FLAG(20) 232 #define SMSC9218I_INT_EN_GPT SMSC9218I_FLAG(19) 233 #define SMSC9218I_INT_EN_PHY SMSC9218I_FLAG(18) 234 #define SMSC9218I_INT_EN_PME SMSC9218I_FLAG(17) 235 #define SMSC9218I_INT_EN_TXSO SMSC9218I_FLAG(16) 236 #define SMSC9218I_INT_EN_RWT SMSC9218I_FLAG(15) 237 #define SMSC9218I_INT_EN_RXE SMSC9218I_FLAG(14) 238 #define SMSC9218I_INT_EN_TXE SMSC9218I_FLAG(13) 239 #define SMSC9218I_INT_EN_TDFO SMSC9218I_FLAG(10) 240 #define SMSC9218I_INT_EN_TDFA SMSC9218I_FLAG(9) 241 #define SMSC9218I_INT_EN_TSFF SMSC9218I_FLAG(8) 242 #define SMSC9218I_INT_EN_TSFL SMSC9218I_FLAG(7) 243 #define SMSC9218I_INT_EN_RSFF SMSC9218I_FLAG(4) 244 #define SMSC9218I_INT_EN_RSFL SMSC9218I_FLAG(3) 245 #define SMSC9218I_INT_EN_GPIO2 SMSC9218I_FLAG(2) 246 #define SMSC9218I_INT_EN_GPIO1 SMSC9218I_FLAG(1) 247 #define SMSC9218I_INT_EN_GPIO0 SMSC9218I_FLAG(0) 192 * @name Interrupt Enable and Status 193 * @{ 194 */ 195 196 #define SMSC9218I_INT_SW SMSC9218I_FLAG(31) 197 #define SMSC9218I_INT_TXSTOP SMSC9218I_FLAG(25) 198 #define SMSC9218I_INT_RXSTOP SMSC9218I_FLAG(24) 199 #define SMSC9218I_INT_RXDFH SMSC9218I_FLAG(23) 200 #define SMSC9218I_INT_TIOC SMSC9218I_FLAG(21) 201 #define SMSC9218I_INT_RXD SMSC9218I_FLAG(20) 202 #define SMSC9218I_INT_GPT SMSC9218I_FLAG(19) 203 #define SMSC9218I_INT_PHY SMSC9218I_FLAG(18) 204 #define SMSC9218I_INT_PME SMSC9218I_FLAG(17) 205 #define SMSC9218I_INT_TXSO SMSC9218I_FLAG(16) 206 #define SMSC9218I_INT_RWT SMSC9218I_FLAG(15) 207 #define SMSC9218I_INT_RXE SMSC9218I_FLAG(14) 208 #define SMSC9218I_INT_TXE SMSC9218I_FLAG(13) 209 #define SMSC9218I_INT_TDFO SMSC9218I_FLAG(10) 210 #define SMSC9218I_INT_TDFA SMSC9218I_FLAG(9) 211 #define SMSC9218I_INT_TSFF SMSC9218I_FLAG(8) 212 #define SMSC9218I_INT_TSFL SMSC9218I_FLAG(7) 213 #define SMSC9218I_INT_RSFF SMSC9218I_FLAG(4) 214 #define SMSC9218I_INT_RSFL SMSC9218I_FLAG(3) 215 #define SMSC9218I_INT_GPIO2 SMSC9218I_FLAG(2) 216 #define SMSC9218I_INT_GPIO1 SMSC9218I_FLAG(1) 217 #define SMSC9218I_INT_GPIO0 SMSC9218I_FLAG(0) 248 218 249 219 /** @} */ … … 436 406 437 407 #define SMSC9218I_RX_DROP_GET(reg) SMSC9218I_SWAP(reg) 408 409 /** @} */ 410 411 /** 412 * @name EEPROM Command Register 413 * @{ 414 */ 415 416 #define SMSC9218I_E2P_CMD_EPC_BUSY SMSC9218I_FLAG(31) 438 417 439 418 /** @} */ … … 600 579 601 580 /** 602 * @name Basic Control603 * @{604 */605 606 #define SMSC9218I_PHY_BCR 0x00000000U607 #define SMSC9218I_PHY_BCR_RST 0x00008000U608 #define SMSC9218I_PHY_BCR_LOOPBK 0x00004000U609 #define SMSC9218I_PHY_BCR_SS 0x00002000U610 #define SMSC9218I_PHY_BCR_ANE 0x00001000U611 #define SMSC9218I_PHY_BCR_PWRDN 0x00000800U612 #define SMSC9218I_PHY_BCR_RSTAN 0x00000200U613 #define SMSC9218I_PHY_BCR_FDPLX 0x00000100U614 #define SMSC9218I_PHY_BCR_COLLTST 0x00000080U615 616 /** @} */617 618 /**619 * @name Basic Status620 * @{621 */622 623 #define SMSC9218I_PHY_BSR 0x00000001U624 #define SMSC9218I_PHY_BSR_100_T4_ABLE 0x00008000U625 #define SMSC9218I_PHY_BSR_100_TX_FDPLX 0x00004000U626 #define SMSC9218I_PHY_BSR_100_TX_HDPLX 0x00002000U627 #define SMSC9218I_PHY_BSR_10_FDPLX 0x00001000U628 #define SMSC9218I_PHY_BSR_10_HDPLX 0x00000800U629 #define SMSC9218I_PHY_BSR_ANC 0x00000020U630 #define SMSC9218I_PHY_BSR_REM_FAULT 0x00000010U631 #define SMSC9218I_PHY_BSR_AN_ABLE 0x00000008U632 #define SMSC9218I_PHY_BSR_LINK_STATUS 0x00000004U633 #define SMSC9218I_PHY_BSR_JAB_DET 0x00000002U634 #define SMSC9218I_PHY_BSR_EXT_CAP 0x00000001U635 636 /** @} */637 638 /**639 581 * @name PHY Identifier 1 640 582 * @{ 641 583 */ 642 584 643 #define SMSC9218I_PHY_ID1 0x00000002U 644 #define SMSC9218I_PHY_ID1_MASK 0x0000ffffU 645 #define SMSC9218I_PHY_ID1_LAN9118 0x00000007U 646 #define SMSC9218I_PHY_ID1_LAN9218 (PHY_ID1_LAN9118) 585 #define SMSC9218I_PHY_ID1_LAN9118 0x7 647 586 648 587 /** @} */ … … 653 592 */ 654 593 655 #define SMSC9218I_PHY_ID2 0x00000003U 656 #define SMSC9218I_PHY_ID2_MASK 0x0000ffffU 657 #define SMSC9218I_PHY_ID2_MODEL_MASK 0x000003f0U 658 #define SMSC9218I_PHY_ID2_REV_MASK 0x0000000fU 659 #define SMSC9218I_PHY_ID2_LAN9118 0x0000c0d1U 660 #define SMSC9218I_PHY_ID2_LAN9218 0x0000c0c3U 661 662 /** @} */ 663 664 /** 665 * @name Auto-negotiation Advertisment 666 * @{ 667 */ 668 669 #define SMSC9218I_PHY_ANAR 0x00000004U 670 #define SMSC9218I_PHY_ANAR_NXTPG_CAP 0x00008000U 671 #define SMSC9218I_PHY_ANAR_REM_FAULT 0x00002000U 672 #define SMSC9218I_PHY_ANAR_PAUSE_OP_MASK 0x00000c00U 673 #define SMSC9218I_PHY_ANAR_PAUSE_OP_NONE 0x00000000U 674 #define SMSC9218I_PHY_ANAR_PAUSE_OP_ASLP 0x00000400U 675 #define SMSC9218I_PHY_ANAR_PAUSE_OP_SLP 0x00000800U 676 #define SMSC9218I_PHY_ANAR_PAUSE_OP_BOTH 0x00000c00U 677 #define SMSC9218I_PHY_ANAR_100_T4_ABLE 0x00000200U 678 #define SMSC9218I_PHY_ANAR_100_TX_FDPLX 0x00000100U 679 #define SMSC9218I_PHY_ANAR_100_TX_ABLE 0x00000080U 680 #define SMSC9218I_PHY_ANAR_10_FDPLX 0x00000040U 681 #define SMSC9218I_PHY_ANAR_10_ABLE 0x00000020U 682 683 /** @} */ 684 685 /** 686 * @name Auto-negotiation Link Partner Ability 687 * @{ 688 */ 689 690 #define SMSC9218I_PHY_ANLPAR 0x00000005U 691 #define SMSC9218I_PHY_ANLPAR_NXTPG_CAP 0x00008000U 692 #define SMSC9218I_PHY_ANLPAR_ACK 0x00004000U 693 #define SMSC9218I_PHY_ANLPAR_REM_FAULT 0x00002000U 694 #define SMSC9218I_PHY_ANLPAR_PAUSE_CAP 0x00000400U 695 #define SMSC9218I_PHY_ANLPAR_100_T4_ABLE 0x00000200U 696 #define SMSC9218I_PHY_ANLPAR_100_TX_FDPLX 0x00000100U 697 #define SMSC9218I_PHY_ANLPAR_100_TX_ABLE 0x00000080U 698 #define SMSC9218I_PHY_ANLPAR_10_FDPLX 0x00000040U 699 #define SMSC9218I_PHY_ANLPAR_10_ABLE 0x00000020U 700 701 /** @} */ 702 703 /** 704 * @name Auto-negotiation Expansion 705 * @{ 706 */ 707 708 #define SMSC9218I_PHY_ANEXPR 0x00000006U 709 #define SMSC9218I_PHY_ANEXPR_PARDET_FAULT 0x00000010U 710 #define SMSC9218I_PHY_ANEXPR_LP_NXTPG_CAP 0x00000008U 711 #define SMSC9218I_PHY_ANEXPR_NXTPG_CAP 0x00000004U 712 #define SMSC9218I_PHY_ANEXPR_NEWPG_REC 0x00000002U 713 #define SMSC9218I_PHY_ANEXPR_LP_AN_ABLE 0x00000001U 594 #define SMSC9218I_PHY_ID2_LAN9218 0xc0c3 714 595 715 596 /** @} */ -
c/src/lib/libbsp/powerpc/mpc55xxevb/network/smsc9218i.c
r1343dfa3 ra4475277 8 8 9 9 /* 10 * Copyright (c) 2009 11 * embedded brains GmbH 12 * Obere Lagerstr. 30 13 * D-82178 Puchheim 14 * Germany 15 * rtems@embedded-brains.de 10 * Copyright (c) 2009-2011 embedded brains GmbH. All rights reserved. 11 * 12 * embedded brains GmbH 13 * Obere Lagerstr. 30 14 * 82178 Puchheim 15 * Germany 16 * <rtems@embedded-brains.de> 16 17 * 17 18 * The license and distribution terms for this file may be 18 19 * found in the file LICENSE in this distribution or at 19 20 * http://www.rtems.com/license/LICENSE. 21 * 22 * $Id$ 20 23 */ 24 25 #define __INSIDE_RTEMS_BSD_TCPIP_STACK__ 1 26 #define __BSD_VISIBLE 1 21 27 22 28 #include <mpc55xx/regs.h> … … 77 83 #define SMSC9218I_RX_DATA_OFFSET 2 78 84 79 #define SMSC9218I_TX_JOBS 1 6U85 #define SMSC9218I_TX_JOBS 128U 80 86 81 87 #define SMSC9218I_TX_JOBS_MAX (SMSC9218I_TX_JOBS - 1U) … … 89 95 #define SMSC9218I_IRQ_CFG_GLOBAL_DISABLE SMSC9218I_IRQ_CFG_IRQ_TYPE 90 96 91 #define SMSC9218I_EDMA_RX_CHANNEL 4 897 #define SMSC9218I_EDMA_RX_CHANNEL 49 92 98 93 99 #define SMSC9218I_EDMA_RX_TCD_CDF 0x10004 … … 95 101 #define SMSC9218I_EDMA_RX_TCD_BMF 0x10003 96 102 97 #define SMSC9218I_EDMA_TX_CHANNEL 4 9103 #define SMSC9218I_EDMA_TX_CHANNEL 48 98 104 99 105 #define SMSC9218I_EDMA_TX_TCD_BMF_LINK 0x10011 … … 102 108 103 109 #define SMSC9218I_EDMA_TX_TCD_BMF_CLEAR 0x10000 110 111 #define SMSC9218I_ERROR_INTERRUPTS \ 112 (SMSC9218I_INT_TXSO \ 113 | SMSC9218I_INT_RWT \ 114 | SMSC9218I_INT_RXE \ 115 | SMSC9218I_INT_TXE) 104 116 105 117 #ifdef DEBUG … … 120 132 typedef struct { 121 133 struct arpcom arpcom; 122 struct rtems_mdio_info mdio _info;134 struct rtems_mdio_info mdio; 123 135 smsc9218i_state state; 124 136 rtems_id receive_task; … … 130 142 unsigned transmitted_frames; 131 143 unsigned transmit_interrupts; 144 unsigned receiver_errors; 132 145 unsigned receive_too_long_errors; 133 146 unsigned receive_collision_errors; 134 147 unsigned receive_crc_errors; 135 148 unsigned receive_edma_errors; 136 unsigned transmit_errors; 149 unsigned receive_drop; 150 unsigned receive_watchdog_timeouts; 151 unsigned transmitter_errors; 152 unsigned transmit_status_overflows; 153 unsigned transmit_frame_errors; 137 154 unsigned transmit_edma_errors; 138 155 } smsc9218i_driver_entry; … … 161 178 uint16_t tag; 162 179 bool done; 180 unsigned fixme_tiny_fragments; 181 unsigned fixme_too_many; 163 182 } smsc9218i_transmit_job_control; 164 183 … … 391 410 printf("mac: wucsr: 0x%08" PRIx32 "\n", smsc9218i_mac_read(regs, SMSC9218I_MAC_WUCSR)); 392 411 393 printf("phy: bcr: 0x%08" PRIx32 "\n", smsc9218i_phy_read(regs, SMSC9218I_PHY_BCR));394 printf("phy: bsr: 0x%08" PRIx32 "\n", smsc9218i_phy_read(regs, SMSC9218I_PHY_BSR));395 printf("phy: id1: 0x%08" PRIx32 "\n", smsc9218i_phy_read(regs, SMSC9218I_PHY_ID1));396 printf("phy: id2: 0x%08" PRIx32 "\n", smsc9218i_phy_read(regs, SMSC9218I_PHY_ID2));397 printf("phy: anar: 0x%08" PRIx32 "\n", smsc9218i_phy_read(regs, SMSC9218I_PHY_ANAR));398 printf("phy: anlpar: 0x%08" PRIx32 "\n", smsc9218i_phy_read(regs, SMSC9218I_PHY_ANLPAR));399 printf("phy: anexpr: 0x%08" PRIx32 "\n", smsc9218i_phy_read(regs, SMSC9218I_PHY_ANEXPR));412 printf("phy: bcr: 0x%08" PRIx32 "\n", smsc9218i_phy_read(regs, MII_BMCR)); 413 printf("phy: bsr: 0x%08" PRIx32 "\n", smsc9218i_phy_read(regs, MII_BMSR)); 414 printf("phy: id1: 0x%08" PRIx32 "\n", smsc9218i_phy_read(regs, MII_PHYIDR1)); 415 printf("phy: id2: 0x%08" PRIx32 "\n", smsc9218i_phy_read(regs, MII_PHYIDR2)); 416 printf("phy: anar: 0x%08" PRIx32 "\n", smsc9218i_phy_read(regs, MII_ANAR)); 417 printf("phy: anlpar: 0x%08" PRIx32 "\n", smsc9218i_phy_read(regs, MII_ANLPAR)); 418 printf("phy: anexpr: 0x%08" PRIx32 "\n", smsc9218i_phy_read(regs, MII_ANER)); 400 419 printf("phy: mcsr: 0x%08" PRIx32 "\n", smsc9218i_phy_read(regs, SMSC9218I_PHY_MCSR)); 401 420 printf("phy: spmodes: 0x%08" PRIx32 "\n", smsc9218i_phy_read(regs, SMSC9218I_PHY_SPMODES)); … … 436 455 regs->int_sts = int_sts; 437 456 457 /* Error interrupts */ 458 if ((int_sts & SMSC9218I_ERROR_INTERRUPTS) != 0) { 459 if ((int_sts & SMSC9218I_INT_TXSO) != 0) { 460 ++e->transmit_status_overflows; 461 } 462 if ((int_sts & SMSC9218I_INT_RWT) != 0) { 463 ++e->receive_watchdog_timeouts; 464 } 465 if ((int_sts & SMSC9218I_INT_RXE) != 0) { 466 ++e->receiver_errors; 467 } 468 if ((int_sts & SMSC9218I_INT_TXE) != 0) { 469 ++e->transmitter_errors; 470 } 471 } 472 438 473 /* Check receive interrupts */ 439 if ((int_sts & SMSC9218I_INT_ STS_RSFL) != 0) {440 int_en &= ~SMSC9218I_INT_ EN_RSFL;474 if ((int_sts & SMSC9218I_INT_RSFL) != 0) { 475 int_en &= ~SMSC9218I_INT_RSFL; 441 476 re = SMSC9218I_EVENT_RX; 442 477 } 443 478 444 479 /* Check PHY interrupts */ 445 if ((int_sts & SMSC9218I_INT_ STS_PHY) != 0) {446 int_en &= ~SMSC9218I_INT_ EN_PHY;480 if ((int_sts & SMSC9218I_INT_PHY) != 0) { 481 int_en &= ~SMSC9218I_INT_PHY; 447 482 re |= SMSC9218I_EVENT_PHY; 448 483 } … … 456 491 457 492 /* Check transmit interrupts */ 458 if ((int_sts & SMSC9218I_INT_ STS_TDFA) != 0) {459 int_en &= ~SMSC9218I_INT_ EN_TDFA;493 if ((int_sts & SMSC9218I_INT_TDFA) != 0) { 494 int_en &= ~SMSC9218I_INT_TDFA; 460 495 te = SMSC9218I_EVENT_TX; 461 496 } … … 482 517 483 518 rtems_interrupt_disable(level); 484 regs->int_en |= SMSC9218I_INT_ EN_RSFL;519 regs->int_en |= SMSC9218I_INT_RSFL; 485 520 rtems_interrupt_enable(level); 486 521 } … … 493 528 494 529 rtems_interrupt_disable(level); 495 regs->int_en |= SMSC9218I_INT_ EN_TDFA;530 regs->int_en |= SMSC9218I_INT_TDFA; 496 531 rtems_interrupt_enable(level); 497 532 } … … 504 539 505 540 rtems_interrupt_disable(level); 506 regs->int_en |= SMSC9218I_INT_ EN_PHY;541 regs->int_en |= SMSC9218I_INT_PHY; 507 542 rtems_interrupt_enable(level); 508 543 } 509 544 510 static struct mbuf *smsc9218i_new_mbuf(struct ifnet *ifp, bool wait) 511 { 512 struct mbuf *m = NULL; 513 int mw = wait ? M_WAIT : M_DONTWAIT; 514 515 MGETHDR(m, mw, MT_DATA); 516 if (m != NULL) { 517 MCLGET(m, mw); 518 if ((m->m_flags & M_EXT) != 0) { 519 /* Set receive interface */ 520 m->m_pkthdr.rcvif = ifp; 521 522 return m; 523 } else { 524 m_freem(m); 525 } 526 } 527 528 return NULL; 545 static void smsc9218i_phy_clear_interrupts( 546 volatile smsc9218i_registers *regs 547 ) 548 { 549 smsc9218i_phy_read(regs, SMSC9218I_PHY_ISR); 550 } 551 552 static bool smsc9218i_media_status(smsc9218i_driver_entry *e, int *media) 553 { 554 struct ifnet *ifp = &e->arpcom.ac_if; 555 556 *media = IFM_MAKEWORD(0, 0, 0, SMSC9218I_MAC_MII_ACC_PHY_DEFAULT); 557 558 return (*ifp->if_ioctl)(ifp, SIOCGIFMEDIA, (caddr_t) media) == 0; 559 } 560 561 static void smsc9218i_media_status_change( 562 smsc9218i_driver_entry *e, 563 volatile smsc9218i_registers *regs 564 ) 565 { 566 int media = 0; 567 bool media_ok = false; 568 uint32_t mac_cr = 0; 569 570 smsc9218i_phy_clear_interrupts(regs); 571 smsc9218i_enable_phy_interrupts(regs); 572 573 media_ok = smsc9218i_media_status(e, &media); 574 mac_cr = smsc9218i_mac_read(regs, SMSC9218I_MAC_CR); 575 if (media_ok && (IFM_OPTIONS(media) & IFM_FDX) == 0) { 576 mac_cr &= ~SMSC9218I_MAC_CR_FDPX; 577 } else { 578 mac_cr |= SMSC9218I_MAC_CR_FDPX; 579 } 580 smsc9218i_mac_write(regs, SMSC9218I_MAC_CR, mac_cr); 581 } 582 583 static struct mbuf *smsc9218i_new_mbuf(struct ifnet *ifp) 584 { 585 struct mbuf *m = m_gethdr(M_WAIT, MT_DATA); 586 587 m->m_pkthdr.rcvif = ifp; 588 MCLGET(m, M_WAIT); 589 590 return m; 529 591 } 530 592 … … 593 655 594 656 if ((events & SMSC9218I_EVENT_PHY) != 0) { 595 uint32_t phy_isr = smsc9218i_phy_read(regs, SMSC9218I_PHY_ISR); 596 597 /* TODO */ 598 599 printf("rx: PHY event: 0x%08" PRIx32 "\n", phy_isr); 600 601 smsc9218i_enable_phy_interrupts(regs); 657 smsc9218i_media_status_change(e, regs); 602 658 } 603 659 … … 632 688 633 689 if ((rx_fifo_status & SMSC9218I_RX_STS_ERROR) == 0) { 634 struct mbuf *m = smsc9218i_new_mbuf(ifp , true);690 struct mbuf *m = smsc9218i_new_mbuf(ifp); 635 691 struct ether_header *eh = (struct ether_header *) 636 692 (mtod(m, char *) + SMSC9218I_RX_DATA_OFFSET); … … 707 763 708 764 /* Clear FIFO level status */ 709 regs->int_sts = SMSC9218I_INT_ STS_RSFL;765 regs->int_sts = SMSC9218I_INT_RSFL; 710 766 711 767 /* Next FIFO status */ … … 822 878 823 879 if (len < 4) { 824 printf("FIXME\n");880 ++jc->fixme_tiny_fragments; 825 881 } 826 882 … … 842 898 843 899 if (fragments > SMSC9218I_TX_FRAGMENT_MAX) { 844 printf("FIXME\n");900 ++jc->fixme_too_many; 845 901 } 846 902 … … 921 977 ); 922 978 923 __asm__ volatile ( "sync");924 925 979 /* Remember fragement */ 926 980 jc->fragment_table [c] = m; … … 990 1044 for (i = 0; i < n; ++i) { 991 1045 struct tcd_t *tcd = &jc->data_tcd_table [c]; 992 uint32_t data_length = tcd->NBYTES ;1046 uint32_t data_length = tcd->NBYTES + 14; 993 1047 994 1048 if (data_length <= data_free) { … … 1043 1097 /* Cache flush for last data TCD */ 1044 1098 rtems_cache_flush_multiple_data_lines(last, sizeof(*last)); 1099 ppc_synchronize_data(); 1045 1100 1046 1101 /* Start eDMA transfer */ … … 1089 1144 ++e->transmitted_frames; 1090 1145 } else { 1091 ++e->transmit_ errors;1146 ++e->transmit_frame_errors; 1092 1147 } 1093 1148 … … 1297 1352 #endif 1298 1353 1354 static void smsc9218i_wait_for_eeprom_access(volatile smsc9218i_registers *regs) 1355 { 1356 while ((regs->e2p_cmd & SMSC9218I_E2P_CMD_EPC_BUSY) != 0) { 1357 /* Wait */ 1358 } 1359 } 1360 1299 1361 static void smsc9218i_set_mac_address( 1300 1362 volatile smsc9218i_registers *regs, … … 1315 1377 } 1316 1378 1379 #if defined(DEBUG) 1317 1380 static void smsc9218i_mac_address_dump(volatile smsc9218i_registers *regs) 1318 1381 { … … 1331 1394 ); 1332 1395 } 1396 #endif 1333 1397 1334 1398 static void smsc9218i_interrupt_init( … … 1416 1480 /* Enable interrupts and use push-pull driver (active low) */ 1417 1481 regs->irq_cfg = SMSC9218I_IRQ_CFG_GLOBAL_ENABLE; 1482 1483 /* Enable error interrupts */ 1484 regs->int_en = SMSC9218I_ERROR_INTERRUPTS; 1418 1485 } 1419 1486 … … 1442 1509 } 1443 1510 1511 static void smsc9218i_hardware_reset(volatile smsc9218i_registers *regs) 1512 { 1513 smsc9218i_reset_signal_init(); 1514 smsc9218i_reset_signal(false); 1515 rtems_bsp_delay(200); 1516 smsc9218i_reset_signal(true); 1517 1518 while ((regs->pmt_ctrl & SMSC9218I_PMT_CTRL_READY) == 0) { 1519 /* Wait */ 1520 } 1521 } 1522 1444 1523 static void smsc9218i_interface_init(void *arg) 1445 1524 { … … 1451 1530 1452 1531 if (e->state == SMSC9218I_CONFIGURED) { 1453 /* Hardware reset */ 1454 smsc9218i_reset_signal_init(); 1455 smsc9218i_reset_signal(false); 1456 rtems_bsp_delay(200); 1457 smsc9218i_reset_signal(true); 1532 smsc9218i_hardware_reset(regs); 1458 1533 1459 1534 #if defined(DEBUG) … … 1466 1541 1467 1542 /* MAC address */ 1543 smsc9218i_wait_for_eeprom_access(regs); 1468 1544 smsc9218i_set_mac_address(regs, e->arpcom.ac_enaddr); 1545 #if defined(DEBUG) 1469 1546 smsc9218i_mac_address_dump(regs); 1547 #endif 1548 1549 /* Auto-negotiation advertisment */ 1550 smsc9218i_phy_write( 1551 regs, 1552 MII_ANAR, 1553 ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA 1554 ); 1470 1555 1471 1556 /* Initialize interrupts */ … … 1477 1562 /* Set FIFO interrupts */ 1478 1563 regs->fifo_int = SMSC9218I_FIFO_INT_TDAL(32); 1564 1565 /* Clear receive drop counter */ 1566 regs->rx_drop; 1479 1567 1480 1568 /* Start receive task */ … … 1520 1608 } 1521 1609 1522 static void smsc9218i_interface_stats(const smsc9218i_driver_entry *e) 1523 { 1524 printf("received frames: %u\n", e->received_frames); 1525 printf("receive interrupts: %u\n", e->receive_interrupts); 1526 printf("transmitted frames: %u\n", e->transmitted_frames); 1527 printf("transmit interrupts: %u\n", e->transmit_interrupts); 1528 printf("receive to long errors: %u\n", e->receive_too_long_errors); 1529 printf("receive collision errors: %u\n", e->receive_collision_errors); 1530 printf("receive CRC errors: %u\n", e->receive_crc_errors); 1531 printf("receive eDMA errors: %u\n", e->receive_edma_errors); 1532 printf("transmit errors: %u\n", e->transmit_errors); 1533 printf("transmit eDMA errors: %u\n", e->transmit_edma_errors); 1610 static int smsc9218i_mdio_read( 1611 int phy, 1612 void *arg, 1613 unsigned phy_reg, 1614 uint32_t *val 1615 ) 1616 { 1617 volatile smsc9218i_registers *const regs = smsc9218i; 1618 1619 *val = smsc9218i_phy_read(regs, phy_reg); 1620 1621 return 0; 1622 } 1623 1624 static int smsc9218i_mdio_write( 1625 int phy, 1626 void *arg, 1627 unsigned phy_reg, 1628 uint32_t data 1629 ) 1630 { 1631 volatile smsc9218i_registers *const regs = smsc9218i; 1632 1633 smsc9218i_phy_write(regs, phy_reg, data); 1634 1635 return 0; 1636 } 1637 1638 static void smsc9218i_interface_stats(smsc9218i_driver_entry *e) 1639 { 1640 volatile smsc9218i_registers *const regs = smsc9218i; 1641 smsc9218i_transmit_job_control *jc = &smsc_jc; 1642 int media = 0; 1643 bool media_ok = smsc9218i_media_status(e, &media); 1644 1645 if (media_ok) { 1646 rtems_ifmedia2str(media, NULL, 0); 1647 printf ("\n"); 1648 } else { 1649 printf ("PHY communication error\n"); 1650 } 1651 1652 e->receive_drop += SMSC9218I_SWAP(regs->rx_drop); 1653 1654 printf("received frames: %u\n", e->received_frames); 1655 printf("receive interrupts: %u\n", e->receive_interrupts); 1656 printf("transmitted frames: %u\n", e->transmitted_frames); 1657 printf("transmit interrupts: %u\n", e->transmit_interrupts); 1658 printf("receiver errors: %u\n", e->receiver_errors); 1659 printf("receive to long errors: %u\n", e->receive_too_long_errors); 1660 printf("receive collision errors: %u\n", e->receive_collision_errors); 1661 printf("receive CRC errors: %u\n", e->receive_crc_errors); 1662 printf("receive eDMA errors: %u\n", e->receive_edma_errors); 1663 printf("receive drops: %u\n", e->receive_drop); 1664 printf("receive watchdog timeouts: %u\n", e->receive_watchdog_timeouts); 1665 printf("transmitter errors: %u\n", e->transmitter_errors); 1666 printf("transmit status overflows: %u\n", e->transmit_status_overflows); 1667 printf("transmit frame errors: %u\n", e->transmit_frame_errors); 1668 printf("transmit eDMA errors: %u\n", e->transmit_edma_errors); 1669 printf("fixme tiny fragments: %u\n", jc->fixme_tiny_fragments); 1670 printf("fixme too many: %u\n", jc->fixme_too_many); 1534 1671 } 1535 1672 … … 1547 1684 case SIOCGIFMEDIA: 1548 1685 case SIOCSIFMEDIA: 1549 rtems_mii_ioctl(&e->mdio _info, e, (int) command, (int *) data);1686 rtems_mii_ioctl(&e->mdio, e, (int) command, (int *) data); 1550 1687 break; 1551 1688 case SIOCGIFADDR: … … 1641 1778 ifp->if_timer = 0; 1642 1779 1780 /* MDIO */ 1781 e->mdio.mdio_r = smsc9218i_mdio_read; 1782 e->mdio.mdio_w = smsc9218i_mdio_write; 1783 1643 1784 /* Change status */ 1644 1785 e->state = SMSC9218I_CONFIGURED; -
c/src/lib/libbsp/powerpc/mpc55xxevb/startup/bspstart.c
r1343dfa3 ra4475277 479 479 { 480 480 /* External Ethernet Controller (3 wait states, 64kB) */ 481 { 482 .B.TLBSEL = 1, /* MAS0 */ 483 .B.ESEL = 5 484 }, 485 { 486 .B.VALID = 1, /* MAS1 */ 487 .B.IPROT = 1, 488 .B.TSIZ = 1 489 }, 490 { 491 .B.EPN = 0x3fff8, /* MAS2 */ 492 .B.I = 1, 493 .B.G = 1 494 }, 495 { 496 .B.RPN = 0x3fff8, /* MAS3 */ 497 .B.UW = 1, 498 .B.SW = 1, 499 .B.UR = 1, 500 .B.SR = 1 501 } 481 .MAS0 = { .R = 0x10050000 }, 482 .MAS1 = { .R = 0xc0000100 }, 483 .MAS2 = { .R = 0x3fff800a }, 484 .MAS3 = { .R = 0x3fff800f } 502 485 } 503 486 #endif /* MMU setup */
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