Changeset a3db5001 in rtems


Ignore:
Timestamp:
Feb 28, 2019, 10:21:40 AM (8 weeks ago)
Author:
Sebastian Huber <sebastian.huber@…>
Branches:
master
Children:
03b2163
Parents:
76918e1
git-author:
Sebastian Huber <sebastian.huber@…> (02/28/19 10:21:40)
git-committer:
Sebastian Huber <sebastian.huber@…> (02/28/19 10:52:35)
Message:

bsp/altera-cyclone-v: Enable FIQ for group 0 irqs

File:
1 edited

Legend:

Unmodified
Added
Removed
  • bsps/arm/altera-cyclone-v/include/bsp.h

    r76918e1 ra3db5001  
    4040#define BSP_ARM_A9MPCORE_SCU_BASE 0xFFFEC000
    4141
     42#define BSP_ARM_GIC_ENABLE_FIQ_FOR_GROUP_0
     43
    4244#define BSP_ARM_GIC_CPUIF_BASE ( BSP_ARM_A9MPCORE_SCU_BASE + 0x00000100 )
    4345
    4446#define BSP_ARM_A9MPCORE_GT_BASE ( BSP_ARM_A9MPCORE_SCU_BASE + 0x00000200 )
     47
     48#define BSP_ARM_GIC_DIST_BASE ( BSP_ARM_A9MPCORE_SCU_BASE + 0x00001000 )
    4549
    4650#ifndef BSP_ARM_A9MPCORE_PERIPHCLK
     
    4953#define ALTERA_CYCLONE_V_NEED_A9MPCORE_PERIPHCLK
    5054#endif
    51 
    52 #define BSP_ARM_GIC_DIST_BASE ( BSP_ARM_A9MPCORE_SCU_BASE + 0x00001000 )
    5355
    5456#define BSP_ARM_L2C_310_BASE 0xfffef000
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