Changeset a385489 in rtems


Ignore:
Timestamp:
Aug 18, 2011, 9:00:14 AM (9 years ago)
Author:
Chris Johns <chrisj@…>
Branches:
4.11, 5, master
Children:
74ac113
Parents:
b7ee9ab
Message:

2011-08-18 Chris Johns <chrisj@…>

  • cpu.c: Fix the ISR get level for the IIC. Make _CPU_Context_Initialize a function rather than inlined.
  • cpu_asm.S: Do not enable interrupt on return, rather resume the state on entry to the ISR.
  • irq.c, nios2/nios2-iic-low-level.S: Change the ISR handler so the ipending decoding is in C and within the interrupt context. This is usable with the Altera HAL directly.
  • rtems/score/cpu.h: Add ienable and ipending interfaces. Add some comments. Remove _CPU_Context_Initialize.
Location:
cpukit/score/cpu/nios2
Files:
6 edited

Legend:

Unmodified
Added
Removed
  • cpukit/score/cpu/nios2/ChangeLog

    rb7ee9ab ra385489  
     12011-08-18      Chris Johns <chrisj@rtems.org>
     2
     3        * cpu.c: Fix the ISR get level for the IIC. Make
     4        _CPU_Context_Initialize a function rather than inlined.
     5        * cpu_asm.S: Do not enable interrupt on return, rather resume the
     6        state on entry to the ISR.
     7        * irq.c, nios2/nios2-iic-low-level.S: Change the ISR handler so
     8        the ipending decoding is in C and within the interrupt
     9        context. This is usable with the Altera HAL directly.
     10        * rtems/score/cpu.h: Add ienable and ipending interfaces. Add some
     11        comments. Remove _CPU_Context_Initialize.
     12
    1132011-08-14      Chris Johns <chrisj@rtems.org>
    214
  • cpukit/score/cpu/nios2/cpu.c

    rb7ee9ab ra385489  
    1919#include <rtems/score/isr.h>
    2020#include <rtems/score/wkspace.h>
     21
     22#include <rtems/score/nios2.h>
    2123
    2224/*  _CPU_Initialize
     
    4547/*
    4648 *  _CPU_ISR_Get_level
    47  *
    48  *  NO_CPU Specific Information:
    49  *
    50  *  XXX document implementation including references if appropriate
    5149 */
    5250
    5351uint32_t   _CPU_ISR_Get_level( void )
    5452{
    55   /*
    56    *  This routine returns the current interrupt level.
    57    */
     53  /* @todo Add EIC support. */
     54  uint32_t status = __builtin_rdctl(0);
     55  return status & 1 ? 0 : 1;
     56}
    5857
    59   return 0;
     58/*
     59 * FIXME: Evaluate interrupt level.
     60 */
     61void _CPU_Context_Initialize(
     62  Context_Control  *the_context,
     63  uint32_t         *stack_base,
     64  uint32_t          size,
     65  uint32_t          new_level,
     66  void             *entry_point,
     67  bool              is_fp
     68)
     69{
     70  uint32_t stack = (uint32_t)stack_base + size - 4;
     71  the_context->fp = stack;
     72  the_context->sp = stack;
     73  the_context->ra = (intptr_t) entry_point;
     74  /* @todo Add EIC support. */
     75  the_context->status = new_level ? 0 : 1;
    6076}
    6177
  • cpukit/score/cpu/nios2/cpu_asm.S

    rb7ee9ab ra385489  
    7171    ldw ea,  40(r5)
    7272    ldw at,  44(r5)
    73     /* FIXME: Always have interrupts enabled when we return from Context_switch */
    74     ori at, at, 1
    7573    wrctl estatus, at
    7674
  • cpukit/score/cpu/nios2/irq.c

    rb7ee9ab ra385489  
    3535register unsigned long  *stack_ptr __asm__ ("sp");
    3636
    37 RTEMS_INLINE_ROUTINE void
    38 __Dipatch_interrupt_vector(uint32_t vector, proc_ptr pp)
    39 {
    40   if ( _ISR_Vector_table[ vector] )
    41   {
    42     (*_ISR_Vector_table[ vector ])(vector, pp);
    43   };
    44 }
    45 
    46 #if (RTEMS_NIOS_USE_ALT_HAL == TRUE)
    47 
    48 #include <bsp/alt/nios2.h>
    49 
    5037RTEMS_INLINE_ROUTINE void __IIC_Handler(void)
    5138{
     
    5744   * Obtain from the interrupt controller a bit list of pending interrupts,
    5845   * and then process the highest priority interrupt. This process loops,
    59    * loading the active interrupt list on each pass until alt_irq_pending()
     46   * loading the active interrupt list on each pass until ipending
    6047   * return zero.
    6148   *
     
    6754   */
    6855
    69   NIOS2_READ_IPENDING (active);
     56  _CPU_read_ipending (active);
    7057
    7158  while (active)
     
    7663    /*
    7764     * Test each bit in turn looking for an active interrupt. Once one is
    78      * found, the interrupt handler asigned by a call to alt_irq_register() is
    79      * called to clear the interrupt condition.
     65     * found call it to clear the interrupt condition.
    8066     */
    8167
     
    8470      if (active & mask)
    8571      {
    86         __Dipatch_interrupt_vector(vector, NULL);
     72        if ( _ISR_Vector_table[ vector] )
     73          (*_ISR_Vector_table[ vector ])(vector, NULL);
    8774        active &= ~mask;
    8875      }
     
    9178    };
    9279
    93     NIOS2_READ_IPENDING (active);
     80    _CPU_read_ipending (active);
    9481  }
    9582 
    9683}
    97 #endif
    9884
    99 #if (RTEMS_NIOS_USE_ALT_HAL == TRUE)
    10085void __ISR_Handler(void)
    101 #else
    102 void __ISR_Handler(uint32_t vector, CPU_Interrupt_frame *ifr)
    103 #endif
    10486{
    105   register uint32_t   level;
     87  register uint32_t level;
    10688
    10789  /* Interrupts are disabled upon entry to this Handler */
     
    119101  _Thread_Dispatch_increment_disable_level();
    120102
    121 #if (RTEMS_NIOS_USE_ALT_HAL == TRUE)
    122103  __IIC_Handler();
    123 #else
    124   __Dipatch_interrupt_vector(vector, ifr);
    125 #endif
    126104 
    127105  /* Make sure that interrupts are disabled again */
  • cpukit/score/cpu/nios2/nios2-iic-low-level.S

    rb7ee9ab ra385489  
    232232    stw ea,  72(sp)
    233233
     234#if REMOVED_BY_CCJ
    234235    /*
    235236     * Obtain a bitlist of the pending interrupts.
     
    267268
    268269    mov     r5, sp
    269 
     270#endif
     271       
    270272    .extern __ISR_Handler
    271273    call    __ISR_Handler
  • cpukit/score/cpu/nios2/rtems/score/cpu.h

    rb7ee9ab ra385489  
    190190#endif
    191191
     192/**
     193 *  @brief Read the ienable register.
     194 */
     195#define _CPU_read_ienable( value ) \
     196    do { value = __builtin_rdctl(3); } while (0)
     197
     198/**
     199 *  @brief Write the ienable register.
     200 */
     201#define _CPU_write_ienable( value ) \
     202    do { __builtin_wrctl(3, value); } while (0)
     203
     204/**
     205 *  @brief Read the ipending register.
     206 */
     207#define _CPU_read_ipending( value ) \
     208    do { value = __builtin_rdctl(4); } while (0)
     209
     210/**
     211 *  Disable all interrupts for a critical section.  The previous
     212 *  level is returned in _level.
     213 */
    192214#define _CPU_ISR_Disable( _isr_cookie ) \
    193215  do { \
     
    196218  } while ( 0 )
    197219
     220/**
     221 *  Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
     222 *  This indicates the end of a critical section.  The parameter
     223 *  _level is not modified.
     224 */
    198225#define _CPU_ISR_Enable( _isr_cookie ) \
    199226  do { \
     
    201228  } while ( 0 )
    202229
     230/**
     231 *  This temporarily restores the interrupt to _level before immediately
     232 *  disabling them again.  This is used to divide long critical
     233 *  sections into two or more parts.  The parameter _level is not
     234 *  modified.
     235 */
    203236#define _CPU_ISR_Flash( _isr_cookie ) \
    204237  do { \
     
    207240  } while ( 0 )
    208241
    209 #define _CPU_ISR_Set_level( new_level ) \
     242/**
     243 *  Map interrupt level in task mode onto the hardware that the CPU
     244 *  actually provides.  Currently, interrupt levels which do not
     245 *  map onto the CPU in a straight fashion are undefined.
     246 */
     247#define _CPU_ISR_Set_level( new_level )      \
    210248  _CPU_ISR_Enable( new_level == 0 ? 1 : 0 );
    211249
     250/**
     251 *  @brief Obtain the Current Interrupt Disable Level
     252 *
     253 *  This method is invoked to return the current interrupt disable level.
     254 *
     255 *  @return This method returns the current interrupt disable level.
     256 */
    212257uint32_t _CPU_ISR_Get_level( void );
    213258
    214 /*
    215  * FIXME: Evaluate interrupt level.
    216  */
    217 #define _CPU_Context_Initialize( _the_context, _stack_base, _size, \
    218                                  _isr, _entry_point, _is_fp ) \
    219   do { \
    220     uint32_t _stack = (uint32_t)(_stack_base) + (_size) - 4; \
    221     (_the_context)->fp = (void *)_stack; \
    222     (_the_context)->sp = (void *)_stack; \
    223     (_the_context)->ra = (void *)(_entry_point); \
    224     (_the_context)->status  = 0x1; /* IRQs enabled */ \
    225   } while ( 0 )
     259/**
     260 *  Initialize the context to a state suitable for starting a
     261 *  task after a context restore operation.  Generally, this
     262 *  involves:
     263 *
     264 *  - setting a starting address
     265 *  - preparing the stack
     266 *  - preparing the stack and frame pointers
     267 *  - setting the proper interrupt level in the context
     268 *  - initializing the floating point context
     269 *
     270 * @param[in] the_context points to the context area
     271 * @param[in] stack_base is the low address of the allocated stack area
     272 * @param[in] size is the size of the stack area in bytes
     273 * @param[in] new_level is the interrupt level for the task
     274 * @param[in] entry_point is the task's entry point
     275 * @param[in] is_fp is set to TRUE if the task is a floating point task
     276 *
     277 *  @note  Implemented as a subroutine for the NIOS2 port.
     278 */
     279void _CPU_Context_Initialize(
     280  Context_Control  *the_context,
     281  uint32_t         *stack_base,
     282  uint32_t          size,
     283  uint32_t          new_level,
     284  void             *entry_point,
     285  bool              is_fp
     286);
    226287
    227288#define _CPU_Context_Restart_self( _the_context ) \
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