Changeset a321f7a in rtems


Ignore:
Timestamp:
Sep 10, 2007, 1:54:12 PM (12 years ago)
Author:
Joel Sherrill <joel.sherrill@…>
Branches:
4.10, 4.11, 4.8, 4.9, master
Children:
27d33ed
Parents:
c040e6ec
Message:

2007-09-10 Alain Schaefer <alani@…>

  • rtems/bfin/bf533.h: Add more definitions.
Location:
cpukit/score/cpu/bfin
Files:
2 edited

Legend:

Unmodified
Added
Removed
  • cpukit/score/cpu/bfin/ChangeLog

    rc040e6ec ra321f7a  
     12007-09-10      Alain Schaefer <alani@easc.ch>
     2
     3        * rtems/bfin/bf533.h: Add more definitions.
     4
    152007-05-31      Alain Schaefer <alani@easc.ch>
    26
  • cpukit/score/cpu/bfin/rtems/bfin/bf533.h

    rc040e6ec ra321f7a  
    359359#define EBIU_SDSTAT            0xFFC00A1CL
    360360
     361
     362
     363
     364/* DCPLB_DATA and ICPLB_DATA Registers */
     365/*** Bit Positions */
     366#define CPLB_VALID_P            0x00000000  /* 0=invalid entry, 1=valid entry */
     367#define CPLB_LOCK_P             0x00000001  /* 0=entry may be replaced, 1=entry locked */
     368#define CPLB_USER_RD_P          0x00000002  /* 0=no read access, 1=read access allowed (user mode) */
     369/*** Masks */
     370#define CPLB_VALID             0x00000001  /* 0=invalid entry, 1=valid entry */
     371#define CPLB_LOCK              0x00000002  /* 0=entry may be replaced, 1=entry locked */
     372#define CPLB_USER_RD           0x00000004  /* 0=no read access, 1=read access allowed (user mode) */
     373#define PAGE_SIZE_1KB          0x00000000  /* 1 KB page size */
     374#define PAGE_SIZE_4KB          0x00010000  /* 4 KB page size */
     375#define PAGE_SIZE_1MB          0x00020000  /* 1 MB page size */
     376#define PAGE_SIZE_4MB          0x00030000  /* 4 MB page size */
     377#define CPLB_PORTPRIO             0x00000200  /* 0=low priority port, 1= high priority port */
     378#define CPLB_L1_CHBL           0x00001000  /* 0=non-cacheable in L1, 1=cacheable in L1 */
     379/*** ICPLB_DATA only */
     380#define CPLB_LRUPRIO              0x00000100  /* 0=can be replaced by any line, 1=priority for non-replacement */
     381/*** DCPLB_DATA only */
     382#define CPLB_USER_WR           0x00000008  /* 0=no write access, 0=write access allowed (user mode) */
     383#define CPLB_SUPV_WR           0x00000010  /* 0=no write access, 0=write access allowed (supervisor mode) */
     384#define CPLB_DIRTY             0x00000080  /* 1=dirty, 0=clean */
     385#define CPLB_L1_AOW                       0x00008000  /* 0=do not allocate cache lines on write-through writes,  */
     386                                                                                  /* 1= allocate cache lines on write-through writes. */
     387#define CPLB_WT                0x00004000  /* 0=write-back, 1=write-through */
     388
     389
    361390#ifdef __cplusplus
    362391}
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