Changeset a191b28 in rtems


Ignore:
Timestamp:
May 14, 2002, 5:54:22 PM (18 years ago)
Author:
Joel Sherrill <joel.sherrill@…>
Branches:
4.10, 4.11, 4.8, 4.9, master
Children:
c7286d9
Parents:
830e5f7
Message:

2001-05-14 Till Straumann <strauman@…>

  • bootloader/Makefile.am, console/Makefile.am, pci/Makefile.am: Per PR215 address the following issues:
    • _IO_BASE, _ISA_MEM_BASE and PCI_DRAM_OFFSET are no longer defined by libcpu (powerpc/shared/include/io.h) but by the BSP (who is the only one to know the values)
    • the affected BSP (shared/motorola) headers have been fixed in a separate "libbsp/powerpc/shared" patch.
    • the DEC 21140 driver (libchip/network/dec21140.c) has been fixed to use PCI_DRAM_OFFSET instead of PREP_PCI_DRAM_OFFSET. and PCI_MEM_BASE instead of PREP_ISA_MEM_BASE. PCI_MEM_BASE is to be defined by the BSP who is using this driver.
    • the DEC driver also has been fixed to use the newer rtems_bsp_delay_in_bus_cycles() instead of the obsolete delay_in_bus_cycles().
File:
1 edited

Legend:

Unmodified
Added
Removed
  • c/src/libchip/network/dec21140.c

    r830e5f7 ra191b28  
    186186
    187187#if defined(__PPC)
    188 #define phys_to_bus(address) ((unsigned int)((address)) + PREP_PCI_DRAM_OFFSET)
    189 #define bus_to_phys(address) ((unsigned int)((address)) - PREP_PCI_DRAM_OFFSET)
     188#define phys_to_bus(address) ((unsigned int)((address)) + PCI_DRAM_OFFSET)
     189#define bus_to_phys(address) ((unsigned int)((address)) - PCI_DRAM_OFFSET)
    190190#define CPU_CACHE_ALIGNMENT_FOR_BUFFER PPC_CACHE_ALIGNMENT
    191191#else
     
    193193#define phys_to_bus(address) ((unsigned int) ((address)))
    194194#define bus_to_phys(address) ((unsigned int) ((address)))
    195 #define delay_in_bus_cycles(cycle) Wait_X_ms( cycle/100 )
     195#define rtems_bsp_delay_in_bus_cycles(cycle) Wait_X_ms( cycle/100 )
    196196#define CPU_CACHE_ALIGNMENT_FOR_BUFFER PG_SIZE
    197197
     
    332332                short dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
    333333                st_le32(ioaddr, EE_ENB | dataval);
    334                 delay_in_bus_cycles(200);
     334                rtems_bsp_delay_in_bus_cycles(200);
    335335                st_le32(ioaddr, EE_ENB | dataval | EE_SHIFT_CLK);
    336                 delay_in_bus_cycles(200);
     336                rtems_bsp_delay_in_bus_cycles(200);
    337337                st_le32(ioaddr, EE_ENB | dataval); /* Finish EEPROM a clock tick. */
    338                 delay_in_bus_cycles(200);
     338                rtems_bsp_delay_in_bus_cycles(200);
    339339        }
    340340        st_le32(ioaddr, EE_ENB);
     
    342342        for (i = 16; i > 0; i--) {
    343343                st_le32(ioaddr, EE_ENB | EE_SHIFT_CLK);
    344                 delay_in_bus_cycles(200);
     344                rtems_bsp_delay_in_bus_cycles(200);
    345345                retval = (retval << 1) | ((ld_le32(ioaddr) & EE_DATA_READ) ? 1 : 0);
    346346                st_le32(ioaddr, EE_ENB);
    347                 delay_in_bus_cycles(200);
     347                rtems_bsp_delay_in_bus_cycles(200);
    348348        }
    349349
     
    374374  st_le32( (tbase+memCSR6), CSR6_INIT); 
    375375  st_le32( (tbase+memCSR0), RESET_CHIP); 
    376   delay_in_bus_cycles(200);
     376  rtems_bsp_delay_in_bus_cycles(200);
    377377
    378378  /*
     
    894894
    895895        tmp = (unsigned int)(lvalue & (unsigned int)(~MEM_MASK))
    896           + (unsigned int)PREP_ISA_MEM_BASE;
     896          + (unsigned int)PCI_MEM_BASE;
    897897        sc->base = (unsigned int *)(tmp);
    898898
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