Changeset a11e1ff5 in rtems


Ignore:
Timestamp:
Mar 7, 2017, 6:58:11 AM (3 years ago)
Author:
Sebastian Huber <sebastian.huber@…>
Branches:
master
Children:
088acbb0
Parents:
c6f76392
Message:

powerpc: Optimize AltiVec? context switch

Use r8 instead of r5 to slightly optimize _CPU_Context_switch(). It is
not a big deal, however, we already assume r12 is used by
_CPU_Context_switch(). Treat r5 the in same way.

Location:
c/src/lib/libcpu/powerpc
Files:
2 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libcpu/powerpc/mpc6xx/altivec/vec_sup_asm.S

    rc6f76392 ra11e1ff5  
    7474        .set   r3,   3
    7575        .set   r4,   4
    76         .set   r5,   5
     76        /* Do not use r5, since this is used by _CPU_Context_switch() */
    7777        .set   r6,   6
    7878        .set   r7,   7
     79        .set   r8,   8
    7980        .set   r9,   9
    8081        .set   r10, 10
     
    579580#endif
    580581
    581         PREP_FOR_SAVE r0, r3, r4, r5, r6, r10
     582        PREP_FOR_SAVE r0, r3, r4, r8, r6, r10
    582583        /* r0 now contains VRSAVE, r3 still the aligned memory area
    583          * and r4, r5, r6 are offset by 16, 32, and 48 bytes from r3,
     584         * and r4, r8, r6 are offset by 16, 32, and 48 bytes from r3,
    584585         * respectively. r10 holds zero
    585586         */
    586         S_V0TOV19     _B0=r3, _B1=r4, _B2=r5, _B3=r6, _O1=r10, _O2=r11
     587        S_V0TOV19     _B0=r3, _B1=r4, _B2=r8, _B3=r6, _O1=r10, _O2=r11
    587588        mfvscr        v0
    588589        /* Store vrsave (still in r0) and vscr (in v0) to memory area */
     
    614615        dcbt      0, r3
    615616        L_VSCR_VRSAVE r3, r0, v0
    616         CMP_BASES     r3, r4, r5, r6, r10
     617        CMP_BASES     r3, r4, r8, r6, r10
    617618        /* Start preloading 3rd line (where vectors 3 and 4 are)      */
    618         dcbt      0, r5
    619         L_V0TOV19 r3, r4, r5, r6, r10, r11
     619        dcbt      0, r8
     620        L_V0TOV19 r3, r4, r8, r6, r10, r11
    620621
    621622#ifndef IGNORE_VRSAVE
     
    628629
    629630        /* fetch offset of altivec area in context                   */
    630         CMPOFF    r5
     631        CMPOFF    r8
    631632        /* down-align 'to' area to cache-line boundary               */
    632         add       r4, r4, r5
     633        add       r4, r4, r8
    633634        CACHE_DOWNALGN r4
    634635
     
    659660        /* SAVE NON-VOLATILE REGISTERS                               */
    660661
    661         /* Compute aligned destination pointer (r5 still holds offset
     662        /* Compute aligned destination pointer (r8 still holds offset
    662663         * to 'altivec' area in context)
    663664         */
    664         add       r3, r3, r5
     665        add       r3, r3, r8
    665666        CACHE_DOWNALGN r3
    666667
    667         PREP_FOR_SAVE r0, r3, r5, r6, r7, r10
     668        PREP_FOR_SAVE r0, r3, r8, r6, r7, r10
    668669        /* The manual says reading vscr can take some time - do
    669670         * read it here (into a volatile vector register) while
     
    671672         */
    672673        mfvscr    v0
    673         S_V20TOV31 _LRU=l, _B0=r3, _B1=r5, _B2=r6, _B3=r7, _O1=r10, _O2=r11
     674        S_V20TOV31 _LRU=l, _B0=r3, _B1=r8, _B2=r6, _B3=r7, _O1=r10, _O2=r11
    674675        /* vrsave is now in r0 (PREP_FOR_SAVE), vscr in v0 */
    675         S_VSCR_VRSAVE r0, v0, r3, r5
     676        S_VSCR_VRSAVE r0, v0, r3, r8
    676677
    6776781:
     
    682683        addi      r4, r4, PPC_CACHE_ALIGNMENT
    683684        L_VSCR_VRSAVE r4, r0, v0
    684         CMP_BASES r4, r5, r6, r7, r10
    685         L_V20TOV31 r4, r5, r6, r7, r10, r11
     685        CMP_BASES r4, r8, r6, r7, r10
     686        L_V20TOV31 r4, r8, r6, r7, r10, r11
    686687
    687688#ifndef IGNORE_VRSAVE
     
    692693        .global _CPU_Context_initialize_altivec
    693694_CPU_Context_initialize_altivec:
    694         CMPOFF    r5
    695         add       r3, r3, r5
     695        CMPOFF    r8
     696        add       r3, r3, r8
    696697        CACHE_DOWNALGN r3
    697         lis       r5, _CPU_altivec_vrsave_initval@ha
    698         lwz       r5, _CPU_altivec_vrsave_initval@l(r5)
    699         stw       r5, VRSAVE_OFF(r3)
     698        lis       r8, _CPU_altivec_vrsave_initval@ha
     699        lwz       r8, _CPU_altivec_vrsave_initval@l(r8)
     700        stw       r8, VRSAVE_OFF(r3)
    700701        lis       r6, _CPU_altivec_vscr_initval@ha
    701702        lwz       r6, _CPU_altivec_vscr_initval@l(r6)
     
    716717        .global _CPU_altivec_set_vrsave_initval
    717718_CPU_altivec_set_vrsave_initval:
    718         lis       r5, _CPU_altivec_vrsave_initval@ha
    719         stw       r3, _CPU_altivec_vrsave_initval@l(r5)
     719        lis       r8, _CPU_altivec_vrsave_initval@ha
     720        stw       r3, _CPU_altivec_vrsave_initval@l(r8)
    720721        mtvrsave  r3
    721722        blr
     
    772773        dcbt      0, r3
    773774        L_VSCR_VRSAVE r3, r0, v0
    774         CMP_BASES     r3, r4, r5, r6, r10
     775        CMP_BASES     r3, r4, r8, r6, r10
    775776        /* Start preloading 3rd line (where vectors 3 and 4 are)      */
    776         dcbt      0, r5
    777         L_V0TOV31 r3, r4, r5, r6, r10, r11
     777        dcbt      0, r8
     778        L_V0TOV31 r3, r4, r8, r6, r10, r11
    778779
    779780#ifndef IGNORE_VRSAVE
     
    795796#endif
    796797
    797         PREP_FOR_SAVE r0, r3, r4, r5, r6, r10
     798        PREP_FOR_SAVE r0, r3, r4, r8, r6, r10
    798799        /* r0 now contains VRSAVE, r3 still the aligned memory area
    799          * and r4, r5, r6 are offset by 16, 32, and 48 bytes from r3,
     800         * and r4, r8, r6 are offset by 16, 32, and 48 bytes from r3,
    800801         * respectively. r10 holds zero
    801802         */
    802         S_V0TOV31     _B0=r3, _B1=r4, _B2=r5, _B3=r6, _O1=r10, _O2=r11
     803        S_V0TOV31     _B0=r3, _B1=r4, _B2=r8, _B3=r6, _O1=r10, _O2=r11
    803804        mfvscr        v0
    804805        /* Store vrsave (still in r0) and vscr (in v0) to memory area */
  • c/src/lib/libcpu/powerpc/new-exceptions/cpu_asm.S

    rc6f76392 ra11e1ff5  
    436436
    437437#if defined(__ALTIVEC__) && !defined(PPC_MULTILIB_ALTIVEC)
    438         mr      r14, r5
    439438        mr      r4, r5
    440439        .extern _CPU_Context_switch_altivec
    441440        bl      _CPU_Context_switch_altivec
    442         mr      r5, r14
    443441#endif
    444442
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