Changeset 9ee2ec5 in rtems


Ignore:
Timestamp:
Apr 17, 2014, 7:43:30 AM (5 years ago)
Author:
Ralf Kirchner <ralf.kirchner@…>
Branches:
4.11, master
Children:
cbd9e63
Parents:
e331e69
git-author:
Ralf Kirchner <ralf.kirchner@…> (04/17/14 07:43:30)
git-committer:
Sebastian Huber <sebastian.huber@…> (04/17/14 11:25:11)
Message:

bsp/arm: Consistenly same handling for flushing

It is importeant to consistently apply the same handling for flushing within
level 2 and level 1 cache handling. In this case now both handling use clean and invalidate.

File:
1 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/arm/shared/include/arm-cache-l1.h

    re331e69 r9ee2ec5  
    253253
    254254    for (; adx <= ADDR_LAST; adx += ARM_CACHE_L1_CPU_DATA_ALIGNMENT ) {
    255       /* Store the Data cache line */
    256       arm_cp15_data_cache_clean_line( (void*)adx );
     255      /* Store and invalidate the Data cache line */
     256      arm_cp15_data_cache_clean_and_invalidate_line( (void*)adx );
    257257    }
    258258    /* Wait for L1 store to complete */
Note: See TracChangeset for help on using the changeset viewer.