Changeset 9e7758b in rtems


Ignore:
Timestamp:
Aug 31, 2011, 4:03:10 PM (9 years ago)
Author:
Sebastian Huber <sebastian.huber@…>
Branches:
4.11, master
Children:
d783a1e
Parents:
f23c9ed
Message:

2011-08-31 Sebastian Huber <sebastian.huber@…>

  • startup/bspgetworkarea.c, startup/linkcmds.base: Removed files.
  • include/mpc55xx-config.h, make/custom/mpc5674fevb.cfg, startup/early-init.c, startup/ebi-cal-cs-config.c, startup/ebi-cs-config.c, startup/exc-vector-base.S, startup/fmpll-syncr-vals.c, startup/linkcmds.mpc5674fevb, startup/mmu-config.c, startup/siu-pcr-config.c: New files.
  • Makefile.am, preinstall.am: Reflect changes above.
  • startup/linkcmds.gwlcfm, startup/linkcmds.mpc5566evb, startup/linkcmds.phycore_mpc5554: Use linker command base file.
  • configure.ac: Support MPC5674F. Changed eSCI options.
  • clock/clock-config.c: Support MPC5674F.
  • i2c/i2c_init.c, network/smsc9218i.c, startup/sd-card-init.c: Update due to API changes.
  • include/bsp.h: Define BSP_INTERRUPT_STACK_AT_WORK_AREA_BEGIN.
  • network/if_smc.c: Use HAS_SMC91111.
  • startup/start.S, startup/bspstart.c: Moved low-level initialization into new files. Overall cleanup.
Location:
c/src/lib/libbsp/powerpc/mpc55xxevb
Files:
10 added
2 deleted
15 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/powerpc/mpc55xxevb/ChangeLog

    rf23c9ed r9e7758b  
     12011-08-31      Sebastian Huber <sebastian.huber@embedded-brains.de>
     2
     3        * startup/bspgetworkarea.c, startup/linkcmds.base: Removed files.
     4        * include/mpc55xx-config.h, make/custom/mpc5674fevb.cfg,
     5        startup/early-init.c, startup/ebi-cal-cs-config.c,
     6        startup/ebi-cs-config.c, startup/exc-vector-base.S,
     7        startup/fmpll-syncr-vals.c, startup/linkcmds.mpc5674fevb,
     8        startup/mmu-config.c, startup/siu-pcr-config.c: New files.
     9        * Makefile.am, preinstall.am: Reflect changes above.
     10        * startup/linkcmds.gwlcfm, startup/linkcmds.mpc5566evb,
     11        startup/linkcmds.phycore_mpc5554: Use linker command base file.
     12        * configure.ac: Support MPC5674F.  Changed eSCI options.
     13        * clock/clock-config.c: Support MPC5674F.
     14        * i2c/i2c_init.c, network/smsc9218i.c, startup/sd-card-init.c: Update
     15        due to API changes.
     16        * include/bsp.h: Define BSP_INTERRUPT_STACK_AT_WORK_AREA_BEGIN.
     17        * network/if_smc.c: Use HAS_SMC91111.
     18        * startup/start.S, startup/bspstart.c: Moved low-level initialization
     19        into new files.  Overall cleanup.
     20
    1212011-08-30      Peter Dufault <dufault@hda.com>
    222
  • c/src/lib/libbsp/powerpc/mpc55xxevb/Makefile.am

    rf23c9ed r9e7758b  
    2525# Link commands
    2626project_lib_DATA += startup/linkcmds
    27 dist_project_lib_DATA += \
    28         startup/linkcmds.gwlcfm \
    29         startup/linkcmds.phycore_mpc5554 \
    30         startup/linkcmds.mpc5566evb \
    31         startup/linkcmds.base
     27dist_project_lib_DATA += ../shared/startup/linkcmds.base       
     28dist_project_lib_DATA += startup/linkcmds.gwlcfm
     29dist_project_lib_DATA += startup/linkcmds.mpc5566evb
     30dist_project_lib_DATA += startup/linkcmds.mpc5674fevb
     31dist_project_lib_DATA += startup/linkcmds.phycore_mpc5554
    3232
    3333noinst_LIBRARIES += libbsp.a
     
    4242include_bsp_HEADERS = include/mpc55xxevb.h \
    4343    include/smsc9218i.h \
     44    include/mpc55xx-config.h \
    4445    ../../../libcpu/powerpc/mpc83xx/i2c/mpc83xx_i2cdrv.h \
    4546    ../../shared/include/irq-generic.h \
    4647    ../../shared/include/irq-info.h \
    4748    ../../shared/include/utility.h \
     49    ../shared/include/linker-symbols.h \
    4850    ../shared/include/start.h \
    4951    ../shared/include/tictac.h
    5052
    5153# startup
    52 libbsp_a_SOURCES += ../../shared/bsplibc.c ../../shared/bsppost.c \
    53     ../../shared/bootcard.c ../shared/src/tictac.c ../../shared/bspclean.c \
    54     ../shared/startup/bspidle.c startup/bspstart.c startup/bspgetworkarea.c \
    55     ../../shared/bsppretaskinghook.c \
    56     ../shared/src/memcpy.c \
    57     ../shared/src/bsp-start-zero.S
     54libbsp_a_SOURCES += ../../shared/bootcard.c
     55libbsp_a_SOURCES += ../../shared/bspclean.c
     56libbsp_a_SOURCES += ../../shared/bsplibc.c
     57libbsp_a_SOURCES += ../../shared/bsppost.c
     58libbsp_a_SOURCES += ../../shared/bsppredriverhook.c
     59libbsp_a_SOURCES += ../../shared/bsppretaskinghook.c
     60libbsp_a_SOURCES += ../../shared/bspgetworkarea.c
     61libbsp_a_SOURCES += ../shared/src/bsp-start-zero.S
     62libbsp_a_SOURCES += ../shared/src/memcpy.c
     63libbsp_a_SOURCES += ../shared/src/tictac.c
     64libbsp_a_SOURCES += ../shared/startup/bspidle.c
     65libbsp_a_SOURCES += startup/bspstart.c
     66libbsp_a_SOURCES += startup/fmpll-syncr-vals.c
     67libbsp_a_SOURCES += startup/exc-vector-base.S
     68libbsp_a_SOURCES += startup/ebi-cs-config.c
     69libbsp_a_SOURCES += startup/ebi-cal-cs-config.c
     70libbsp_a_SOURCES += startup/mmu-config.c
     71libbsp_a_SOURCES += startup/siu-pcr-config.c
     72libbsp_a_SOURCES += startup/early-init.c
    5873
    5974# clock
     
    7590# Network
    7691if HAS_NETWORKING
    77 libbsp_a_SOURCES += network/smsc9218i.c network/if_smc.c
     92libbsp_a_SOURCES += network/smsc9218i.c
     93libbsp_a_SOURCES += network/if_smc.c
    7894endif
    7995
  • c/src/lib/libbsp/powerpc/mpc55xxevb/clock/clock-config.c

    rf23c9ed r9e7758b  
    5050
    5151  sc = mpc55xx_interrupt_handler_install(
    52     MPC55XX_IRQ_EMIOS_GET_REQUEST( MPC55XX_CLOCK_EMIOS_CHANNEL),
     52    MPC55XX_IRQ_EMIOS( MPC55XX_CLOCK_EMIOS_CHANNEL),
    5353    "clock",
    5454    RTEMS_INTERRUPT_UNIQUE,
     
    9797  regs->CSR.R = csr.R;
    9898
     99  /* Set internal counter start value */
     100  regs->CCNTR.R = 1;
     101
    99102  /* Set timer period */
    100103  regs->CADR.R = (uint32_t) interval - 1;
    101104
    102   /* Set unused registers */
    103   regs->CBDR.R = 0;
    104   regs->CCNTR.R = 0;
    105 #if MPC55XX_CHIP_TYPE != 5554
    106   /* This is reserved on the MPC5554.
    107    */
    108   regs->ALTCADR.R = 0;
    109 #endif
    110 
    111105  /* Set control register */
    112   /* The mode change, made by Thomas for GW_LCFM support, breaks interrupts
    113    * on the MPC5554.
    114    */
    115 #if MPC55XX_CHIP_TYPE == 5554
     106#if MPC55XX_CHIP_TYPE / 10 == 551
     107  ccr.B.MODE = MPC55XX_EMIOS_MODE_MCB_UP_INT_CLK;
     108#else
    116109  ccr.B.MODE = MPC55XX_EMIOS_MODE_MC_UP_INT_CLK;
    117 #else
    118   ccr.B.MODE = MPC55XX_EMIOS_MODE_MCB_UP_INT_CLK;
    119110#endif
    120111  ccr.B.UCPREN = 1;
     
    136127  /* Remove interrupt handler */
    137128  sc = rtems_interrupt_handler_remove(
    138     MPC55XX_IRQ_EMIOS_GET_REQUEST( MPC55XX_CLOCK_EMIOS_CHANNEL),
     129    MPC55XX_IRQ_EMIOS( MPC55XX_CLOCK_EMIOS_CHANNEL),
    139130    (rtems_interrupt_handler) Clock_isr,
    140131    NULL
  • c/src/lib/libbsp/powerpc/mpc55xxevb/configure.ac

    rf23c9ed r9e7758b  
    2626RTEMS_BSPOPTS_SET_DATA_CACHE_ENABLED([gwlcfm],[])
    2727RTEMS_BSPOPTS_SET_DATA_CACHE_ENABLED([mpc5566evb],[1])
     28RTEMS_BSPOPTS_SET_DATA_CACHE_ENABLED([mpc5674fevb],[1])
    2829RTEMS_BSPOPTS_SET_DATA_CACHE_ENABLED([*],[1])
    2930RTEMS_BSPOPTS_HELP_DATA_CACHE_ENABLED
     
    3132RTEMS_BSPOPTS_SET_INSTRUCTION_CACHE_ENABLED([gwlcfm],[])
    3233RTEMS_BSPOPTS_SET_INSTRUCTION_CACHE_ENABLED([mpc5566evb],[1])
     34RTEMS_BSPOPTS_SET_INSTRUCTION_CACHE_ENABLED([mpc5674fevb],[1])
    3335RTEMS_BSPOPTS_SET_INSTRUCTION_CACHE_ENABLED([*],[1])
    3436RTEMS_BSPOPTS_HELP_INSTRUCTION_CACHE_ENABLED
    3537
    36 RTEMS_BSPOPTS_SET([UARTS_USE_TERMIOS],[*],[])
    37 RTEMS_BSPOPTS_HELP([UARTS_USE_TERMIOS],
    38 [Define to 1 if you want termios support for every port.
    39  Termios support is independent of the choice of UART I/O mode.])
     38RTEMS_BSPOPTS_SET([MPC55XX_ESCI_CONSOLE_MINOR],[*],[0])
     39RTEMS_BSPOPTS_HELP([MPC55XX_ESCI_CONSOLE_MINOR],
     40[determines which eSCI device will be registered as /dev/console])
    4041
    41 RTEMS_BSPOPTS_SET([CONSOLE_MINOR],[gwlcfm],[MPC55XX_ESCI_A_MINOR])
    42 RTEMS_BSPOPTS_SET([CONSOLE_MINOR],[*]     ,[MPC55XX_ESCI_A_MINOR])
    43 RTEMS_BSPOPTS_HELP([CONSOLE_MINOR],
    44 [Must be defined to be one of MPC55XX_ESCI_A_MINOR or MPC55XX_ESCI_B_MINOR.  Determines which
    45  device will be registered as /dev/console.])
    46 
    47 RTEMS_BSPOPTS_SET([UARTS_IO_MODE],[gwlcfm],[1])
    48 RTEMS_BSPOPTS_SET([UARTS_IO_MODE],[*]     ,[])
    49 RTEMS_BSPOPTS_HELP([UARTS_IO_MODE],
    50 [Define to 1 if you want interrupt-driven I/O for the SCI ports.])
    51 
    52 RTEMS_BSPOPTS_SET([PRINTK_MINOR],[gwlcfm],[MPC55XX_ESCI_A_MINOR])
    53 RTEMS_BSPOPTS_SET([PRINTK_MINOR],[phytec_mpc5554],[MPC55XX_ESCI_A_MINOR])
    54 RTEMS_BSPOPTS_SET([PRINTK_MINOR],[*]     ,[MPC55XX_ESCI_B_MINOR])
    55 RTEMS_BSPOPTS_HELP([PRINTK_MINOR],
    56 [Must be defined to be one of MPC55XX_ESCI_A_MINOR or MPC55XX_ESCI_B_MINOR.  Determines which
    57  device is used for output by printk().  The printk port always uses polled
    58  I/O.  Don't open the printk port from RTEMS unless also using polled I/O
    59  for the SCI ports.])
     42RTEMS_BSPOPTS_SET([MPC55XX_ESCI_USE_INTERRUPTS],[*],[1])
     43RTEMS_BSPOPTS_HELP([MPC55XX_ESCI_USE_INTERRUPTS],
     44[define to zero or one to disable or enable interrupts for the eSCI devices])
    6045
    6146RTEMS_BSPOPTS_SET([MPC55XX_FMPLL_REF_CLOCK],[gwlcfm],[40000000])
     47RTEMS_BSPOPTS_SET([MPC55XX_FMPLL_REF_CLOCK],[mpc5674fevb],[40000000])
    6248RTEMS_BSPOPTS_SET([MPC55XX_FMPLL_REF_CLOCK],[*]     ,[8000000])
    6349RTEMS_BSPOPTS_HELP([MPC55XX_FMPLL_REF_CLOCK],
     
    6652
    6753RTEMS_BSPOPTS_SET([MPC55XX_FMPLL_CLK_OUT],[gwlcfm],[66000000])
     54RTEMS_BSPOPTS_SET([MPC55XX_FMPLL_CLK_OUT],[mpc5674fevb],[264000000])
    6855RTEMS_BSPOPTS_SET([MPC55XX_FMPLL_CLK_OUT],[*]     ,[128000000])
    6956RTEMS_BSPOPTS_HELP([MPC55XX_FMPLL_CLK_OUT],
     
    7158
    7259RTEMS_BSPOPTS_SET([MPC55XX_FMPLL_PREDIV],[gwlcfm],[10])
     60RTEMS_BSPOPTS_SET([MPC55XX_FMPLL_PREDIV],[mpc5674fevb],[5])
    7361RTEMS_BSPOPTS_SET([MPC55XX_FMPLL_PREDIV],[*]     ,[1])
    7462RTEMS_BSPOPTS_HELP([MPC55XX_FMPLL_PREDIV],
     
    7664
    7765RTEMS_BSPOPTS_SET([MPC55XX_FMPLL_MFD],[gwlcfm],[99])
     66RTEMS_BSPOPTS_SET([MPC55XX_FMPLL_MFD],[mpc5674fevb],[66])
    7867RTEMS_BSPOPTS_SET([MPC55XX_FMPLL_MFD],[*]     ,[12])
    7968RTEMS_BSPOPTS_HELP([MPC55XX_FMPLL_MFD],
     
    9887 The default is the last channel.])
    9988
     89RTEMS_BSPOPTS_SET([MPC55XX_CHIP_TYPE],[mpc5674fevb],[5674])
    10090RTEMS_BSPOPTS_SET([MPC55XX_CHIP_TYPE],[mpc5566evb],[5566])
    10191RTEMS_BSPOPTS_SET([MPC55XX_CHIP_TYPE],[gwlcfm]    ,[5516])
     
    10494[specifies the chip type in use (e.g. 5554 for MPC5554)])
    10595
     96RTEMS_BSPOPTS_SET([MPC55XX_BOOTFLAGS],[*],[])
    10697RTEMS_BSPOPTS_HELP([MPC55XX_BOOTFLAGS],
    107 [If defined, builds in bootflags above the RCHW for setup in a debugger to avoid startup MMU setup])
     98[if defined, builds in bootflags above the RCHW for setup in a debugger to avoid startup MMU setup])
    10899
    109 RTEMS_BSPOPTS_SET([BOARD_GWLCFM],[gwlcfm],[1])
    110 RTEMS_BSPOPTS_HELP([BOARD_GWLCFM],
    111 [If defined, use custom settings of for the GW_LCFM board])
     100RTEMS_BSPOPTS_SET([MPC55XX_BOARD_MPC5674FEVB],[mpc5674fevb],[1])
     101RTEMS_BSPOPTS_HELP([MPC55XX_BOARD_MPC5674FEVB],[if defined, use custom settings for MPC5674FEVB board])
     102
     103RTEMS_BSPOPTS_SET([MPC55XX_BOARD_MPC5566EVB],[mpc5566evb],[1])
     104RTEMS_BSPOPTS_HELP([MPC55XX_BOARD_MPC5566EVB],[if defined, use custom settings for MPC5566EVB board])
     105
     106RTEMS_BSPOPTS_SET([MPC55XX_BOARD_GWLCFM],[gwlcfm],[1])
     107RTEMS_BSPOPTS_HELP([MPC55XX_BOARD_GWLCFM],[if defined, use custom settings for GWLCFM board])
     108
     109RTEMS_BSPOPTS_SET([MPC55XX_BOARD_PHYCORE_MPC5554],[phycore_mpc5554],[1])
     110RTEMS_BSPOPTS_HELP([MPC55XX_BOARD_PHYCORE_MPC5554],[if defined, use custom settings for phyCORE MPC5554 board])
    112111
    113112RTEMS_BSPOPTS_SET([RTEMS_BSP_I2C_EEPROM_DEVICE_NAME],[gwlcfm],['"eeprom"'])
  • c/src/lib/libbsp/powerpc/mpc55xxevb/i2c/i2c_init.c

    rf23c9ed r9e7758b  
    2424#include <bsp/mpc83xx_i2cdrv.h>
    2525
    26 #ifdef MPC55XX_IRQ_I2C
     26#if MPC55XX_CHIP_TYPE / 10 == 551
    2727  static mpc83xx_i2c_desc_t mpc55xx_i2c_bus = {
    2828    .bus_desc = {
     
    3333      .reg_ptr = (m83xxI2CRegisters_t *) 0xfff88000,
    3434      .initialized = FALSE,
    35       .irq_number = MPC55XX_IRQ_I2C,
     35      .irq_number = MPC55XX_IRQ_I2C(0),
    3636      .base_frq = 0
    3737    }
     
    4242    int rv = 0;
    4343    int busno = 0;
    44  
     44
    4545    rtems_libi2c_initialize ();
    46  
     46
    4747    mpc55xx_i2c_bus.softc.base_frq = bsp_clock_speed;
    4848    busno = rtems_libi2c_register_bus(
     
    6565      }
    6666    #endif
    67  
     67
    6868    return RTEMS_SUCCESSFUL;
    6969  }
  • c/src/lib/libbsp/powerpc/mpc55xxevb/include/bsp.h

    rf23c9ed r9e7758b  
    88
    99/*
    10  * Copyright (c) 2008
    11  * Embedded Brains GmbH
    12  * Obere Lagerstr. 30
    13  * D-82178 Puchheim
    14  * Germany
    15  * rtems@embedded-brains.de
     10 * Copyright (c) 2008-2011 embedded brains GmbH.  All rights reserved.
    1611 *
    17  * The license and distribution terms for this file may be found in the file
    18  * LICENSE in this distribution or at http://www.rtems.com/license/LICENSE.
     12 *  embedded brains GmbH
     13 *  Obere Lagerstr. 30
     14 *  82178 Puchheim
     15 *  Germany
     16 *  <rtems@embedded-brains.de>
     17 *
     18 * The license and distribution terms for this file may be
     19 * found in the file LICENSE in this distribution or at
     20 * http://www.rtems.com/license/LICENSE.
     21 *
     22 * $Id$
    1923 */
    2024
     
    3741
    3842#define BSP_SMALL_MEMORY 1
     43
     44#define BSP_INTERRUPT_STACK_AT_WORK_AREA_BEGIN
    3945
    4046#define BSP_FEATURE_IRQ_EXTENSION
  • c/src/lib/libbsp/powerpc/mpc55xxevb/network/if_smc.c

    rf23c9ed r9e7758b  
    22 *  $Id$
    33 */
     4
     5#include <bsp.h>
     6
     7#ifdef HAS_SMC91111M
    48
    59#include <mpc55xx/mpc55xx.h>
     
    711
    812#include <rtems.h>
    9 
    10 #include <bsp.h>
    1113
    1214#include <bsp/irq.h>
     
    166168    return _rtems_smc91111_driver_attach(config,&mpc5554_scmv91111_configuration);
    167169};
     170
     171#endif /* HAS_SMC91111M */
  • c/src/lib/libbsp/powerpc/mpc55xxevb/network/smsc9218i.c

    rf23c9ed r9e7758b  
    791791  /* Obtain receive eDMA channel */
    792792  e->edma_receive.id = e->receive_task;
    793   sc = mpc55xx_edma_obtain_channel(&e->edma_receive);
     793  sc = mpc55xx_edma_obtain_channel(
     794    &e->edma_receive,
     795    MPC55XX_INTC_DEFAULT_PRIORITY
     796  );
    794797  ASSERT_SC(sc);
    795798
     
    13421345  /* Obtain transmit eDMA channel */
    13431346  e->edma_transmit.id = e->transmit_task;
    1344   sc = mpc55xx_edma_obtain_channel(&e->edma_transmit);
     1347  sc = mpc55xx_edma_obtain_channel(
     1348    &e->edma_transmit,
     1349    MPC55XX_INTC_DEFAULT_PRIORITY
     1350  );
    13451351  ASSERT_SC(sc);
    13461352
     
    14111417  }
    14121418
    1413 cleanup:
    1414 
    14151419  /* Release network semaphore */
    14161420  rtems_bsdnet_semaphore_release();
     
    15241528  pcr.B.OBE = 0;
    15251529  pcr.B.IBE = 1;
     1530#if MPC55XX_CHIP_TYPE / 10 != 551
    15261531  pcr.B.DSC = 0;
     1532#endif
    15271533  pcr.B.ODE = 0;
    15281534  pcr.B.HYS = 0;
     
    15351541  rtems_interrupt_disable(level);
    15361542  dirsr.R = SIU.DIRSR.R;
     1543#if MPC55XX_CHIP_TYPE / 10 != 551
    15371544  dirsr.B.DIRS0 = 0;
     1545#endif
    15381546  SIU.DIRSR.R = dirsr.R;
    15391547  rtems_interrupt_enable(level);
     
    16081616  pcr.B.OBE = 1;
    16091617  pcr.B.IBE = 0;
     1618#if MPC55XX_CHIP_TYPE / 10 != 551
    16101619  pcr.B.DSC = 0;
     1620#endif
    16111621  pcr.B.ODE = 0;
    16121622  pcr.B.HYS = 0;
  • c/src/lib/libbsp/powerpc/mpc55xxevb/preinstall.am

    rf23c9ed r9e7758b  
    5454TMPINSTALL_FILES += $(PROJECT_LIB)/linkcmds
    5555
     56$(PROJECT_LIB)/linkcmds.base: ../shared/startup/linkcmds.base $(PROJECT_LIB)/$(dirstamp)
     57        $(INSTALL_DATA) $< $(PROJECT_LIB)/linkcmds.base
     58PREINSTALL_FILES += $(PROJECT_LIB)/linkcmds.base
     59
    5660$(PROJECT_LIB)/linkcmds.gwlcfm: startup/linkcmds.gwlcfm $(PROJECT_LIB)/$(dirstamp)
    5761        $(INSTALL_DATA) $< $(PROJECT_LIB)/linkcmds.gwlcfm
    5862PREINSTALL_FILES += $(PROJECT_LIB)/linkcmds.gwlcfm
    59 
    60 $(PROJECT_LIB)/linkcmds.phycore_mpc5554: startup/linkcmds.phycore_mpc5554 $(PROJECT_LIB)/$(dirstamp)
    61         $(INSTALL_DATA) $< $(PROJECT_LIB)/linkcmds.phycore_mpc5554
    62 PREINSTALL_FILES += $(PROJECT_LIB)/linkcmds.phycore_mpc5554
    6363
    6464$(PROJECT_LIB)/linkcmds.mpc5566evb: startup/linkcmds.mpc5566evb $(PROJECT_LIB)/$(dirstamp)
     
    6666PREINSTALL_FILES += $(PROJECT_LIB)/linkcmds.mpc5566evb
    6767
    68 $(PROJECT_LIB)/linkcmds.base: startup/linkcmds.base $(PROJECT_LIB)/$(dirstamp)
    69         $(INSTALL_DATA) $< $(PROJECT_LIB)/linkcmds.base
    70 PREINSTALL_FILES += $(PROJECT_LIB)/linkcmds.base
     68$(PROJECT_LIB)/linkcmds.mpc5674fevb: startup/linkcmds.mpc5674fevb $(PROJECT_LIB)/$(dirstamp)
     69        $(INSTALL_DATA) $< $(PROJECT_LIB)/linkcmds.mpc5674fevb
     70PREINSTALL_FILES += $(PROJECT_LIB)/linkcmds.mpc5674fevb
     71
     72$(PROJECT_LIB)/linkcmds.phycore_mpc5554: startup/linkcmds.phycore_mpc5554 $(PROJECT_LIB)/$(dirstamp)
     73        $(INSTALL_DATA) $< $(PROJECT_LIB)/linkcmds.phycore_mpc5554
     74PREINSTALL_FILES += $(PROJECT_LIB)/linkcmds.phycore_mpc5554
    7175
    7276$(PROJECT_INCLUDE)/bsp.h: include/bsp.h $(PROJECT_INCLUDE)/$(dirstamp)
     
    98102PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/smsc9218i.h
    99103
     104$(PROJECT_INCLUDE)/bsp/mpc55xx-config.h: include/mpc55xx-config.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
     105        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/mpc55xx-config.h
     106PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/mpc55xx-config.h
     107
    100108$(PROJECT_INCLUDE)/bsp/mpc83xx_i2cdrv.h: ../../../libcpu/powerpc/mpc83xx/i2c/mpc83xx_i2cdrv.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
    101109        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/mpc83xx_i2cdrv.h
     
    114122PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/utility.h
    115123
     124$(PROJECT_INCLUDE)/bsp/linker-symbols.h: ../shared/include/linker-symbols.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
     125        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/linker-symbols.h
     126PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/linker-symbols.h
     127
    116128$(PROJECT_INCLUDE)/bsp/start.h: ../shared/include/start.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
    117129        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/start.h
  • c/src/lib/libbsp/powerpc/mpc55xxevb/startup/bspstart.c

    rf23c9ed r9e7758b  
    88
    99/*
    10  * Copyright (c) 2008
    11  * Embedded Brains GmbH
    12  * Obere Lagerstr. 30
    13  * D-82178 Puchheim
    14  * Germany
    15  * rtems@embedded-brains.de
     10 * Copyright (c) 2008-2011 embedded brains GmbH.  All rights reserved.
    1611 *
    17  * The license and distribution terms for this file may be found in the file
    18  * LICENSE in this distribution or at http://www.rtems.com/license/LICENSE.
     12 *  embedded brains GmbH
     13 *  Obere Lagerstr. 30
     14 *  82178 Puchheim
     15 *  Germany
     16 *  <rtems@embedded-brains.de>
     17 *
     18 * The license and distribution terms for this file may be
     19 * found in the file LICENSE in this distribution or at
     20 * http://www.rtems.com/license/LICENSE.
     21 *
     22 * $Id$
    1923 */
    2024
     
    2327#include <mpc55xx/edma.h>
    2428#include <mpc55xx/emios.h>
    25 #include <mpc55xx/siu.h>
     29
     30#include <string.h>
    2631
    2732#include <rtems.h>
     33#include <rtems/config.h>
    2834
    2935#include <libcpu/powerpc-utility.h>
     
    3440#include <bsp/irq.h>
    3541#include <bsp/irq-generic.h>
    36 
    37 #define RTEMS_STATUS_CHECKS_USE_PRINTK
    38 
    39 #include <rtems/status-checks.h>
    40 
    41 #define DEBUG_DONE() RTEMS_DEBUG_PRINT( "Done\n")
    42 
    43 #define MPC55XX_INTERRUPT_STACK_SIZE 0x1000
     42#include <bsp/linker-symbols.h>
     43#include <bsp/start.h>
     44#include <bsp/mpc55xx-config.h>
    4445
    4546/* Symbols defined in linker command file */
     
    4849LINKER_SYMBOL(bsp_external_ram_start);
    4950LINKER_SYMBOL(bsp_external_ram_size);
    50 LINKER_SYMBOL(bsp_section_bss_end);
     51LINKER_SYMBOL(mpc55xx_exc_vector_base);
    5152
    5253unsigned int bsp_clock_speed = 0;
     
    8081}
    8182
    82 void bsp_predriver_hook()
     83static void null_pointer_protection(void)
    8384{
    84         rtems_status_code sc = RTEMS_SUCCESSFUL;
     85#if defined(MPC55XX_BOARD_MPC5674FEVB) || defined(MPC55XX_BOARD_MPC5566EVB)
     86        struct MMU_tag mmu = { .MAS0 = { .B = { .TLBSEL = 1, .ESEL = 1 } } };
    8587
    86         RTEMS_DEBUG_PRINT( "Initialize eDMA ...\n");
    87         sc = mpc55xx_edma_init();
    88         if (sc != RTEMS_SUCCESSFUL) {
    89                 BSP_panic( "Cannot initialize eDMA");
    90         } else {
    91                 DEBUG_DONE();
    92         }
     88        PPC_SET_SPECIAL_PURPOSE_REGISTER(FSL_EIS_MAS0, mmu.MAS0.R);
     89        __asm__ volatile ("tlbre");
     90        mmu.MAS1.R = PPC_SPECIAL_PURPOSE_REGISTER(FSL_EIS_MAS1);
     91        mmu.MAS1.B.VALID = 0;
     92        PPC_SET_SPECIAL_PURPOSE_REGISTER(FSL_EIS_MAS1, mmu.MAS1.R);
     93        __asm__ volatile ("tlbwe");
     94#endif
    9395}
    94 
    95 #if ((MPC55XX_CHIP_TYPE>=5510) && (MPC55XX_CHIP_TYPE<=5517))
    96 /*
    97  * define init values for FMPLL ESYNCRx
    98  * (used in start.S/fmpll.S)
    99  */
    100 #define EPREDIV_VAL (MPC55XX_FMPLL_PREDIV-1)
    101 #define EMFD_VAL    (MPC55XX_FMPLL_MFD-16)
    102 #define VCO_CLK_REF (MPC55XX_FMPLL_REF_CLOCK/(EPREDIV_VAL+1))
    103 #define VCO_CLK_OUT (VCO_CLK_REF*(EMFD_VAL+16))
    104 #define ERFD_VAL    ((VCO_CLK_OUT/MPC55XX_FMPLL_CLK_OUT)-1)
    105 
    106 const struct fmpll_syncr_vals_t {
    107   union ESYNCR2_tag esyncr2_temp;
    108   union ESYNCR2_tag esyncr2_final;
    109   union ESYNCR1_tag esyncr1_final;
    110 } fmpll_syncr_vals =
    111   {
    112     { /* esyncr2_temp */
    113       .B.LOCEN=0,
    114       .B.LOLRE=0,
    115       .B.LOCRE=0,
    116       .B.LOLIRQ=0,
    117       .B.LOCIRQ=0,
    118       .B.ERATE=0,
    119       .B.DEPTH=0,
    120       .B.ERFD=ERFD_VAL+2 /* reduce output clock during init */
    121     },
    122     { /* esyncr2_final */
    123       .B.LOCEN=0,
    124       .B.LOLRE=0,
    125       .B.LOCRE=0,
    126       .B.LOLIRQ=0,
    127       .B.LOCIRQ=0,
    128       .B.ERATE=0,
    129       .B.DEPTH=0,
    130       .B.ERFD=ERFD_VAL /* nominal output clock after init */
    131     },
    132     { /* esyncr1_final */
    133       .B.CLKCFG=7,
    134       .B.EPREDIV=EPREDIV_VAL,
    135       .B.EMFD=EMFD_VAL
    136     }
    137   };
    138 
    139 #else /* ((MPC55XX_CHIP_TYPE>=5510) && (MPC55XX_CHIP_TYPE<=5517)) */
    140 
    141 const struct fmpll_syncr_vals_t {
    142   union SYNCR_tag syncr_temp;
    143   union SYNCR_tag syncr_final;
    144 } fmpll_syncr_vals =
    145   {
    146     { /* syncr_temp */
    147       .B.PREDIV=MPC55XX_FMPLL_PREDIV-1,
    148       .B.MFD=MPC55XX_FMPLL_MFD,
    149       .B.RFD=2,
    150       .B.LOCEN=1
    151     },
    152     { /* syncr_final */
    153       .B.PREDIV=MPC55XX_FMPLL_PREDIV-1,
    154       .B.MFD=MPC55XX_FMPLL_MFD,
    155       .B.RFD=0,
    156       .B.LOCEN=1
    157     }
    158   };
    159 
    160 #endif /* ((MPC55XX_CHIP_TYPE>=5510) && (MPC55XX_CHIP_TYPE<=5517)) */
    161 
    162 #if defined(BOARD_GWLCFM)
    163 static const mpc55xx_siu_pcr_entry_t siu_pcr_list[] = {
    164   {  0,16,{.B.PA = 1,           .B.WPE = 0}}, /* PA[ 0..15] analog input */
    165   { 16, 4,{.B.PA = 0,.B.OBE = 1,.B.WPE = 0}}, /* PB[ 0.. 4] LED/CAN_STBN out */
    166   { 20, 2,{.B.PA = 0,.B.IBE = 1,.B.WPE = 0}}, /* PB[ 5.. 6] CAN_ERR/USBFLGC in*/
    167   { 22, 1,{.B.PA = 0,.B.OBE = 1,.B.WPE = 0}}, /* PB[ 7    ] FR_A_EN out */
    168   { 23, 4,{.B.PA = 0,.B.IBE = 1,.B.WPE = 0}}, /* PB[ 8..10] IRQ/FR_A_ERR/USB_RDYin */
    169   { 27, 1,{.B.PA = 0,.B.OBE = 1,.B.WPE = 0}}, /* PB[11..11] FR_STBN out */
    170 
    171   { 32, 2,{.B.PA = 2,.B.OBE = 1,.B.WPE = 0}}, /* PC[ 0.. 1] FR_A_TX/TXEN out */
    172   { 34, 1,{.B.PA = 2,.B.IBE = 1,.B.WPE = 0}}, /* PC[ 2.. 2] FR_A_RX in */
    173   { 35, 2,{.B.PA = 0,.B.IBE = 1,.B.WPE = 0}}, /* PC[ 3.. 4] INIT_ERR/ISB_IRQ in */
    174   { 37, 2,{.B.PA = 0,.B.OBE = 1,.B.WPE = 0}}, /* PC[ 5.. 6] PWRO1/2_ON out */
    175   { 39, 1,{.B.PA = 2,.B.IBE = 1,.B.WPE = 0}}, /* PC[ 7.. 7] FR_B_RX in */
    176   { 40, 2,{.B.PA = 2,.B.OBE = 1,.B.WPE = 0}}, /* PC[ 8.. 9] FR_B_TX/TXEN out */
    177   { 42, 1,{.B.PA = 0,.B.OBE = 1,.B.WPE = 0}}, /* PC[10    ] FR_B_EN out */
    178   { 43, 1,{.B.PA = 0,.B.IBE = 1,.B.WPE = 0}}, /* PC[11    ] FOR_STATUS in */
    179   { 44, 1,{.B.PA = 0,.B.IBE = 1,.B.WPE = 0}}, /* PC[12    ] FR_B_ERRN  in */
    180   { 45, 1,{.B.PA = 0,.B.OBE = 1,.B.WPE = 0}}, /* PC[13    ] HS_CAN_STBN out */
    181   { 46, 1,{.B.PA = 0,.B.IBE = 1,.B.WPE = 0}}, /* PC[14    ] HS_CAN_ERR in */
    182   { 47, 1,{.B.PA = 0,.B.OBE = 1,.B.WPE = 0}}, /* PC[15    ] HS_CAN_EN out */
    183 
    184   { 48, 1,{.B.PA = 1,.B.OBE = 1,.B.WPE = 0}}, /* PD[ 0    ] HS_CAN_TX out */
    185   { 49, 1,{.B.PA = 1,.B.IBE = 1,.B.WPE = 0}}, /* PD[ 1    ] HS_CAN_RX in  */
    186   { 50, 2,{.B.PA = 0,.B.IBE = 1,.B.WPE = 0}}, /* PD[ 2.. 3] PWRO1/2_OC in */
    187   { 52, 1,{.B.PA = 1,.B.OBE = 1,.B.WPE = 0}}, /* PD[ 4    ] LS_CAN_TX out */
    188   { 53, 1,{.B.PA = 1,.B.IBE = 1,.B.WPE = 0}}, /* PD[ 5    ] LS_CAN_RX in  */
    189   { 54, 1,{.B.PA = 1,.B.OBE = 1,.B.WPE = 0}}, /* PD[ 6    ] HS_CAN_TX out */
    190   { 55, 1,{.B.PA = 1,.B.IBE = 1,.B.WPE = 0}}, /* PD[ 7    ] HS_CAN_RX in  */
    191   { 56, 1,{.B.PA = 2,.B.IBE = 1,.B.OBE = 1,.B.WPE = 0}},
    192   /* PD[ 8    ] I2C_SCL in/out */
    193   { 57, 1,{.B.PA = 2,.B.IBE = 1,.B.OBE = 1,.B.WPE = 0}},
    194   /* PD[ 9    ] I2C_SDA in/out */
    195  
    196   { 58, 1,{.B.PA = 0,.B.OBE = 1,.B.WPE = 0}}, /* PD[10] LS_CAN_EN     out*/
    197   { 59, 3,{.B.PA = 0,.B.IBE = 1,.B.WPE = 0}},
    198   /* PD[11..13] PWO1_OC, MOCO_INT in */
    199  
    200   { 62, 4,{.B.PA = 0,.B.IBE = 1,.B.WPE = 0}}, /* PD[14..15] USB_FLGA/B    in */
    201 
    202   { 64, 5,{.B.PA = 0,.B.OBE = 1,.B.WPE = 0}}, /* PE[ 0.. 4] LED_EXT1-5.   out*/
    203   { 70, 1,{.B.PA = 1,.B.SRC = 3,.B.WPE = 0}}, /* PE[ 6.. 6] CLKOUT        out*/
    204 
    205   { 80, 1,{.B.PA = 1,.B.SRC = 1,.B.WPE = 0}}, /* PF[ 0.. 0] RD_WR         out*/
    206   { 81, 1,{.B.PA = 0,.B.SRC = 0,.B.WPE = 0}}, /* PF[ 1.. 1] (nc)          in */
    207   { 82, 8,{.B.PA = 2,.B.SRC = 1,.B.WPE = 0}}, /* PF[ 2..11] ADDR[8..15]   out*/
    208   { 90, 2,{.B.PA = 1,.B.SRC = 1,.B.WPE = 0}}, /* PF[ 2..11] CS[0..1]      out*/
    209   { 92, 1,{.B.PA = 3,.B.SRC = 3,.B.WPE = 0}}, /* PF[    12] ALE           out*/
    210   { 93, 3,{.B.PA = 1,.B.SRC = 1,.B.WPE = 0}}, /* PF[13..15] OE/WE         out*/
    211 
    212   { 96,16,{.B.PA = 1,.B.SRC = 1,.B.WPE = 0}}, /* PG[ 0..15] AD16..31   in/out*/
    213 
    214   {113, 1,{.B.PA = 0,.B.OBE = 1,.B.WPE = 0}}, /* PH[ 1.. 1] RES_MOSTComp  out*/
    215   {114, 1,{.B.PA = 3,.B.OBE = 1,.B.WPE = 0}}, /* PH[ 2.. 2] CS3_MOSTComp  out*/
    216   {115, 1,{.B.PA = 3,.B.OBE = 1,.B.WPE = 0}}, /* PH[ 3.. 3] CS2_ETH       out*/
    217   {116, 2,{.B.PA = 0,.B.OBE = 1,.B.WPE = 0}}, /* PH[ 4.. 5] FR/HC_TERM    out*/
    218   {118, 1,{.B.PA = 2,.B.OBE = 1,.B.WPE = 0}}, /* PH[ 6.. 6] LIN_Tx        out*/
    219   {119, 1,{.B.PA = 2,.B.IBE = 1,.B.WPE = 0}}, /* PH[ 7.. 7] LIN_Rx        in */
    220   {120, 4,{.B.PA = 0,.B.OBE = 1,.B.WPE = 0}}, /* PH[ 8..11] LIN_SLP,RST   out*/
    221 
    222   {0,0}
    223 };
    224 #elif defined(BOARD_PHYCORE_MPC5554)
    225 
    226 static const mpc55xx_siu_pcr_entry_t siu_pcr_list[] = {
    227   {  0, 4,{.B.PA = 1,          .B.DSC = 1,.B.WPE=1,.B.WPS=1}}, /* !CS  [0:3]    */
    228   {  4,24,{.B.PA = 1,          .B.DSC = 1                  }}, /* ADDR [8 : 31] */
    229   { 28,32,{.B.PA = 1,          .B.DSC = 1                  }}, /* DATA [0 : 31] */
    230   { 60, 4,{.B.PA = 1,          .B.DSC = 1,                 }}, /* TSIZ[0:1], RD_!WR, BDIP */
    231   { 64, 6,{.B.PA = 1,          .B.DSC = 1,.B.WPE=1,.B.WPS=1}}, /* RD_!WR, BDIP, !WE, !OE, !TS */
    232   { 89, 4,{.B.PA = 1                                       }}, /* ESCI_A and ESCI_B        */
    233   {229, 4,{          .B.OBE= 1,.B.DSC = 1                  }}, /* CLKOUT */
    234 
    235   {0,0}
    236 };
    237 
    238 #else /* MPC55xxEVB */
    239 
    240 static const mpc55xx_siu_pcr_entry_t siu_pcr_list[] = {
    241   {  0, 1,{.B.PA = 1,.B.DSC = 1,.B.WPE=1,.B.WPS=1}}, /* !CS  [0]      */
    242   {  3, 1,{.B.PA = 1,.B.DSC = 1,.B.WPE=1,.B.WPS=1}}, /* !CS  [3]      */
    243   {  4,24,{.B.PA = 1,.B.DSC = 1                  }}, /* ADDR [8 : 31] */
    244   { 28,16,{.B.PA = 1,.B.DSC = 1                  }}, /* DATA [0 : 15] */
    245   { 62, 8,{.B.PA = 1,.B.DSC = 1,.B.WPE=1,.B.WPS=1}}, /* RD_!WR, BDIP,
    246                                                         !WE, !OE, !TS */
    247   { 89, 2,{.B.PA = 1                             }}, /* ESCI_B        */
    248 
    249   {0,0}
    250 };
    251 #endif /* BOARD_GWLCFM */
    252 
    253 /*
    254  * Arrays for setting up the chip selects.
    255  * You can define up to four, and those with the valid bit
    256  * set will be loaded into the matching chip select.
    257  */
    258 static const struct EBI_CS_tag cs_setup[] = {
    259 #if defined(BOARD_GWLCFM)
    260         /* CS0: External SRAM (16 bit, 1 wait states, 512kB, no burst) */
    261         {
    262         {
    263             .B.BA = 0x20000000>>15,
    264             .B.PS = 1,
    265             .B.AD_MUX = 1,
    266             .B.WEBS = 1,
    267             .B.TBDIP = 0,
    268             .B.BI = 1,
    269             .B.V = 1
    270         },
    271         {
    272             .B.AM = 0x1fff0,
    273             .B.SCY = 1,
    274             .B.BSCY = 0
    275         }
    276     },
    277         /* CS1: External USB controller (16 bit, 3 wait states, 32kB, no burst) */
    278         {
    279         {
    280             .B.BA = 0x22000000>>15,
    281             .B.PS = 1,
    282             .B.AD_MUX = 1,
    283             .B.WEBS = 0,
    284             .B.TBDIP = 0,
    285             .B.BI = 1,
    286             .B.V = 1
    287         },
    288         {
    289             .B.AM = 0x1ffff,
    290             .B.SCY = 3,
    291             .B.BSCY = 0
    292         }
    293     },
    294         /* CS2: Ethernet (16 bit, 2 wait states, 32kB, no burst) */
    295         {
    296         {
    297             .B.BA = 0x22800000>>15,
    298             .B.PS = 1,
    299             .B.AD_MUX = 1,
    300             .B.WEBS = 1,
    301             .B.TBDIP = 0,
    302             .B.BI = 1,
    303             .B.V = 1
    304         },
    305         {
    306             .B.AM = 0x1ffff,
    307             .B.SCY = 1,
    308             .B.BSCY = 0
    309         }
    310     },
    311     {                           /* CS3: MOST Companion. */
    312         {
    313             .B.BA = 0x23000000>>15,
    314             .B.PS = 1,
    315             .B.AD_MUX = 1,
    316             .B.WEBS = 0,
    317             .B.TBDIP = 0,
    318             .B.BI = 1,
    319             .B.V = 1
    320         },
    321 
    322         {
    323             .B.AM = 0x1fff0,
    324             .B.SCY = 1,
    325             .B.BSCY = 0
    326         }
    327     }
    328 #elif defined(BOARD_PHYCORE_MPC5554)
    329     /* CS0: External flash. */
    330     {
    331         { .R = 0x20000003 },   /* Base 0x2000000, Burst Inhibit, Valid */
    332         { .R = 0xff000050 }
    333     },
    334     /* CS1: External synchronous burst mode SRAM. */
    335     {
    336         { .R = 0x21000051 },   /* Base 0x2100000, 4-word Burst Enabled, Valid */
    337         { .R = 0xff000000 }    /* No wait states. */
    338     },
    339     /* CS2: External LAN91C111 */
    340     {
    341         { .R = 0x22000003 },   /* Base 0x22000000, Burst inhibit, valid */
    342         { .R = 0xff000010 }
    343     },
    344 
    345     /* CS3: External FPGA */
    346     {
    347         { .R = 0x23000003 },   /* Base 0x23000000, Burst inhibit, valid. */
    348         { .R = 0xff000020 }
    349     }
    350 #else /* default, MPC55xxEVB */
    351         /* CS0: External SRAM (2 wait states, 512kB, 4 word burst) */
    352     {
    353         {
    354             .B.BA = 0,
    355             .B.PS = 1,
    356             .B.BL = 1,
    357             .B.WEBS = 0,
    358             .B.TBDIP = 0,
    359             .B.BI = 1, /* TODO: Enable burst */
    360             .B.V = 1
    361         },
    362 
    363         {
    364             .B.AM = 0x1fff0,
    365             .B.SCY = 0,
    366             .B.BSCY = 0
    367         }
    368     },
    369     { { .R = 0 }, { .R = 0 } },   /* CS1: Unused. */
    370     { { .R = 0 }, { .R = 0 } },   /* CS2: Unused. */
    371     {   /* CS3: ethernet? */
    372         {
    373             .B.BA = 0x7fff,
    374             .B.PS = 1,
    375             .B.BL = 0,
    376             .B.WEBS = 0,
    377             .B.TBDIP = 0,
    378             .B.BI = 1,
    379             .B.V = 1
    380         },
    381 
    382         {
    383             .B.AM = 0x1ffff,
    384             .B.SCY = 1,
    385             .B.BSCY = 0
    386         }
    387     }
    388 #endif /* Chip select setup */
    389 };
    390 
    391 /*
    392  * Arrays for setting up the MAS registers.
    393  * You can set as many as you want,we determine the size using sizeof.
    394  */
    395 static const struct MMU_tag mmu_setup[] = {
    396 #if defined(BOARD_GWLCFM)
    397     {
    398         /* External Ethernet Controller (3 wait states, 64kB) */
    399 
    400         {
    401             .B.TLBSEL = 1,      /* MAS0 */
    402             .B.ESEL = 5
    403         },
    404         {
    405             .B.VALID = 1,       /* MAS1 */
    406             .B.IPROT = 1,
    407             .B.TSIZ = 1
    408         },
    409         {
    410             .B.EPN = 0x3fff8,   /* MAS2 */
    411             .B.I = 1,
    412             .B.G = 1
    413         },
    414         {
    415             .B.RPN = 0x3fff8,   /* MAS3 */
    416             .B.UW = 1,
    417             .B.SW = 1,
    418             .B.UR = 1,
    419             .B.SR = 1
    420         }
    421     }
    422 
    423 #elif defined(BOARD_PHYCORE_MPC5554)
    424 
    425     /* XXX I'm not using TLB1 entry 2 the same way as
    426          * in the BAM.
    427      */
    428     /*  Set up MMU TLB1 entry 2 for external ram. */
    429     /*  Effective Base address = 0x2100_0000 XXX NOT LIKE BAM */
    430     /*       Real Base address = 0x2100_0000 XXX NOT LIKE BAM */
    431     /*  Page Size            6 =  4MB XXX Not like BAM */
    432     /*  Not Guarded, Cache Enable, All Access (0, 3F) */
    433     {
    434         { .R = 0x10020000},     /* MAS0 */
    435         { .R = 0xC0000600},     /* MAS1 */
    436         { .R = 0x21000000},     /* MAS2 */
    437         { .R = 0x2100003F}      /* MAS3 */
    438     },
    439 
    440     /*  Set up MMU TLB1 entry 5 for second half of SRAM (debug RAM) */
    441     /*  Effective Base address = 0x2140_0000 */
    442     /*       Real Base address = 0x2140_0000 */
    443     /*  Page Size            6 = 4MB */
    444     /*  Not Guarded, Cache Enable, All Access (0, 3F) */
    445     {
    446         { .R =  0x10050000 },   /* MAS0 */
    447         { .R =  0xC0000600 },   /* MAS1 */
    448         { .R =  0x21400000 },   /* MAS2 */
    449         { .R =  0x2140003F }    /* MAS3 */
    450     },
    451     /*  Set up MMU TLB1 entry 6 for External LAN91C111 */
    452     /*  Effective Base address = 0x2200_0000 */
    453     /*       Real Base address = 0x2200_0000 */
    454     /*  Page Size            7 = 16MB */
    455     /*  Write-through, Guarded, Cache Inhibit, All Access (E, 3F) */
    456     {
    457         { .R = 0x10060000},     /* MAS0 */
    458         { .R = 0xC0000700},     /* MAS1 */
    459         { .R = 0x2200000E},     /* MAS2 */
    460         { .R = 0x2200003F}      /* MAS3 */
    461     },
    462 
    463     /*  Set up MMU TLB1 entry 7 for External FPGA */
    464     /*  Effective Base address = 0x2300_0000 */
    465     /*       Real Base address = 0x2300_0000 */
    466     /*  Page Size            7 = 16MB */
    467     /*  Write-through, Guarded, Cache Inhibit, All Access (E, 3F) */
    468     {
    469         { .R = 0x10070000},     /* MAS0 */
    470         { .R = 0xC0000700},     /* MAS1 */
    471         { .R = 0x2300000E},     /* MAS2 */
    472         { .R = 0x2300003F},     /* MAS3 */
    473     },
    474 
    475         /* Should also set up maps for the debug RAM and the
    476          * external flash.
    477          */
    478 #else /* default, MPC55xxEVB */
    479     {
    480         /* External Ethernet Controller (3 wait states, 64kB) */
    481         .MAS0 = { .R = 0x10050000 },
    482         .MAS1 = { .R = 0xc0000100 },
    483         .MAS2 = { .R = 0x3fff800a },
    484         .MAS3 = { .R = 0x3fff800f }
    485     }
    486 #endif /* MMU setup */
    487 };
    488 
    489 #ifdef MPC55XX_BOOTFLAGS
    490 /* mpc55xx_bootflag_0 is defined in start.S using PUBLIC_VAR().  I go through this
    491  * indirection to avoid a linker issue - if I try to reference
    492  * mpc55xx_bootflag_0 as an "extern uint32_t" I get a linker error.
    493  * Maybe if I declare it as an "extern const uint32_t"?  Anyway, this works.
    494  */
    495 extern void *mpc55xx_bootflag_0(void);
    496 uint32_t *p_mpc55xx_bootflag_0 = (uint32_t *)mpc55xx_bootflag_0;
    497 #endif
    498 
    499 static void mpc55xx_ebi_init(void)
    500 {
    501     int i;
    502        
    503 #if defined(BOARD_GWLCFM)
    504     SIU.GPDO[122].B.PDO=1; /* make sure USB reset is kept high */
    505     SIU.GPDO[121].B.PDO=1; /* make sure Ethernet reset is kept high */
    506     SIU.GPDO[113].B.PDO=1; /* make sure MOST Companion reset is kept high */
    507 #endif /* defined(BOARD_GWLCFM) */
    508         /*
    509          * init I/O pins to proper state
    510          */
    511         mpc55xx_siu_pcr_init(&SIU,
    512                              siu_pcr_list);
    513 
    514     /* Set up chip selects. */
    515     for (i = 0; i < sizeof(cs_setup) / sizeof(cs_setup[0]); i++) {
    516         if (cs_setup[i].BR.B.V) {
    517             EBI.CS [i] = cs_setup[i];
    518         }
    519     }
    520 
    521 #ifdef MPC55XX_BOOTFLAGS
    522     /* If the low bit of bootflag 0 is clear don't change the MMU.
    523      */
    524     if (((*p_mpc55xx_bootflag_0) & 1))
    525 #endif
    526       {
    527         /* Set up MMU. */
    528         for (i = 0; i < sizeof(mmu_setup) / sizeof(mmu_setup[0]); i++) {
    529             PPC_SET_SPECIAL_PURPOSE_REGISTER( FSL_EIS_MAS0, mmu_setup[i].MAS0.R);
    530             PPC_SET_SPECIAL_PURPOSE_REGISTER( FSL_EIS_MAS1, mmu_setup[i].MAS1.R);
    531             PPC_SET_SPECIAL_PURPOSE_REGISTER( FSL_EIS_MAS2, mmu_setup[i].MAS2.R);
    532             PPC_SET_SPECIAL_PURPOSE_REGISTER( FSL_EIS_MAS3, mmu_setup[i].MAS3.R);
    533             __asm__ volatile ("tlbwe");
    534         }
    535       }
    536 
    537 #if defined(BOARD_GWLCFM)
    538         /*
    539          * init EBI for Muxed AD bus
    540          */
    541         EBI.MCR.B.DBM = 1;
    542         EBI.MCR.B.ADMUX = 1; /* use multiplexed bus */
    543         EBI.MCR.B.D16_32 = 1; /* use lower AD bus    */
    544 
    545         SIU.ECCR.B.EBDF = 3;  /* use CLK/4 as bus clock */
    546 
    547 #endif /* defined(BOARD_GWLCFM) */
    548 }
    549 
    550 /**
    551  * @brief Start BSP.
    552  */
    553 LINKER_SYMBOL(bsp_section_bss_start);
    554 LINKER_SYMBOL(bsp_section_bss_end);
    555 LINKER_SYMBOL(bsp_section_sbss_start);
    556 LINKER_SYMBOL(bsp_section_sbss_end);
    557 LINKER_SYMBOL(bsp_section_vector_start);
    55896
    55997void bsp_start(void)
     
    562100        ppc_cpu_id_t myCpu;
    563101        ppc_cpu_revision_t myCpuRevision;
     102#if defined(MPC55XX_BOARD_MPC5674FEVB)
     103        unsigned system_clock_divider = 2;
     104#else
     105        unsigned system_clock_divider = 1;
     106#endif
    564107
    565         uintptr_t interrupt_stack_start = (uintptr_t)bsp_ram_end - 2 * MPC55XX_INTERRUPT_STACK_SIZE;
    566         uint32_t interrupt_stack_size = MPC55XX_INTERRUPT_STACK_SIZE;
    567 
    568 
    569         /* Initialize External Bus Interface */
    570         mpc55xx_ebi_init();
     108        null_pointer_protection();
    571109
    572110        /*
    573111         * make sure BSS/SBSS is cleared
    574112         */
    575         memset(bsp_section_bss_start,0,
    576                bsp_section_bss_end-bsp_section_bss_start);
    577         memset(bsp_section_sbss_start,0,
    578                bsp_section_sbss_end-bsp_section_sbss_start);
    579 
    580         ppc_exc_vector_base = (uint32_t) bsp_section_vector_start;
    581 
    582         RTEMS_DEBUG_PRINT( "BSP start ...\n");
    583 
    584         RTEMS_DEBUG_PRINT( "System clock          : %i\n", mpc55xx_get_system_clock());
    585         RTEMS_DEBUG_PRINT( "Memory start          : 0x%08x\n", bsp_ram_start);
    586         RTEMS_DEBUG_PRINT( "Memory end            : 0x%08x\n", bsp_ram_end);
    587         RTEMS_DEBUG_PRINT( "Memory size           : 0x%08x\n", bsp_ram_end - bsp_ram_start);
    588         RTEMS_DEBUG_PRINT( "Interrupt stack start : 0x%08x\n", interrupt_stack_start);
    589         RTEMS_DEBUG_PRINT( "Interrupt stack end   : 0x%08x\n", interrupt_stack_start + interrupt_stack_size);
    590         RTEMS_DEBUG_PRINT( "Interrupt stack size  : 0x%08x\n", interrupt_stack_size);
     113        memset(&bsp_section_bss_begin [0], 0, (size_t) bsp_section_bss_size);
    591114
    592115        /*
     
    601124         * determine clock speed
    602125         */
    603         bsp_clock_speed = mpc55xx_get_system_clock();
     126        bsp_clock_speed = mpc55xx_get_system_clock() / system_clock_divider;
    604127
    605128        /* Time reference value */
     
    607130
    608131        /* Initialize exceptions */
    609         RTEMS_DEBUG_PRINT( "Initialize exceptions ...\n");
     132        ppc_exc_vector_base = (uint32_t) mpc55xx_exc_vector_base;
    610133        sc = ppc_exc_initialize(
    611134                PPC_INTERRUPT_DISABLE_MASK_DEFAULT,
    612                 interrupt_stack_start,
    613                 interrupt_stack_size
     135                (uintptr_t) bsp_section_work_begin,
     136                Configuration.interrupt_stack_size
    614137        );
    615138        if (sc != RTEMS_SUCCESSFUL) {
    616139                BSP_panic( "Cannot initialize exceptions");
    617         } else {
    618                 DEBUG_DONE();
    619140        }
    620141        ppc_exc_set_handler(ASM_ALIGN_VECTOR, ppc_exc_alignment_handler);
    621142
    622143        /* Initialize interrupts */
    623         RTEMS_DEBUG_PRINT( "Initialize interrupts ...\n");
    624144        sc = bsp_interrupt_initialize();
    625145        if (sc != RTEMS_SUCCESSFUL) {
    626146                BSP_panic( "Cannot initialize interrupts");
    627         } else {
    628                 DEBUG_DONE();
    629147        }
    630148
    631         /* Initialize eMIOS */
    632         mpc55xx_emios_initialize( MPC55XX_EMIOS_PRESCALER);
     149        mpc55xx_edma_init();
     150        mpc55xx_emios_initialize(MPC55XX_EMIOS_PRESCALER);
    633151}
  • c/src/lib/libbsp/powerpc/mpc55xxevb/startup/linkcmds.gwlcfm

    rf23c9ed r9e7758b  
    11MEMORY
    22{
    3         ROM (RX)  : ORIGIN = 0x0, LENGTH = 1536M
     3        ROM (RX)  : ORIGIN = 0x0, LENGTH = 1536K
    44        RAM (AIW) : ORIGIN = 0x40000000, LENGTH = 80K
    55        RAM_EXT   : ORIGIN = 0x20000000, LENGTH = 512K
     
    1919bsp_external_ram_size = LENGTH (RAM_EXT);
    2020
    21 bsp_section_align = 32;
    22 
    23 REGION_ALIAS ("REGION_TEXT",      ROM);
    24 REGION_ALIAS ("REGION_VECTORS",   RAM);
    25 REGION_ALIAS ("REGION_DATA",      RAM);
    26 REGION_ALIAS ("REGION_BSS",       RAM_EXT);
     21REGION_ALIAS ("REGION_START", ROM);
     22REGION_ALIAS ("REGION_FAST_TEXT", RAM);
     23REGION_ALIAS ("REGION_FAST_TEXT_LOAD", ROM);
     24REGION_ALIAS ("REGION_TEXT", ROM);
     25REGION_ALIAS ("REGION_TEXT_LOAD", ROM);
     26REGION_ALIAS ("REGION_RODATA", ROM);
     27REGION_ALIAS ("REGION_RODATA_LOAD", ROM);
     28REGION_ALIAS ("REGION_FAST_DATA", RAM);
     29REGION_ALIAS ("REGION_FAST_DATA_LOAD", ROM);
     30REGION_ALIAS ("REGION_DATA", RAM);
     31REGION_ALIAS ("REGION_DATA_LOAD", ROM);
     32REGION_ALIAS ("REGION_BSS", RAM_EXT);
     33REGION_ALIAS ("REGION_RWEXTRA", RAM_EXT);
     34REGION_ALIAS ("REGION_WORK", RAM_EXT);
     35REGION_ALIAS ("REGION_STACK", RAM_EXT);
    2736
    2837INCLUDE linkcmds.base
    29 
    30 bsp_workspace_start = bsp_section_bss_end;
    31 
  • c/src/lib/libbsp/powerpc/mpc55xxevb/startup/linkcmds.mpc5566evb

    rf23c9ed r9e7758b  
    1919bsp_external_ram_size = LENGTH (RAM_EXT);
    2020
    21 bsp_section_align = 32;
    22 
    23 REGION_ALIAS ("REGION_TEXT",      ROM);
    24 REGION_ALIAS ("REGION_VECTORS",   RAM);
    25 REGION_ALIAS ("REGION_DATA",      RAM);
    26 REGION_ALIAS ("REGION_BSS",       RAM_EXT);
     21REGION_ALIAS ("REGION_START", ROM);
     22REGION_ALIAS ("REGION_FAST_TEXT", RAM);
     23REGION_ALIAS ("REGION_FAST_TEXT_LOAD", ROM);
     24REGION_ALIAS ("REGION_TEXT", ROM);
     25REGION_ALIAS ("REGION_TEXT_LOAD", ROM);
     26REGION_ALIAS ("REGION_RODATA", ROM);
     27REGION_ALIAS ("REGION_RODATA_LOAD", ROM);
     28REGION_ALIAS ("REGION_FAST_DATA", RAM);
     29REGION_ALIAS ("REGION_FAST_DATA_LOAD", ROM);
     30REGION_ALIAS ("REGION_DATA", RAM);
     31REGION_ALIAS ("REGION_DATA_LOAD", ROM);
     32REGION_ALIAS ("REGION_BSS", RAM_EXT);
     33REGION_ALIAS ("REGION_RWEXTRA", RAM_EXT);
     34REGION_ALIAS ("REGION_WORK", RAM_EXT);
     35REGION_ALIAS ("REGION_STACK", RAM_EXT);
    2736
    2837INCLUDE linkcmds.base
    29 
    30 bsp_workspace_start = bsp_section_bss_end;
    31 
  • c/src/lib/libbsp/powerpc/mpc55xxevb/startup/linkcmds.phycore_mpc5554

    rf23c9ed r9e7758b  
    66{
    77        ROM (RX)       : ORIGIN = 0x00000000, LENGTH = 2M
    8     RAM (AIW)      : ORIGIN = 0x40000000, LENGTH = 64K
     8        RAM (AIW)      : ORIGIN = 0x40000000, LENGTH = 64K
    99        RAM_EXT (AIW)  : ORIGIN = 0x21000000, LENGTH = 4M
    1010        DEBUG_RAM (AIW): ORIGIN = 0x21400000, LENGTH = 4M
     
    2828bsp_debug_ram_size = LENGTH (DEBUG_RAM);
    2929
    30 bsp_section_align = 32;
    31 
    32 REGION_ALIAS ("REGION_TEXT",      ROM);
    33 REGION_ALIAS ("REGION_VECTORS",   RAM);
    34 REGION_ALIAS ("REGION_DATA",      RAM);
    35 REGION_ALIAS ("REGION_BSS",       RAM_EXT);
     30REGION_ALIAS ("REGION_START", ROM);
     31REGION_ALIAS ("REGION_FAST_TEXT", RAM);
     32REGION_ALIAS ("REGION_FAST_TEXT_LOAD", ROM);
     33REGION_ALIAS ("REGION_TEXT", ROM);
     34REGION_ALIAS ("REGION_TEXT_LOAD", ROM);
     35REGION_ALIAS ("REGION_RODATA", ROM);
     36REGION_ALIAS ("REGION_RODATA_LOAD", ROM);
     37REGION_ALIAS ("REGION_FAST_DATA", RAM);
     38REGION_ALIAS ("REGION_FAST_DATA_LOAD", ROM);
     39REGION_ALIAS ("REGION_DATA", RAM);
     40REGION_ALIAS ("REGION_DATA_LOAD", ROM);
     41REGION_ALIAS ("REGION_BSS", RAM_EXT);
     42REGION_ALIAS ("REGION_RWEXTRA", RAM_EXT);
     43REGION_ALIAS ("REGION_WORK", RAM_EXT);
     44REGION_ALIAS ("REGION_STACK", RAM_EXT);
    3645
    3746INCLUDE linkcmds.base
    38 
    39 bsp_workspace_start = bsp_section_bss_end;
  • c/src/lib/libbsp/powerpc/mpc55xxevb/startup/sd-card-init.c

    rf23c9ed r9e7758b  
    3939        RTEMS_CHECK_RV_SC( rv, "rtems_libi2c_initialize");
    4040
     41#if MPC55XX_CHIP_TYPE / 10 != 551
    4142        /* DSPI D inputs are taken from DSPI C */
    4243        SIU.DISR.R = 0x000000FC;
     44#endif
    4345
    4446        /* DSPI A signals */
  • c/src/lib/libbsp/powerpc/mpc55xxevb/startup/start.S

    rf23c9ed r9e7758b  
    88
    99/*
    10  * Copyright (c) 2008
    11  * Embedded Brains GmbH
    12  * Obere Lagerstr. 30
    13  * D-82178 Puchheim
    14  * Germany
    15  * rtems@embedded-brains.de
    16  *
    17  * The license and distribution terms for this file may be found in the file
    18  * LICENSE in this distribution or at http://www.rtems.com/license/LICENSE.
     10 * Copyright (c) 2008-2011 embedded brains GmbH.  All rights reserved.
     11 *
     12 *  embedded brains GmbH
     13 *  Obere Lagerstr. 30
     14 *  82178 Puchheim
     15 *  Germany
     16 *  <rtems@embedded-brains.de>
     17 *
     18 * The license and distribution terms for this file may be
     19 * found in the file LICENSE in this distribution or at
     20 * http://www.rtems.com/license/LICENSE.
     21 *
     22 * $Id$
    1923 */
    2024
     
    2529 */
    2630
     31#include <bspopts.h>
     32
    2733#include <libcpu/powerpc-utility.h>
     34
    2835#include <mpc55xx/reg-defs.h>
    29 #include <bspopts.h>
     36
     37#include <bsp/vectors.h>
     38
     39#define HAS_CACHE (BSP_DATA_CACHE_ENABLED || BSP_INSTRUCTION_CACHE_ENABLED)
     40
     41        .extern mpc55xx_fmpll_config
     42        .extern mpc55xx_fmpll_init
     43        .extern mpc55xx_flash_init
     44        .extern mpc55xx_early_init
     45        .extern bsp_start_zero
     46        .extern bsp_ram_start
     47        .extern bsp_ram_size
     48        .extern bsp_ram_end
     49        .extern __eabi
     50        .extern boot_card
     51
     52        .globl _start
    3053       
    31 .section ".bsp_start_text", "ax"
    3254#ifdef MPC55XX_BOOTFLAGS
    33 PUBLIC_VAR (mpc55xx_bootflag_0)
    34 PUBLIC_VAR (mpc55xx_bootflag_1)
    35 #endif
    36 PUBLIC_VAR (start)
    37 .globl  fmpll_syncr_vals
    38 bam_rchw:
    39 /*
    40  * BAM
    41  */
     55        .globl mpc55xx_bootflag_0
     56        .globl mpc55xx_bootflag_1
     57#endif
     58
     59        .section ".bsp_start_text", "ax"
    4260
    4361        /* BAM: RCHW */
    4462        .int 0x005a0000
    4563
     64        /* BAM: Address of start instruction */
     65        .int _start
     66
    4667#ifdef MPC55XX_BOOTFLAGS
    47         /* BAM: Address of start instruction
    48      *      We skip over the next two boot flag words to the next
    49      *      64-bit aligned start address. It is 64-bit aligned
    50      *      to play well with FLASH programming.
    51      *      These boot flags can be set by debuggers and emulators to
    52      *      customize boot.
    53      *      Currently bit0 of bootflag_0 means to "skip setting up the MMU",
    54      *      allowing external MMU setup in a debugger before branching
    55      *      to 0x10.  This can be used e.g., to map FLASH into RAM.
    56      */
    57         .int 0x00000010 /* Start address is 0x10. */
    58 
     68        /*
     69         * We skip over the next two boot flag words to the next 64-bit
     70         * aligned start address. It is 64-bit aligned to play well with
     71         * FLASH programming.  These boot flags can be set by debuggers
     72         * and emulators to customize boot.  Currently bit0 of
     73         * bootflag_0 means to "skip setting up the MMU", allowing
     74         * external MMU setup in a debugger before branching to 0x10.
     75         * This can be used e.g., to map FLASH into RAM.
     76         */
    5977mpc55xx_bootflag_0:
    60     .int 0xffffffff
     78        .int 0xffffffff
    6179mpc55xx_bootflag_1:
    62     .int 0xffffffff
    63 
     80        .int 0xffffffff
     81#endif
     82
     83_start:
     84
     85        /* Enable time base */
     86        li      r0, 0
     87        mtspr   TBWU, r0
     88        mtspr   TBWL, r0
     89        mfspr   r2, HID0
     90        ori     r2, r2, 0x4000
     91        mtspr   HID0, r2
     92
     93        /* FMPLL setup */
     94        LWI     r3, mpc55xx_fmpll_config
     95        bl      mpc55xx_fmpll_init
     96
     97        /* Enable branch prediction */
     98        LWI     r2, BUCSR_BBFI | BUCSR_BPEN
     99        mtspr   BUCSR, r2
     100
     101        /* Set intermediate stack start to end of internal SRAM */
     102        LA      r1, bsp_ram_end
     103        subi    r1, r1, 16
     104
     105        /* Enable SPE */
     106        mfmsr   r2
     107        oris    r2, r2, 0x200
     108        mtmsr   r2
     109
     110        /* Config internal flash */
     111        bl      mpc55xx_flash_init
     112
     113#if HAS_CACHE
     114        bl config_cache
     115
     116        /* Enable cache in the MMU for the internal SRAM */
     117        LWI     r3, 0x10030000
     118        mtspr   FSL_EIS_MAS0, r3
     119        tlbre
     120        LWI     r4, ~0x00000008
     121        mfspr   r3, FSL_EIS_MAS2
     122        and     r3, r3, r4
     123        mtspr   FSL_EIS_MAS2, r3
     124        tlbwe
     125#endif
     126
     127        /* Zero internal SRAM (needed to get proper ECC) */
     128        LA      r3, bsp_ram_start
     129        LA      r4, bsp_ram_size
     130        bl      bsp_start_zero
     131
     132        /* Initialize intermediate start stack */
     133        li      r0, 0
     134        stw     r0, 0(r1)
     135        stw     r0, 4(r1)
     136
     137        /* Do early initialization */
     138        bl      mpc55xx_early_init
     139
     140        /* Set up EABI and SYSV environment */
     141        bl      __eabi
     142
     143        /* Initialize start stack */
     144        LWI     r1, start_stack_end
     145        subi    r1, r1, 16
     146        li      r0, 0
     147        stw     r0, 0(r1)
     148
     149        /* Clear command line */
     150        li      r3, 0
     151
     152        /* Start RTEMS */
     153        bl      boot_card
     154
     155        /* Spin around */
     156twiddle:
     157        b       twiddle
     158
     159#if HAS_CACHE
     160config_cache:
     161
     162        /* Load zero, CINV, and CABT) */
     163        li      r0, 0
     164        li      r3, 0x2
     165        li      r4, 0x4
     166
     167#if MPC55XX_CHIP_TYPE / 10 == 567
     168start_instruction_cache_invalidation:
     169
     170        /* Clear instruction cache invalidation abort */
     171        mtspr   FSL_EIS_L1CSR1, r0
     172
     173        /* Start instruction cache invalidation */
     174        mtspr   FSL_EIS_L1CSR1, r3
     175
     176get_instruction_cache_invalidation_status:
     177
     178        /* Get instruction cache invalidation status */
     179        mfspr   r5, FSL_EIS_L1CSR1
     180
     181        /* Check CABT */
     182        and.    r6, r5, r4
     183        bne     start_instruction_cache_invalidation
     184
     185        /* Check CINV */
     186        and.    r6, r5, r3
     187        bne     get_instruction_cache_invalidation_status
     188
     189        /* Save instruction cache settings */
     190        LWI     r6, 0x00010001
     191        isync
     192        msync
     193        mtspr   FSL_EIS_L1CSR1, r6
     194#endif /* MPC55XX_CHIP_TYPE / 10 == 567 */
     195
     196start_data_cache_invalidation:
     197
     198        /* Clear data cache invalidation abort */
     199        mtspr   FSL_EIS_L1CSR0, r0
     200
     201        /* Start data cache invalidation */
     202        mtspr   FSL_EIS_L1CSR0, r3
     203
     204get_data_cache_invalidation_status:
     205
     206        /* Get data cache invalidation status */
     207        mfspr   r5, FSL_EIS_L1CSR0
     208
     209        /* Check CABT */
     210        and.    r6, r5, r4
     211        bne     start_data_cache_invalidation
     212
     213        /* Check CINV */
     214        and.    r6, r5, r3
     215        bne     get_data_cache_invalidation_status
     216
     217        /* Save data cache settings */
     218#if MPC55XX_CHIP_TYPE / 10 != 567
     219        /* FIXME: CORG??? 0x00180011 */
     220        LWI     r6, 0x00100001
    64221#else
    65         .int 0x00000008 /* Start address is 0x08. */
    66 #endif
    67 
    68 /*
    69  * Enable time base
    70  */
    71 start: 
    72         li r0, 0
    73         mtspr TBWU, r0
    74         mtspr TBWL, r0
    75         mfspr r2, HID0
    76         ori r2, r2, 0x4000
    77         mtspr HID0, r2
    78 
    79 /*
    80  * System clock
    81  */
    82 
    83         LWI r3,fmpll_syncr_vals
    84         bl SYM (mpc55xx_fmpll_reset_config)
    85 
    86 /*
    87  * Enable branch prediction
    88  */
    89 
    90         LWI r2, BUCSR_BBFI | BUCSR_BPEN
    91         mtspr BUCSR, r2
    92 
    93 /*
    94  * Basics
    95  */
    96 
    97         /* Set stack start to end of ram */
    98         LA r1, bsp_ram_end
    99         addi r1, r1, -8
    100 
    101         /* Enable SPE */
    102         mfmsr r2
    103         oris r2, r2, 0x200
    104         mtmsr r2
    105 
    106         /* Config internal flash */
    107         bl SYM (mpc55xx_flash_config)
    108 
    109 #if BSP_DATA_CACHE_ENABLED || BSP_INSTRUCTION_CACHE_ENABLED
    110         /* FIXME: Config cache */
    111         bl config_cache
    112 #endif /* BSP_DATA_CACHE_ENABLED || BSP_INSTRUCTION_CACHE_ENABLED */
    113 
    114 /*
    115  * TODO, FIXME: Enable cache in the MMU for the SRAM
    116  */
    117 
    118 .equ MAS0, 624
    119 .equ MAS1, 625
    120 .equ MAS2, 626
    121 .equ MAS3, 627
    122 
    123 /* Read back MMU TLB1 entry 3 (internal SRAM) and enable the cache.
    124  */
    125         LWI r3, 0x10030000
    126         mtspr MAS0, r3
    127         tlbre
    128         LWI r4, ~0x00000008
    129         mfspr r3, MAS2
    130         and r3, r3, r4
    131         mtspr MAS2, r3
    132         tlbwe
    133 
    134 /*
    135  * TODO, FIXME: Set MMU for the external SRAM
    136  */
    137 
    138 /* Read back MMU TLB1 entry 2 (external SRAM) and set the
    139  * logical address to the external RAM start.
    140  */
    141         LWI r3, 0x10020000
    142         mtspr MAS0, r3
    143         tlbre
    144         LWI r4, 0xfff
    145         mfspr r3, MAS3
    146         and r3, r3, r4
    147         LA r4, bsp_external_ram_start
    148         or r3, r3, r4
    149         mtspr MAS3, r3
    150         tlbwe
    151 
    152 /* Read back MMU TLB1 entry 1 (internal flash) and disable
    153  * write access.
    154  */
    155         LWI r3, 0x10010000
    156         mtspr MAS0, r3
    157         tlbre
    158         LWI r4, ~0x0000000C
    159         mfspr r3, MAS3
    160         and r3, r3, r4
    161         mtspr MAS3, r3
    162         tlbwe
    163 
    164 /*
    165  * Zero RAM (needed to get proper ECC)
    166  */
    167 
    168         /* Addresses */
    169         LA r3, bsp_ram_start
    170         LA r4, bsp_ram_size
    171 
    172         /* Zero */
    173         bl SYM (bsp_start_zero)
    174 
    175 /*
    176  * Copy data
    177  */
    178 
    179         /* Addresses */
    180         LA r3, bsp_section_text_end
    181         LA r4, bsp_section_data_start
    182         LA r5, bsp_section_data_end
    183 
    184         /* Assert: Proper alignment of source start */
    185         andi. r6, r3, 0x7
    186         bne twiddle
    187 
    188         /* Assert: Proper alignment of destination start */
    189         andi. r6, r4, 0x7
    190         bne twiddle
    191 
    192         /* Assert: Proper alignment of destination end */
    193         andi. r6, r5, 0x7
    194         bne twiddle
    195 
    196         /* Data size = destination end - destination start */
    197         subf r5, r4, r5
    198 
    199         /* Copy */
    200         bl SYM (mpc55xx_copy_8)
    201 
    202         /* Save time and get time delta */
    203         mftb r26
    204         subf r25, r25, r26
    205 
    206 /*
    207  * Prepare high level initialization
    208  */
    209 
    210         /* Create NULL */
    211         li r0, 0
    212 
    213         /* Return address */
    214         stw r0, 4(r1)
    215 
    216         /* Back chain */
    217         stw r0, 0(r1)
    218 
    219         /* Read-only small data */
    220         LA r2, _SDA2_BASE_
    221 
    222         /* Read-write small data */
    223         LA r13, _SDA_BASE_
    224 
    225 /*
    226  * Start RTEMS
    227  */
    228 
    229         /* Clear command line */
    230         xor r3, r3, r3
    231 
    232         /* Start RTEMS */
    233         bl SYM (boot_card)
    234 
    235         /* Spin around */
    236         b twiddle
    237 
    238 .equ L1CSR0, 1010
    239 .equ L1CSR0_CINV, 0x2
    240 .equ L1CSR0_CABT, 0x4
    241 /* FIXME: CORG??? .equ L1CSR0_SETTINGS, 0x00180011 */
    242 .equ L1CSR0_SETTINGS, 0x00100001
    243 
    244 /*
    245  * Configure cache
    246  */
    247 config_cache:
    248         /* Start cache invalidation */
    249         LWI r5, L1CSR0_CINV
    250         mtspr L1CSR0, r5
    251 
    252         /* Bit masks to test and clear invalidation abortion (CABT) */
    253         LWI r6, L1CSR0_CABT
    254         not r7, r6
    255 
    256         /* Wait for cache invalidation to complete */
    257 check_cache_invalidation:
    258         mfspr r9, L1CSR0
    259 
    260         /* Check if the invalidate was aborted */
    261         and. r10, r9, r6
    262         beq no_chache_invalidation_abort
    263 
    264         /* Clear CABT bit */
    265         and r10, r9, r7
    266         mtspr L1CSR0, r10
    267 
    268         /* Retry invalidation */
    269         b config_cache
    270 
    271 no_chache_invalidation_abort:
    272         /* Check CINV bit */
    273         and. r10, r5, r9
    274 
    275         /* Wait? */
    276         bne check_cache_invalidation
    277 
    278         /* Enable cache */
    279         LWI r6, L1CSR0_SETTINGS
    280         mfspr r5, L1CSR0
    281         or r5, r5, r6
     222        LWI     r6, 0x00190001
     223#endif
     224        isync
    282225        msync
    283         isync
    284         mtspr L1CSR0, r5
     226        mtspr   FSL_EIS_L1CSR0, r6
    285227
    286228        /* Return */
    287229        blr
    288 
    289 twiddle:
    290         b       twiddle
     230#endif /* HAS_CACHE */
     231
     232        /* Start stack area */
     233        .section ".bsp_rwextra", "aw", @nobits
     234        .align 4
     235        .space 4096
     236start_stack_end:
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