Changeset 9ddff29 in rtems


Ignore:
Timestamp:
Feb 11, 2011, 8:57:36 AM (9 years ago)
Author:
Ralf Corsepius <ralf.corsepius@…>
Branches:
4.11, master
Children:
9f9371f
Parents:
05d72d5
Message:

2011-02-11 Ralf Corsépius <ralf.corsepius@…>

  • cpu.c, irq.c, rtems/score/lm32.h: Use "asm" instead of "asm" for improved c99-compliance.
Location:
cpukit/score/cpu/lm32
Files:
4 edited

Legend:

Unmodified
Added
Removed
  • cpukit/score/cpu/lm32/ChangeLog

    r05d72d5 r9ddff29  
     12011-02-11      Ralf Corsépius <ralf.corsepius@rtems.org>
     2
     3        * cpu.c, irq.c, rtems/score/lm32.h:
     4        Use "__asm__" instead of "asm" for improved c99-compliance.
     5
    162010-10-21      Joel Sherrill <joel.sherrill@oarcorp.com>
    27
  • cpukit/score/cpu/lm32/cpu.c

    r05d72d5 r9ddff29  
    170170     * LM32 qemu target interprets this nop instruction as HLT.
    171171     */
    172     asm volatile("and r0, r0, r0");
     172    __asm__ volatile("and r0, r0, r0");
    173173 }
    174174}
  • cpukit/score/cpu/lm32/irq.c

    r05d72d5 r9ddff29  
    3636void *_exception_stack_frame;
    3737
    38 register unsigned long  *stack_ptr asm("sp");
     38register unsigned long  *stack_ptr __asm__ ("sp");
    3939
    4040void __ISR_Handler(uint32_t vector, CPU_Interrupt_frame *ifr)
  • cpukit/score/cpu/lm32/rtems/score/lm32.h

    r05d72d5 r9ddff29  
    7070
    7171#define lm32_read_interrupts( _ip) \
    72   asm volatile ("rcsr %0, ip":"=r"(_ip));
     72  __asm__ volatile ("rcsr %0, ip":"=r"(_ip));
    7373
    7474#define lm32_disable_interrupts( _level ) \
    7575  do { register uint32_t ie; \
    76     asm volatile ("rcsr %0,ie":"=r"(ie)); \
     76    __asm__ volatile ("rcsr %0,ie":"=r"(ie)); \
    7777    _level = ie; \
    7878    ie &= (~0x0001); \
    79     asm volatile ("wcsr ie,%0"::"r"(ie)); \
     79    __asm__ volatile ("wcsr ie,%0"::"r"(ie)); \
    8080  } while (0)
    8181
    8282#define lm32_enable_interrupts( _level ) \
    83   asm volatile ("wcsr ie,%0"::"r"(_level));
     83  __asm__ volatile ("wcsr ie,%0"::"r"(_level));
    8484
    8585#define lm32_flash_interrupts( _level ) \
    8686  do { register uint32_t ie; \
    87     asm volatile ("wcsr ie,%0"::"r"(_level)); \
     87    __asm__ volatile ("wcsr ie,%0"::"r"(_level)); \
    8888    ie = _level & (~0x0001); \
    89     asm volatile ("wcsr ie,%0"::"r"(ie)); \
     89    __asm__ volatile ("wcsr ie,%0"::"r"(ie)); \
    9090  } while (0)
    9191
    9292#define lm32_interrupt_unmask( _mask ) \
    9393  do { register uint32_t im; \
    94     asm volatile ("rcsr %0,im":"=r"(im)); \
     94    __asm__ volatile ("rcsr %0,im":"=r"(im)); \
    9595    im |= _mask; \
    96     asm volatile ("wcsr im,%0"::"r"(im)); \
     96    __asm__ volatile ("wcsr im,%0"::"r"(im)); \
    9797  } while (0)
    9898
    9999#define lm32_interrupt_mask( _mask ) \
    100100  do { register uint32_t im; \
    101     asm volatile ("rcsr %0,im":"=r"(im)); \
     101    __asm__ volatile ("rcsr %0,im":"=r"(im)); \
    102102    im &= ~_mask; \
    103     asm volatile ("wcsr im,%0"::"r"(im)); \
     103    __asm__ volatile ("wcsr im,%0"::"r"(im)); \
    104104  } while (0)
    105105
    106106#define lm32_interrupt_ack( _mask ) \
    107107  do { register uint32_t ip = _mask; \
    108     asm volatile ("wcsr ip,%0"::"r"(ip)); \
     108    __asm__ volatile ("wcsr ip,%0"::"r"(ip)); \
    109109  } while (0)
    110110
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