Changeset 9d5b6a8 in rtems


Ignore:
Timestamp:
Apr 26, 2005, 11:20:36 PM (15 years ago)
Author:
Joel Sherrill <joel.sherrill@…>
Branches:
4.10, 4.11, 4.8, 4.9, master
Children:
7c6a5ca
Parents:
106e048
Message:

2005-04-26 Joel Sherrill <joel@…>

  • console/uart.h: Eliminate tabs.
Location:
c/src/lib/libbsp/powerpc/shared
Files:
2 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/powerpc/shared/ChangeLog

    r106e048 r9d5b6a8  
     12005-04-26      Joel Sherrill <joel@OARcorp.com>
     2
     3        * console/uart.h: Eliminate tabs.
     4
    152005-04-15      Jennifer Averett <jennifer.averett@oarcorp.com>
    26
  • c/src/lib/libbsp/powerpc/shared/console/uart.h

    r106e048 r9d5b6a8  
    4646 * or installing break callback
    4747 */
    48 typedef void (*BSP_UartBreakCbProc)(int                 uartMinor,
    49                                                                         unsigned        uartRBRLSRStatus,
    50                                                                         void            *termiosPrivatePtr,
    51                                                                         void            *private);
     48typedef void (*BSP_UartBreakCbProc)(
     49  int uartMinor,
     50  unsigned uartRBRLSRStatus,
     51  void  *termiosPrivatePtr,
     52  void  *private
     53);
    5254
    5355typedef struct BSP_UartBreakCbRec_ {
    54                 BSP_UartBreakCbProc             handler;        /* NOTE NOTE this handler runs in INTERRUPT CONTEXT */
    55                 void                                    *private;       /* closure pointer which is passed to the callback  */
     56  BSP_UartBreakCbProc  handler; /* NOTE: handler runs in INTERRUPT CONTEXT */
     57  void     *private; /* closure pointer which is passed to the callback  */
    5658} BSP_UartBreakCbRec, *BSP_UartBreakCb;
    5759
    58 #define BIOCGETBREAKCB  _IOR('b',1,sizeof(BSP_UartBreakCbRec))
    59 #define BIOCSETBREAKCB  _IOW('b',2,sizeof(BSP_UartBreakCbRec))
     60#define BIOCGETBREAKCB _IOR('b',1,sizeof(BSP_UartBreakCbRec))
     61#define BIOCSETBREAKCB _IOW('b',2,sizeof(BSP_UartBreakCbRec))
    6062
    6163/*
     
    105107 * Interrupt source definition via IIR
    106108 */
    107 #define MODEM_STATUS                            0
    108 #define NO_MORE_INTR                            1
    109 #define TRANSMITTER_HODING_REGISTER_EMPTY       2
    110 #define RECEIVER_DATA_AVAIL                     4
    111 #define RECEIVER_ERROR                          6
    112 #define CHARACTER_TIMEOUT_INDICATION            12
     109#define MODEM_STATUS                       0
     110#define NO_MORE_INTR                       1
     111#define TRANSMITTER_HODING_REGISTER_EMPTY  2
     112#define RECEIVER_DATA_AVAIL                4
     113#define RECEIVER_ERROR                     6
     114#define CHARACTER_TIMEOUT_INDICATION      12
    113115
    114116/*
    115117 * Bits definition of IER
    116118 */
    117 #define RECEIVE_ENABLE          0x1
    118 #define TRANSMIT_ENABLE         0x2
    119 #define RECEIVER_LINE_ST_ENABLE 0x4
    120 #define MODEM_ENABLE            0x8
    121 #define INTERRUPT_DISABLE       0x0
     119#define RECEIVE_ENABLE          0x1
     120#define TRANSMIT_ENABLE         0x2
     121#define RECEIVER_LINE_ST_ENABLE 0x4
     122#define MODEM_ENABLE            0x8
     123#define INTERRUPT_DISABLE       0x0
    122124
    123125/*
    124126 * Bits definition of the Line Status Register (LSR)
    125127 */
    126 #define DR      0x01    /* Data Ready */
    127 #define OE      0x02    /* Overrun Error */
    128 #define PE      0x04    /* Parity Error */
    129 #define FE      0x08    /* Framing Error */
    130 #define BI      0x10    /* Break Interrupt */
    131 #define THRE    0x20    /* Transmitter Holding Register Empty */
    132 #define TEMT    0x40    /* Transmitter Empty */
    133 #define ERFIFO  0x80    /* Error receive Fifo */
     128#define DR     0x01 /* Data Ready */
     129#define OE     0x02 /* Overrun Error */
     130#define PE     0x04 /* Parity Error */
     131#define FE     0x08 /* Framing Error */
     132#define BI     0x10 /* Break Interrupt */
     133#define THRE   0x20 /* Transmitter Holding Register Empty */
     134#define TEMT   0x40 /* Transmitter Empty */
     135#define ERFIFO 0x80 /* Error receive Fifo */
    134136
    135137/*
    136138 * Bits definition of the MODEM Control Register (MCR)
    137139 */
    138 #define DTR     0x01    /* Data Terminal Ready */
    139 #define RTS     0x02    /* Request To Send */
    140 #define OUT_1   0x04    /* Output 1, (reserved on COMPAQ I/O Board) */
    141 #define OUT_2   0x08    /* Output 2, Enable Asynchronous Port Interrupts */
    142 #define LB      0x10    /* Enable Internal Loop Back */
     140#define DTR   0x01 /* Data Terminal Ready */
     141#define RTS   0x02 /* Request To Send */
     142#define OUT_1 0x04 /* Output 1, (reserved on COMPAQ I/O Board) */
     143#define OUT_2 0x08 /* Output 2, Enable Asynchronous Port Interrupts */
     144#define LB    0x10 /* Enable Internal Loop Back */
    143145
    144146/*
     
    150152#define CHR_8_BITS 3
    151153
    152 #define WL      0x03    /* Word length mask */
    153 #define STB     0x04    /* 1 Stop Bit, otherwise 2 Stop Bits */
    154 #define PEN     0x08    /* Parity Enabled */
    155 #define EPS     0x10    /* Even Parity Select, otherwise Odd */
    156 #define SP      0x20    /* Stick Parity */
    157 #define BCB     0x40    /* Break Control Bit */
    158 #define DLAB    0x80    /* Enable Divisor Latch Access */
     154#define WL   0x03 /* Word length mask */
     155#define STB  0x04 /* 1 Stop Bit, otherwise 2 Stop Bits */
     156#define PEN  0x08 /* Parity Enabled */
     157#define EPS  0x10 /* Even Parity Select, otherwise Odd */
     158#define SP   0x20 /* Stick Parity */
     159#define BCB  0x40 /* Break Control Bit */
     160#define DLAB 0x80 /* Enable Divisor Latch Access */
    159161
    160162/*
    161163 * Bits definition of the MODEM Status Register (MSR)
    162164 */
    163 #define DCTS    0x01    /* Delta Clear To Send */
    164 #define DDSR    0x02    /* Delta Data Set Ready */
    165 #define TERI    0x04    /* Trailing Edge Ring Indicator */
    166 #define DDCD    0x08    /* Delta Carrier Detect Indicator */
    167 #define CTS     0x10    /* Clear To Send (when loop back is active) */
    168 #define DSR     0x20    /* Data Set Ready (when loop back is active) */
    169 #define RI      0x40    /* Ring Indicator (when loop back is active) */
    170 #define DCD     0x80    /* Data Carrier Detect (when loop back is active) */
     165#define DCTS 0x01 /* Delta Clear To Send */
     166#define DDSR 0x02 /* Delta Data Set Ready */
     167#define TERI 0x04 /* Trailing Edge Ring Indicator */
     168#define DDCD 0x08 /* Delta Carrier Detect Indicator */
     169#define CTS  0x10 /* Clear To Send (when loop back is active) */
     170#define DSR  0x20 /* Data Set Ready (when loop back is active) */
     171#define RI   0x40 /* Ring Indicator (when loop back is active) */
     172#define DCD  0x80 /* Data Carrier Detect (when loop back is active) */
    171173
    172174/*
     
    174176 */
    175177
    176 #define FIFO_CTRL   0x01    /* Set to 1 permit access to other bits */
    177 #define FIFO_EN     0x01    /* Enable the FIFO */
    178 #define XMIT_RESET  0x02    /* Transmit FIFO Reset */
    179 #define RCV_RESET   0x04    /* Receive FIFO Reset */
    180 #define FCR3        0x08    /* do not understand manual! */
     178#define FIFO_CTRL  0x01 /* Set to 1 permit access to other bits */
     179#define FIFO_EN    0x01 /* Enable the FIFO */
     180#define XMIT_RESET 0x02 /* Transmit FIFO Reset */
     181#define RCV_RESET  0x04 /* Receive FIFO Reset */
     182#define FCR3       0x08 /* do not understand manual! */
    181183
    182 #define RECEIVE_FIFO_TRIGGER1   0x0  /* trigger recieve interrupt after 1 byte  */
    183 #define RECEIVE_FIFO_TRIGGER4   0x40 /* trigger recieve interrupt after 4 byte  */
    184 #define RECEIVE_FIFO_TRIGGER8   0x80 /* trigger recieve interrupt after 8 byte  */
    185 #define RECEIVE_FIFO_TRIGGER12  0xc0 /* trigger recieve interrupt after 12 byte */
    186 #define TRIG_LEVEL              0xc0 /* Mask for the trigger level              */
     184#define RECEIVE_FIFO_TRIGGER1  0x00 /* trigger RX interrupt after 1 byte  */
     185#define RECEIVE_FIFO_TRIGGER4  0x40 /* trigger RX interrupt after 4 bytes  */
     186#define RECEIVE_FIFO_TRIGGER8  0x80 /* trigger RX interrupt after 8 bytes  */
     187#define RECEIVE_FIFO_TRIGGER12 0xc0 /* trigger RX interrupt after 12 bytes */
     188#define TRIG_LEVEL             0xc0 /* Mask for the trigger level   */
    187189
    188190#endif /* _BSPUART_H */
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