Changeset 9cd4a6e8 in rtems
- Timestamp:
- 01/03/03 16:48:28 (21 years ago)
- Branches:
- 4.10, 4.11, 4.8, 4.9, 5, master
- Children:
- fad4a52b
- Parents:
- 8f10c92
- Location:
- c/src/lib/libbsp/powerpc/shared
- Files:
-
- 2 edited
Legend:
- Unmodified
- Added
- Removed
-
c/src/lib/libbsp/powerpc/shared/ChangeLog
r8f10c92 r9cd4a6e8 1 2002-12-08 Greg Menke <gregory.menke@gsfc.nasa.gov> 2 3 * bootloader/head.S: Added support for optional debug via PPCbug. 4 Also turn off mmu/caches for the bootstrap phase, which seems to 5 cause trouble with the 603. The cpu init functions in the bsp 6 get all that stuff going properly. 7 1 8 2002-12-19 Joel Sherrill <joel@OARcorp.com> 2 9 -
c/src/lib/libbsp/powerpc/shared/bootloader/head.S
r8f10c92 r9cd4a6e8 19 19 #include <rtems/score/cpu.h> 20 20 #include "bootldr.h" 21 22 #undef TEST_PPCBUG_CALLS 21 22 #define TEST_PPCBUG_CALLS 23 #undef TEST_PPCBUG_CALLS 24 23 25 #define FRAME_SIZE 32 24 #define LOCK_CACHES (HID0_DLOCK |HID0_ILOCK)25 #define INVL_CACHES (HID0_DCI |HID0_ICFI)26 #define ENBL_CACHES (HID0_DCE |HID0_ICE)26 #define LOCK_CACHES (HID0_DLOCK | HID0_ILOCK) 27 #define INVL_CACHES (HID0_DCI | HID0_ICFI) 28 #define ENBL_CACHES (HID0_DCE | HID0_ICE) 27 29 28 30 #define USE_PPCBUG 29 31 #undef USE_PPCBUG 30 32 33 34 #define PRINT_CHAR(c) \ 35 addi r20,r3,0 ; \ 36 li r3,c ; \ 37 li r10,0x20 ; \ 38 sc ; \ 39 addi r3,r20,0 ; \ 40 li r10,0x26 ; \ 41 sc 42 43 44 45 31 46 #define MONITOR_ENTER \ 32 47 mfmsr r10 ; \ … … 35 50 li r10,0x63 ; \ 36 51 sc 37 52 53 54 38 55 START_GOT 39 56 GOT_ENTRY(_GOT2_TABLE_) … … 54 71 .globl start 55 72 .type start,@function 73 56 74 /* Point the stack into the PreP partition header in the x86 reserved 57 75 * code area, so that simple C routines can be called. … … 59 77 start: 60 78 #ifdef USE_PPCBUG 61 MONITOR_ENTER 79 MONITOR_ENTER 62 80 #endif 63 81 bl 1f … … 67 85 stmw r26,FRAME_SIZE-24(r1) 68 86 GET_GOT 69 mfmsr r28 /* Turn off interrupts */87 mfmsr r28 /* Turn off interrupts */ 70 88 ori r0,r28,MSR_EE 71 89 xori r0,r0,MSR_EE … … 73 91 74 92 /* Enable the caches, from now on cr2.eq set means processor is 601 */ 93 75 94 mfpvr r0 76 95 mfspr r29,HID0 … … 78 97 cmplwi cr2,r0,1 79 98 beq 2,2f 99 100 101 /* 102 * commented out, 11/7/2002, gregm. This instruction sequence seems to 103 * be pathological on the 603e. 104 * 105 80 106 #ifndef USE_PPCBUG 81 107 ori r0,r29,ENBL_CACHES|INVL_CACHES|LOCK_CACHES … … 85 111 mtspr HID0,r0 86 112 #endif 113 */ 114 115 87 116 2: bl reloc 88 117 … … 116 145 lwz r3,mover(bd) 117 146 lwz r6,cache_lsize(bd) 147 118 148 bl codemove 149 119 150 mtctr r3 # Where the temporary codemove is. 120 151 lwz r3,image(bd) … … 124 155 lwz r6,cache_lsize(bd) 125 156 lwz r8,GOT(moved) 157 126 158 sub r7,r3,r4 # Difference to adjust pointers. 127 159 add r8,r8,r7 128 160 add r30,r30,r7 129 161 add bd,bd,r7 162 130 163 /* Call the copy routine but return to the new area. */ 164 131 165 mtlr r8 # for the return address 132 166 bctr # returns to the moved instruction 167 133 168 /* Establish the new top stack frame. */ 134 169 moved: lwz r1,stack(bd) … … 154 189 * during this time! 155 190 */ 156 #ifndef USE_PPCBUG 157 4: bl MMUoff 158 #endif 191 4: 192 #ifdef USE_PPCBUG 193 PRINT_CHAR('M') 194 #endif 195 bl MMUoff 196 197 #ifdef USE_PPCBUG 198 PRINT_CHAR('B') 199 #endif 159 200 bl flush_tlb 201 160 202 /* Some firmware versions leave stale values in the BATs, it's time 161 203 * to invalidate them to avoid interferences with our own mappings. … … 163 205 * the [ID]BATU. Bloat, bloat.. fortunately thrown away later. 164 206 */ 207 #ifdef USE_PPCBUG 208 PRINT_CHAR('T') 209 #endif 165 210 li r3,0 166 211 beq cr2,5f … … 180 225 addi r3,r3,__size@sectoff@l 181 226 sync # We are going to touch SDR1 ! 227 #ifdef USE_PPCBUG 228 PRINT_CHAR('i') 229 #endif 182 230 bl mm_init 231 232 #ifdef USE_PPCBUG 233 PRINT_CHAR('M') 234 #endif 183 235 bl MMUon 184 236 … … 193 245 sc 194 246 #endif 247 #ifdef USE_PPCBUG 248 PRINT_CHAR('H') 249 #endif 195 250 bl setup_hw 196 251 lwz r4,GOT(_binary_rtems_gz_start) … … 222 277 /* 223 278 * Linux code again 279 * 224 280 lis r30,0xdeadc0de@ha 225 281 addi r30,r30,0xdeadc0de@l … … 228 284 */ 229 285 dcbst 0,r30 /* Make sure it's in memory ! */ 286 230 287 /* We just flash invalidate and disable the dcache, unless it's a 601, 231 288 * critical areas have been flushed and we don't care about the stack … … 239 296 xori r0,r0,HID0_DCI|HID0_DCE 240 297 mtspr HID0,r0 298 241 299 /* Provisional return to FW, works for PPCBug */ 242 300 #if 0 … … 287 345 .globl MMUon 288 346 .type MMUon,@function 289 MMUon: mfmsr r0 347 MMUon: blr 348 nop 349 350 /* 351 mfmsr r0 290 352 ori r0,r0,MSR_IR|MSR_DR|MSR_IP 291 353 mflr r11 … … 294 356 mtsrr1 r0 295 357 rfi 358 */ 296 359 .globl MMUoff 297 360 .type MMUoff,@function 298 MMUoff: mfmsr r0 361 MMUoff: blr 362 nop 363 364 /* 365 mfmsr r0 299 366 ori r0,r0,MSR_IR|MSR_DR|MSR_IP 300 367 mflr r11 … … 303 370 mtsrr1 r0 304 371 rfi 372 */ 305 373 306 374 /* Due to the PPC architecture (and according to the specifications), a
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