Changeset 9c1dc8c in rtems
- Timestamp:
- 01/12/01 13:36:30 (22 years ago)
- Branches:
- 4.10, 4.11, 4.8, 4.9, 5, master
- Children:
- d2959b2
- Parents:
- d9f6165
- Files:
-
- 4 edited
Legend:
- Unmodified
- Added
- Removed
-
c/src/exec/score/cpu/mips/ChangeLog
rd9f6165 r9c1dc8c 1 2001-01-12 Joel Sherrill <joel@OARcorp.com> 2 3 * rtems/score/mips.h (mips_get_sr, mips_set_sr): Corrected 4 register constraints from "general" to "register". 5 1 6 2001-01-09 Joel Sherrill <joel@OARcorp.com> 2 7 -
c/src/exec/score/cpu/mips/rtems/score/mips.h
rd9f6165 r9c1dc8c 78 78 #define mips_get_sr( _x ) \ 79 79 do { \ 80 asm volatile( "mfc0 %0, $12; nop" : "= g" (_x) :); \80 asm volatile( "mfc0 %0, $12; nop" : "=r" (_x) : ); \ 81 81 } while (0) 82 82 83 83 #define mips_set_sr( _x ) \ 84 84 do { \ 85 unsigned int __x = (_x); \85 register unsigned int __x = (_x); \ 86 86 asm volatile( "mtc0 %0, $12; nop" : : "r" (__x) ); \ 87 87 } while (0) -
cpukit/score/cpu/mips/ChangeLog
rd9f6165 r9c1dc8c 1 2001-01-12 Joel Sherrill <joel@OARcorp.com> 2 3 * rtems/score/mips.h (mips_get_sr, mips_set_sr): Corrected 4 register constraints from "general" to "register". 5 1 6 2001-01-09 Joel Sherrill <joel@OARcorp.com> 2 7 -
cpukit/score/cpu/mips/rtems/score/mips.h
rd9f6165 r9c1dc8c 78 78 #define mips_get_sr( _x ) \ 79 79 do { \ 80 asm volatile( "mfc0 %0, $12; nop" : "= g" (_x) :); \80 asm volatile( "mfc0 %0, $12; nop" : "=r" (_x) : ); \ 81 81 } while (0) 82 82 83 83 #define mips_set_sr( _x ) \ 84 84 do { \ 85 unsigned int __x = (_x); \85 register unsigned int __x = (_x); \ 86 86 asm volatile( "mtc0 %0, $12; nop" : : "r" (__x) ); \ 87 87 } while (0)
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