Changeset 9aceddaf in rtems
- Timestamp:
- 02/11/98 14:50:31 (25 years ago)
- Branches:
- 4.10, 4.11, 4.8, 4.9, 5, master
- Children:
- 7175b59
- Parents:
- 84b0f7c9
- Location:
- doc/supplements
- Files:
-
- 17 edited
Legend:
- Unmodified
- Added
- Removed
-
doc/supplements/powerpc/bsp.t
r84b0f7c9 r9aceddaf 37 37 38 38 An RTEMS based application is initiated or 39 re-initiated when the PowerPC processor is reset. When the PowerPC 40 is reset, the processor performs the following actions: 39 re-initiated when the PowerPC processor is reset. The PowerPC 40 architecture defines a Reset Exception, but leaves the 41 details of the CPU state as implementation specific. Please 42 refer to the User's Manual for the CPU model in question. 41 43 42 @itemize @bullet 43 @item TBD 44 45 @item TBD 46 47 @item TBD 48 @end itemize 49 50 The processor then begins to execute the code at location 0x00100. 51 By using the SRR1 bit corresponding to MSR[RI] the softwere may 52 distinguish between power-on reset and other types of system resets. 53 54 It is important to note that all fields in the psr 55 are not explicitly set by the above steps and all other 56 registers retain their value from the previous execution mode. 57 This is true even of the Trap Base Register (TBR) whose contents 58 reflect the last trap which occurred before the reset. 44 In general, at power-up the PowerPC begin execution at address 45 0xFFF00100 in supervisor mode with all exceptions disabled. For 46 soft resets, the CPU will vector to either 0xFFF00100 or 0x00000100 47 depending upon the setting of the Exception Prefix bit in the MSR. 48 If during a soft reset, a Machine Check Exception occurs, then the 49 CPU may execute a hard reset. 59 50 60 51 @ifinfo … … 64 55 65 56 It is the responsibility of the application's 66 initialization code to initialize the TBR and install trap 67 handlers for at least the register window overflow and register 68 window underflow conditions. Traps should be enabled before 69 invoking any subroutines to allow for register window 70 management. However, interrupts should be disabled by setting 71 the Processor Interrupt Level (pil) field of the psr to 15. 72 RTEMS installs it's own Trap Table as part of initialization 73 which is initialized with the contents of the Trap Table in 74 place when the rtems_initialize_executive directive was invoked. 75 Upon completion of executive initialization, interrupts are 76 enabled. 57 initialization code to initialize the CPU and board 58 to a quiescent state before invoking the @code{rtems_initialize_executive} 59 directive. It is recommended that the BSP utilize the @code{predriver_hook} 60 to install default handlers for all exceptions. These default handlers 61 may be overwritten as various device drivers and subsystems install 62 their own exception handlers. Upon completion of RTEMS executive 63 initialization, all interrupts are enabled. 77 64 78 65 If this PowerPC implementation supports on-chip caching 79 66 and this is to be utilized, then it should be enabled during the 80 reset application initialization code. 67 reset application initialization code. On-chip caching has been 68 observed to prevent some emulators from working properly, so it 69 may be necessary to run with caching disabled to use these emulators. 81 70 82 71 In addition to the requirements described in the 83 Board Support Packages chapter of the @value{LANGUAGE} 84 Applications User's Manual for the reset code 85 which is executed before the call to 86 rtems_initialize executive, the PowrePC version has the following 87 specific requirements: 72 @b{Board Support Packages} chapter of the @b{@value{LANGUAGE} 73 Applications User's Manual} for the reset code 74 which is executed before the call to @code{rtems_initialize_executive}, 75 the PowrePC version has the following specific requirements: 88 76 89 77 @itemize @bullet 90 @item Must leave the PR bit of the machine state register set so that91 t he PowerPC remains in the supervisor state.78 @item Must leave the PR bit of the Machine State Register (MSR) set 79 to 0 so the PowerPC remains in the supervisor state. 92 80 93 @item Must set stack pointer (sp ) such that a minimum stack81 @item Must set stack pointer (sp or r1) such that a minimum stack 94 82 size of MINIMUM_STACK_SIZE bytes is provided for the 95 rtems_initialize executivedirective.83 @code{rtems_initialize_executive} directive. 96 84 97 85 @item Must disable all external interrupts (i.e. clear the EI (EE) … … 101 89 conditions can be properly handled. 102 90 103 @item Must initialize the PowerPC's initial trap table with at104 least trap handlers for register window overflow and register 105 window underflow. 91 @item Must initialize the PowerPC's initial Exception Table with default 92 handlers. 93 106 94 @end itemize 107 95 -
doc/supplements/powerpc/bsp.texi
r84b0f7c9 r9aceddaf 37 37 38 38 An RTEMS based application is initiated or 39 re-initiated when the PowerPC processor is reset. When the PowerPC 40 is reset, the processor performs the following actions: 39 re-initiated when the PowerPC processor is reset. The PowerPC 40 architecture defines a Reset Exception, but leaves the 41 details of the CPU state as implementation specific. Please 42 refer to the User's Manual for the CPU model in question. 41 43 42 @itemize @bullet 43 @item TBD 44 45 @item TBD 46 47 @item TBD 48 @end itemize 49 50 The processor then begins to execute the code at location 0x00100. 51 By using the SRR1 bit corresponding to MSR[RI] the softwere may 52 distinguish between power-on reset and other types of system resets. 53 54 It is important to note that all fields in the psr 55 are not explicitly set by the above steps and all other 56 registers retain their value from the previous execution mode. 57 This is true even of the Trap Base Register (TBR) whose contents 58 reflect the last trap which occurred before the reset. 44 In general, at power-up the PowerPC begin execution at address 45 0xFFF00100 in supervisor mode with all exceptions disabled. For 46 soft resets, the CPU will vector to either 0xFFF00100 or 0x00000100 47 depending upon the setting of the Exception Prefix bit in the MSR. 48 If during a soft reset, a Machine Check Exception occurs, then the 49 CPU may execute a hard reset. 59 50 60 51 @ifinfo … … 64 55 65 56 It is the responsibility of the application's 66 initialization code to initialize the TBR and install trap 67 handlers for at least the register window overflow and register 68 window underflow conditions. Traps should be enabled before 69 invoking any subroutines to allow for register window 70 management. However, interrupts should be disabled by setting 71 the Processor Interrupt Level (pil) field of the psr to 15. 72 RTEMS installs it's own Trap Table as part of initialization 73 which is initialized with the contents of the Trap Table in 74 place when the rtems_initialize_executive directive was invoked. 75 Upon completion of executive initialization, interrupts are 76 enabled. 57 initialization code to initialize the CPU and board 58 to a quiescent state before invoking the @code{rtems_initialize_executive} 59 directive. It is recommended that the BSP utilize the @code{predriver_hook} 60 to install default handlers for all exceptions. These default handlers 61 may be overwritten as various device drivers and subsystems install 62 their own exception handlers. Upon completion of RTEMS executive 63 initialization, all interrupts are enabled. 77 64 78 65 If this PowerPC implementation supports on-chip caching 79 66 and this is to be utilized, then it should be enabled during the 80 reset application initialization code. 67 reset application initialization code. On-chip caching has been 68 observed to prevent some emulators from working properly, so it 69 may be necessary to run with caching disabled to use these emulators. 81 70 82 71 In addition to the requirements described in the 83 Board Support Packages chapter of the @value{LANGUAGE} 84 Applications User's Manual for the reset code 85 which is executed before the call to 86 rtems_initialize executive, the PowrePC version has the following 87 specific requirements: 72 @b{Board Support Packages} chapter of the @b{@value{LANGUAGE} 73 Applications User's Manual} for the reset code 74 which is executed before the call to @code{rtems_initialize_executive}, 75 the PowrePC version has the following specific requirements: 88 76 89 77 @itemize @bullet 90 @item Must leave the PR bit of the machine state register set so that91 t he PowerPC remains in the supervisor state.78 @item Must leave the PR bit of the Machine State Register (MSR) set 79 to 0 so the PowerPC remains in the supervisor state. 92 80 93 @item Must set stack pointer (sp ) such that a minimum stack81 @item Must set stack pointer (sp or r1) such that a minimum stack 94 82 size of MINIMUM_STACK_SIZE bytes is provided for the 95 rtems_initialize executivedirective.83 @code{rtems_initialize_executive} directive. 96 84 97 85 @item Must disable all external interrupts (i.e. clear the EI (EE) … … 101 89 conditions can be properly handled. 102 90 103 @item Must initialize the PowerPC's initial trap table with at104 least trap handlers for register window overflow and register 105 window underflow. 91 @item Must initialize the PowerPC's initial Exception Table with default 92 handlers. 93 106 94 @end itemize 107 95 -
doc/supplements/powerpc/callconv.t
r84b0f7c9 r9aceddaf 8 8 9 9 @ifinfo 10 @node Calling Conventions, Calling Conventions Introduction, CPU Model Dependent Features CPU Model Implementation Notes, Top10 @node Calling Conventions, Calling Conventions Introduction, CPU Model Dependent Features Low Power Model, Top 11 11 @end ifinfo 12 12 @chapter Calling Conventions … … 15 15 * Calling Conventions Introduction:: 16 16 * Calling Conventions Programming Model:: 17 * Calling Conventions Register Windows::18 17 * Calling Conventions Call and Return Mechanism:: 19 18 * Calling Conventions Calling Mechanism:: … … 54 53 55 54 @ifinfo 56 @node Calling Conventions Programming Model, Non-Floating Point Registers, Calling Conventions Introduction, Calling Conventions55 @node Calling Conventions Programming Model, Calling Conventions Non-Floating Point Registers, Calling Conventions Introduction, Calling Conventions 57 56 @end ifinfo 58 57 @section Programming Model 59 58 @ifinfo 60 59 @menu 61 * Non-Floating Point Registers::62 * Floating Point Registers::63 * Special Registers::60 * Calling Conventions Non-Floating Point Registers:: 61 * Calling Conventions Floating Point Registers:: 62 * Calling Conventions Special Registers:: 64 63 @end menu 65 64 @end ifinfo … … 69 68 70 69 @ifinfo 71 @node Non-Floating Point Registers,Floating Point Registers, Calling Conventions Programming Model, Calling Conventions Programming Model70 @node Calling Conventions Non-Floating Point Registers, Calling Conventions Floating Point Registers, Calling Conventions Programming Model, Calling Conventions Programming Model 72 71 @end ifinfo 73 72 @subsection Non-Floating Point Registers … … 86 85 @example 87 86 @group 88 +---------------+----------------+----------------------+ 89 | Register Name | Alternate Name | Description | 90 +---------------+----------------+----------------------+ 91 | g0 | na | reads return 0 | 92 | | | writes are ignored | 93 +---------------+----------------+----------------------+ 94 | o6 | sp | stack pointer | 95 +---------------+----------------+----------------------+ 96 | i6 | fp | frame pointer | 97 +---------------+----------------+----------------------+ 98 | i7 | na | return address | 99 +---------------+----------------+----------------------+ 87 +---------------+----------------+------------------------------+ 88 | Register Name | Alternate Name | Description | 89 +---------------+----------------+------------------------------+ 90 | r1 | sp | stack pointer | 91 +---------------+----------------+------------------------------+ 92 | | | global pointer to the Small | 93 | r2 | na | Constant Area (SDA2) | 94 +---------------+----------------+------------------------------+ 95 | r3 - r12 | na | parameter and result passing | 96 +---------------+----------------+------------------------------+ 97 | | | global pointer to the Small | 98 | r13 | na | Data Area (SDA) | 99 +---------------+----------------+------------------------------+ 100 100 @end group 101 101 @end example … … 111 111 \hbox to 1.75in{\enskip\hfil#\hfil}& 112 112 \vrule#& 113 \hbox to 1.75in{\enskip\hfil#\hfil}&113 \hbox to 2.50in{\enskip\hfil#\hfil}& 114 114 \vrule#\cr 115 115 \noalign{\hrule} 116 116 &\bf Register Name &&\bf Alternate Names&&\bf Description&\cr\noalign{\hrule} 117 &g0&&NA&&reads return 0; &\cr 118 &&&&&writes are ignored&\cr\noalign{\hrule} 119 &o6&&sp&&stack pointer&\cr\noalign{\hrule} 120 &i6&&fp&&frame pointer&\cr\noalign{\hrule} 121 &i7&&NA&&return address&\cr\noalign{\hrule} 117 &r1&&sp&&stack pointer&\cr\noalign{\hrule} 118 &r2&&NA&&global pointer to the Small&\cr 119 &&&&&Constant Area (SDA2)&\cr\noalign{\hrule} 120 &r3 - r12&&NA&¶meter and result passing&\cr\noalign{\hrule} 121 &r13&&NA&&global pointer to the Small&\cr 122 &&&&&Data Area (SDA2)&\cr\noalign{\hrule} 122 123 }}\hfil} 123 124 @end tex … … 131 132 <TD ALIGN=center><STRONG>Alternate Name</STRONG></TD> 132 133 <TD ALIGN=center><STRONG>Description</STRONG></TD></TR> 133 <TR><TD ALIGN=center>g0</TD> 134 <TD ALIGN=center>NA</TD> 135 <TD ALIGN=center>reads return 0 ; writes are ignored</TD></TR> 136 <TR><TD ALIGN=center>o6</TD> 134 <TR><TD ALIGN=center>r1</TD> 137 135 <TD ALIGN=center>sp</TD> 138 136 <TD ALIGN=center>stack pointer</TD></TR> 139 <TR><TD ALIGN=center> i6</TD>140 <TD ALIGN=center> fp</TD>141 <TD ALIGN=center> frame pointer</TD></TR>142 <TR><TD ALIGN=center> i7</TD>137 <TR><TD ALIGN=center>r2</TD> 138 <TD ALIGN=center>na</TD> 139 <TD ALIGN=center>global pointer to the Small Constant Area (SDA2)</TD></TR> 140 <TR><TD ALIGN=center>r3 - r12</TD> 143 141 <TD ALIGN=center>NA</TD> 144 <TD ALIGN=center>return address</TD></TR> 142 <TD ALIGN=center>parameter and result passing</TD></TR> 143 <TR><TD ALIGN=center>r13</TD> 144 <TD ALIGN=center>NA</TD> 145 <TD ALIGN=center>global pointer to the Small Data Area (SDA)</TD></TR> 145 146 </TABLE> 146 147 </CENTER> … … 150 151 151 152 @ifinfo 152 @node Floating Point Registers, Special Registers,Non-Floating Point Registers, Calling Conventions Programming Model153 @node Calling Conventions Floating Point Registers, Calling Conventions Special Registers, Calling Conventions Non-Floating Point Registers, Calling Conventions Programming Model 153 154 @end ifinfo 154 155 @subsection Floating Point Registers 155 156 156 The PowerPC architecture includes thirty-two, 157 sixty-four bit registers. All PowwerPC floating point instructions158 interpret ethese registers as 32 double precision floating point registers,157 The PowerPC architecture includes thirty-two, sixty-four bit 158 floating point registers. All PowerPC floating point instructions 159 interpret these registers as 32 double precision floating point registers, 159 160 regardless of whether the processor has 64-bit or 32-bit implementation. 160 161 … … 164 165 reporting of floating exceptions to be enabled or disabled. 165 166 166 XXXXXX 167 A queue of the floating point instructions which have 168 started execution but not yet completed is maintained. This 169 queue is needed to support the multiple cycle nature of floating 170 point operations and to aid floating point exception trap 171 handlers. Once a floating point exception has been encountered, 172 the queue is frozen until it is emptied by the trap handler. 173 The floating point queue is loaded by launching instructions. 174 It is emptied normally when the floating point completes all 175 outstanding instructions and by floating point exception 176 handlers with the store double floating point queue (stdfq) 177 instruction. 178 XXX 179 180 @ifinfo 181 @node Special Registers, Calling Conventions Register Windows, Floating Point Registers, Calling Conventions Programming Model 167 @ifinfo 168 @node Calling Conventions Special Registers, Calling Conventions Call and Return Mechanism, Calling Conventions Floating Point Registers, Calling Conventions Programming Model 182 169 @end ifinfo 183 170 @subsection Special Registers 184 171 185 The PowerPC architecture includes XXX special registers 186 which are critical to the programming model: the Machine State 187 Register (msr) and XXX the Window Invalid Mask (wim) XXX. The msr 188 contains the processor mode, power management mode, endian mode, exception 189 information, privlige level, floating point available and floating point 190 excepiton mode, address translation information and the exception prefix. 191 192 XXX 193 condition codes, processor interrupt level, trap 194 enable bit, supervisor mode and previous supervisor mode bits, 195 version information, floating point unit and coprocessor enable 196 bits, and the current window pointer (cwp). The cwp field of 197 the psr and wim register are used to manage the register windows 198 in the SPARC architecture. The register windows are discussed 199 in more detail below. 200 XXX 201 202 @ifinfo 203 @node Calling Conventions Register Windows, Calling Conventions Call and Return Mechanism, Special Registers, Calling Conventions 204 @end ifinfo 205 @section Register Windows 206 207 The SPARC architecture includes the concept of 208 register windows. An overly simplistic way to think of these 209 windows is to imagine them as being an infinite supply of 210 "fresh" register sets available for each subroutine to use. In 211 reality, they are much more complicated. 212 213 The save instruction is used to obtain a new register 214 window. This instruction decrements the current window pointer, 215 thus providing a new set of registers for use. This register 216 set includes eight fresh local registers for use exclusively by 217 this subroutine. When done with a register set, the restore 218 instruction increments the current window pointer and the 219 previous register set is once again available. 220 221 The two primary issues complicating the use of 222 register windows are that (1) the set of register windows is 223 finite, and (2) some registers are shared between adjacent 224 registers windows. 225 226 Because the set of register windows is finite, it is 227 possible to execute enough save instructions without 228 corresponding restore's to consume all of the register windows. 229 This is easily accomplished in a high level language because 230 each subroutine typically performs a save instruction upon 231 entry. Thus having a subroutine call depth greater than the 232 number of register windows will result in a window overflow 233 condition. The window overflow condition generates a trap which 234 must be handled in software. The window overflow trap handler 235 is responsible for saving the contents of the oldest register 236 window on the program stack. 237 238 Similarly, the subroutines will eventually complete 239 and begin to perform restore's. If the restore results in the 240 need for a register window which has previously been written to 241 memory as part of an overflow, then a window underflow condition 242 results. Just like the window overflow, the window underflow 243 condition must be handled in software by a trap handler. The 244 window underflow trap handler is responsible for reloading the 245 contents of the register window requested by the restore 246 instruction from the program stack. 247 248 The Window Invalid Mask (wim) and the Current Window 249 Pointer (cwp) field in the psr are used in conjunction to manage 250 the finite set of register windows and detect the window 251 overflow and underflow conditions. The cwp contains the index 252 of the register window currently in use. The save instruction 253 decrements the cwp modulo the number of register windows. 254 Similarly, the restore instruction increments the cwp modulo the 255 number of register windows. Each bit in the wim represents 256 represents whether a register window contains valid information. 257 The value of 0 indicates the register window is valid and 1 258 indicates it is invalid. When a save instruction causes the cwp 259 to point to a register window which is marked as invalid, a 260 window overflow condition results. Conversely, the restore 261 instruction may result in a window underflow condition. 262 263 Other than the assumption that a register window is 264 always available for trap (i.e. interrupt) handlers, the SPARC 265 architecture places no limits on the number of register windows 266 simultaneously marked as invalid (i.e. number of bits set in the 267 wim). However, RTEMS assumes that only one register window is 268 marked invalid at a time (i.e. only one bit set in the wim). 269 This makes the maximum possible number of register windows 270 available to the user while still meeting the requirement that 271 window overflow and underflow conditions can be detected. 272 273 The window overflow and window underflow trap 274 handlers are a critical part of the run-time environment for a 275 SPARC application. The SPARC architectural specification allows 276 for the number of register windows to be any power of two less 277 than or equal to 32. The most common choice for SPARC 278 implementations appears to be 8 register windows. This results 279 in the cwp ranging in value from 0 to 7 on most implementations. 280 281 282 The second complicating factor is the sharing of 283 registers between adjacent register windows. While each 284 register window has its own set of local registers, the input 285 and output registers are shared between adjacent windows. The 286 output registers for register window N are the same as the input 287 registers for register window ((N - 1) modulo RW) where RW is 288 the number of register windows. An alternative way to think of 289 this is to remember how parameters are passed to a subroutine on 290 the SPARC. The caller loads values into what are its output 291 registers. Then after the callee executes a save instruction, 292 those parameters are available in its input registers. This is 293 a very efficient way to pass parameters as no data is actually 294 moved by the save or restore instructions. 295 296 @ifinfo 297 @node Calling Conventions Call and Return Mechanism, Calling Conventions Calling Mechanism, Calling Conventions Register Windows, Calling Conventions 172 The PowerPC architecture includes a number of special registers 173 which are critical to the programming model: 174 175 @table @b 176 177 @item Machine State Register 178 179 The MSR contains the processor mode, power management mode, endian mode, 180 exception information, privilege level, floating point available and 181 floating point excepiton mode, address translation information and 182 the exception prefix. 183 184 @item Link Register 185 186 The LR contains the return address after a function call. This register 187 must be saved before a subsequent subroutine call can be made. The 188 use of this register is discussed further in the @b{Call and Return 189 Mechanism} section below. 190 191 @item Count Register 192 193 The CTR contains the iteration variable for some loops. It may also be used 194 for indirect function calls and jumps. 195 196 @end table 197 198 @ifinfo 199 @node Calling Conventions Call and Return Mechanism, Calling Conventions Calling Mechanism, Calling Conventions Special Registers, Calling Conventions 298 200 @end ifinfo 299 201 @section Call and Return Mechanism 300 202 301 The SPARC architecture supports a simple yet 302 effective call and return mechanism. A subroutine is invoked 303 via the call (call) instruction. This instruction places the 304 return address in the caller's output register 7 (o7). After 305 the callee executes a save instruction, this value is available 306 in input register 7 (i7) until the corresponding restore 307 instruction is executed. 308 309 The callee returns to the caller via a jmp to the 310 return address. There is a delay slot following this 311 instruction which is commonly used to execute a restore 312 instruction -- if a register window was allocated by this 313 subroutine. 314 315 It is important to note that the SPARC subroutine 203 The PowerPC architecture supports a simple yet effective call 204 and return mechanism. A subroutine is invoked 205 via the "branch and link" (@code{bl}) and 206 "brank and link absolute" (@code{bla}) 207 instructions. This instructions place the return address 208 in the Link Register (LR). The callee returns to the caller by 209 executing a "branch unconditional to the link register" (@code{blr}) 210 instruction. Thus the callee returns to the caller via a jump 211 to the return address which is stored in the LR. 212 213 The previous contents of the LR are not automatically saved 214 by either the @code{bl} or @code{bla}. It is the responsibility 215 of the callee to save the contents of the LR before invoking 216 another subroutine. If the callee invokes another subroutine, 217 it must restore the LR before executing the @code{blr} instruction 218 to return to the caller. 219 220 It is important to note that the PowerPC subroutine 316 221 call and return mechanism does not automatically save and 317 restore any registers. This is accomplished via the save and 318 restore instructions which manage the set of registers windows. 222 restore any registers. 223 224 The LR may be accessed as special purpose register 8 (@code{SPR8}) using the 225 "move from special register" (@code{mfspr}) and 226 "move to special register" (@code{mtspr}) instructions. 319 227 320 228 @ifinfo … … 324 232 325 233 All RTEMS directives are invoked using the regular 326 SPARC calling convention via the call instruction. 234 PowerPC EABI calling convention via the @code{bl} or 235 @code{bla} instructions. 327 236 328 237 @ifinfo … … 332 241 333 242 As discussed above, the call instruction does not 334 automatically save any registers. The save and restore335 instructions are used to allocate and deallocate register 336 windows. When a register window is allocated, the new set of 337 local registers are available for the exclusive use of the 338 subroutine which allocated this register set.243 automatically save any registers. It is the responsibility 244 of the callee to save and restore any registers which must be preserved 245 across subroutine calls. The callee is responsible for saving 246 callee-preserved registers to the program stack and restoring them 247 before returning to the caller. 339 248 340 249 @ifinfo … … 344 253 345 254 RTEMS assumes that arguments are placed in the 346 caller's output registers with the first argument in output 347 register 0 (o0), the second argument in output register 1 (o1),348 and so forth. Until the callee executes a save instruction, the 349 parameters are still visible in the output registers. After the 350 callee executes a save instruction, the parameters are visible 351 in the corresponding input registers. The following pseudo-code255 general purpose registers with the first argument in 256 register 3 (@code{r3}), the second argument in general purpose 257 register 4 (@code{r4}), and so forth until the seventh 258 argument is in general purpose register 10 (@code{r10}). 259 If there are more than seven arguments, then subsequent arguments 260 are placed on the program stack. The following pseudo-code 352 261 illustrates the typical sequence used to call a RTEMS directive 353 262 with three (3) arguments: 354 263 355 264 @example 356 load third argument into o2357 load second argument into o1358 load first argument into o0265 load third argument into r5 266 load second argument into r4 267 load first argument into r3 359 268 invoke directive 360 269 @end example … … 367 276 All user-provided routines invoked by RTEMS, such as 368 277 user extensions, device drivers, and MPCI routines, must also 369 adhere to these calling conventions. 370 371 372 278 adhere to these same calling conventions. 279 280 -
doc/supplements/powerpc/callconv.texi
r84b0f7c9 r9aceddaf 8 8 9 9 @ifinfo 10 @node Calling Conventions, Calling Conventions Introduction, CPU Model Dependent Features CPU Model Implementation Notes, Top10 @node Calling Conventions, Calling Conventions Introduction, CPU Model Dependent Features Low Power Model, Top 11 11 @end ifinfo 12 12 @chapter Calling Conventions … … 15 15 * Calling Conventions Introduction:: 16 16 * Calling Conventions Programming Model:: 17 * Calling Conventions Register Windows::18 17 * Calling Conventions Call and Return Mechanism:: 19 18 * Calling Conventions Calling Mechanism:: … … 54 53 55 54 @ifinfo 56 @node Calling Conventions Programming Model, Non-Floating Point Registers, Calling Conventions Introduction, Calling Conventions55 @node Calling Conventions Programming Model, Calling Conventions Non-Floating Point Registers, Calling Conventions Introduction, Calling Conventions 57 56 @end ifinfo 58 57 @section Programming Model 59 58 @ifinfo 60 59 @menu 61 * Non-Floating Point Registers::62 * Floating Point Registers::63 * Special Registers::60 * Calling Conventions Non-Floating Point Registers:: 61 * Calling Conventions Floating Point Registers:: 62 * Calling Conventions Special Registers:: 64 63 @end menu 65 64 @end ifinfo … … 69 68 70 69 @ifinfo 71 @node Non-Floating Point Registers,Floating Point Registers, Calling Conventions Programming Model, Calling Conventions Programming Model70 @node Calling Conventions Non-Floating Point Registers, Calling Conventions Floating Point Registers, Calling Conventions Programming Model, Calling Conventions Programming Model 72 71 @end ifinfo 73 72 @subsection Non-Floating Point Registers … … 86 85 @example 87 86 @group 88 +---------------+----------------+----------------------+ 89 | Register Name | Alternate Name | Description | 90 +---------------+----------------+----------------------+ 91 | g0 | na | reads return 0 | 92 | | | writes are ignored | 93 +---------------+----------------+----------------------+ 94 | o6 | sp | stack pointer | 95 +---------------+----------------+----------------------+ 96 | i6 | fp | frame pointer | 97 +---------------+----------------+----------------------+ 98 | i7 | na | return address | 99 +---------------+----------------+----------------------+ 87 +---------------+----------------+------------------------------+ 88 | Register Name | Alternate Name | Description | 89 +---------------+----------------+------------------------------+ 90 | r1 | sp | stack pointer | 91 +---------------+----------------+------------------------------+ 92 | | | global pointer to the Small | 93 | r2 | na | Constant Area (SDA2) | 94 +---------------+----------------+------------------------------+ 95 | r3 - r12 | na | parameter and result passing | 96 +---------------+----------------+------------------------------+ 97 | | | global pointer to the Small | 98 | r13 | na | Data Area (SDA) | 99 +---------------+----------------+------------------------------+ 100 100 @end group 101 101 @end example … … 111 111 \hbox to 1.75in{\enskip\hfil#\hfil}& 112 112 \vrule#& 113 \hbox to 1.75in{\enskip\hfil#\hfil}&113 \hbox to 2.50in{\enskip\hfil#\hfil}& 114 114 \vrule#\cr 115 115 \noalign{\hrule} 116 116 &\bf Register Name &&\bf Alternate Names&&\bf Description&\cr\noalign{\hrule} 117 &g0&&NA&&reads return 0; &\cr 118 &&&&&writes are ignored&\cr\noalign{\hrule} 119 &o6&&sp&&stack pointer&\cr\noalign{\hrule} 120 &i6&&fp&&frame pointer&\cr\noalign{\hrule} 121 &i7&&NA&&return address&\cr\noalign{\hrule} 117 &r1&&sp&&stack pointer&\cr\noalign{\hrule} 118 &r2&&NA&&global pointer to the Small&\cr 119 &&&&&Constant Area (SDA2)&\cr\noalign{\hrule} 120 &r3 - r12&&NA&¶meter and result passing&\cr\noalign{\hrule} 121 &r13&&NA&&global pointer to the Small&\cr 122 &&&&&Data Area (SDA2)&\cr\noalign{\hrule} 122 123 }}\hfil} 123 124 @end tex … … 131 132 <TD ALIGN=center><STRONG>Alternate Name</STRONG></TD> 132 133 <TD ALIGN=center><STRONG>Description</STRONG></TD></TR> 133 <TR><TD ALIGN=center>g0</TD> 134 <TD ALIGN=center>NA</TD> 135 <TD ALIGN=center>reads return 0 ; writes are ignored</TD></TR> 136 <TR><TD ALIGN=center>o6</TD> 134 <TR><TD ALIGN=center>r1</TD> 137 135 <TD ALIGN=center>sp</TD> 138 136 <TD ALIGN=center>stack pointer</TD></TR> 139 <TR><TD ALIGN=center> i6</TD>140 <TD ALIGN=center> fp</TD>141 <TD ALIGN=center> frame pointer</TD></TR>142 <TR><TD ALIGN=center> i7</TD>137 <TR><TD ALIGN=center>r2</TD> 138 <TD ALIGN=center>na</TD> 139 <TD ALIGN=center>global pointer to the Small Constant Area (SDA2)</TD></TR> 140 <TR><TD ALIGN=center>r3 - r12</TD> 143 141 <TD ALIGN=center>NA</TD> 144 <TD ALIGN=center>return address</TD></TR> 142 <TD ALIGN=center>parameter and result passing</TD></TR> 143 <TR><TD ALIGN=center>r13</TD> 144 <TD ALIGN=center>NA</TD> 145 <TD ALIGN=center>global pointer to the Small Data Area (SDA)</TD></TR> 145 146 </TABLE> 146 147 </CENTER> … … 150 151 151 152 @ifinfo 152 @node Floating Point Registers, Special Registers,Non-Floating Point Registers, Calling Conventions Programming Model153 @node Calling Conventions Floating Point Registers, Calling Conventions Special Registers, Calling Conventions Non-Floating Point Registers, Calling Conventions Programming Model 153 154 @end ifinfo 154 155 @subsection Floating Point Registers 155 156 156 The PowerPC architecture includes thirty-two, 157 sixty-four bit registers. All PowwerPC floating point instructions158 interpret ethese registers as 32 double precision floating point registers,157 The PowerPC architecture includes thirty-two, sixty-four bit 158 floating point registers. All PowerPC floating point instructions 159 interpret these registers as 32 double precision floating point registers, 159 160 regardless of whether the processor has 64-bit or 32-bit implementation. 160 161 … … 164 165 reporting of floating exceptions to be enabled or disabled. 165 166 166 XXXXXX 167 A queue of the floating point instructions which have 168 started execution but not yet completed is maintained. This 169 queue is needed to support the multiple cycle nature of floating 170 point operations and to aid floating point exception trap 171 handlers. Once a floating point exception has been encountered, 172 the queue is frozen until it is emptied by the trap handler. 173 The floating point queue is loaded by launching instructions. 174 It is emptied normally when the floating point completes all 175 outstanding instructions and by floating point exception 176 handlers with the store double floating point queue (stdfq) 177 instruction. 178 XXX 179 180 @ifinfo 181 @node Special Registers, Calling Conventions Register Windows, Floating Point Registers, Calling Conventions Programming Model 167 @ifinfo 168 @node Calling Conventions Special Registers, Calling Conventions Call and Return Mechanism, Calling Conventions Floating Point Registers, Calling Conventions Programming Model 182 169 @end ifinfo 183 170 @subsection Special Registers 184 171 185 The PowerPC architecture includes XXX special registers 186 which are critical to the programming model: the Machine State 187 Register (msr) and XXX the Window Invalid Mask (wim) XXX. The msr 188 contains the processor mode, power management mode, endian mode, exception 189 information, privlige level, floating point available and floating point 190 excepiton mode, address translation information and the exception prefix. 191 192 XXX 193 condition codes, processor interrupt level, trap 194 enable bit, supervisor mode and previous supervisor mode bits, 195 version information, floating point unit and coprocessor enable 196 bits, and the current window pointer (cwp). The cwp field of 197 the psr and wim register are used to manage the register windows 198 in the SPARC architecture. The register windows are discussed 199 in more detail below. 200 XXX 201 202 @ifinfo 203 @node Calling Conventions Register Windows, Calling Conventions Call and Return Mechanism, Special Registers, Calling Conventions 204 @end ifinfo 205 @section Register Windows 206 207 The SPARC architecture includes the concept of 208 register windows. An overly simplistic way to think of these 209 windows is to imagine them as being an infinite supply of 210 "fresh" register sets available for each subroutine to use. In 211 reality, they are much more complicated. 212 213 The save instruction is used to obtain a new register 214 window. This instruction decrements the current window pointer, 215 thus providing a new set of registers for use. This register 216 set includes eight fresh local registers for use exclusively by 217 this subroutine. When done with a register set, the restore 218 instruction increments the current window pointer and the 219 previous register set is once again available. 220 221 The two primary issues complicating the use of 222 register windows are that (1) the set of register windows is 223 finite, and (2) some registers are shared between adjacent 224 registers windows. 225 226 Because the set of register windows is finite, it is 227 possible to execute enough save instructions without 228 corresponding restore's to consume all of the register windows. 229 This is easily accomplished in a high level language because 230 each subroutine typically performs a save instruction upon 231 entry. Thus having a subroutine call depth greater than the 232 number of register windows will result in a window overflow 233 condition. The window overflow condition generates a trap which 234 must be handled in software. The window overflow trap handler 235 is responsible for saving the contents of the oldest register 236 window on the program stack. 237 238 Similarly, the subroutines will eventually complete 239 and begin to perform restore's. If the restore results in the 240 need for a register window which has previously been written to 241 memory as part of an overflow, then a window underflow condition 242 results. Just like the window overflow, the window underflow 243 condition must be handled in software by a trap handler. The 244 window underflow trap handler is responsible for reloading the 245 contents of the register window requested by the restore 246 instruction from the program stack. 247 248 The Window Invalid Mask (wim) and the Current Window 249 Pointer (cwp) field in the psr are used in conjunction to manage 250 the finite set of register windows and detect the window 251 overflow and underflow conditions. The cwp contains the index 252 of the register window currently in use. The save instruction 253 decrements the cwp modulo the number of register windows. 254 Similarly, the restore instruction increments the cwp modulo the 255 number of register windows. Each bit in the wim represents 256 represents whether a register window contains valid information. 257 The value of 0 indicates the register window is valid and 1 258 indicates it is invalid. When a save instruction causes the cwp 259 to point to a register window which is marked as invalid, a 260 window overflow condition results. Conversely, the restore 261 instruction may result in a window underflow condition. 262 263 Other than the assumption that a register window is 264 always available for trap (i.e. interrupt) handlers, the SPARC 265 architecture places no limits on the number of register windows 266 simultaneously marked as invalid (i.e. number of bits set in the 267 wim). However, RTEMS assumes that only one register window is 268 marked invalid at a time (i.e. only one bit set in the wim). 269 This makes the maximum possible number of register windows 270 available to the user while still meeting the requirement that 271 window overflow and underflow conditions can be detected. 272 273 The window overflow and window underflow trap 274 handlers are a critical part of the run-time environment for a 275 SPARC application. The SPARC architectural specification allows 276 for the number of register windows to be any power of two less 277 than or equal to 32. The most common choice for SPARC 278 implementations appears to be 8 register windows. This results 279 in the cwp ranging in value from 0 to 7 on most implementations. 280 281 282 The second complicating factor is the sharing of 283 registers between adjacent register windows. While each 284 register window has its own set of local registers, the input 285 and output registers are shared between adjacent windows. The 286 output registers for register window N are the same as the input 287 registers for register window ((N - 1) modulo RW) where RW is 288 the number of register windows. An alternative way to think of 289 this is to remember how parameters are passed to a subroutine on 290 the SPARC. The caller loads values into what are its output 291 registers. Then after the callee executes a save instruction, 292 those parameters are available in its input registers. This is 293 a very efficient way to pass parameters as no data is actually 294 moved by the save or restore instructions. 295 296 @ifinfo 297 @node Calling Conventions Call and Return Mechanism, Calling Conventions Calling Mechanism, Calling Conventions Register Windows, Calling Conventions 172 The PowerPC architecture includes a number of special registers 173 which are critical to the programming model: 174 175 @table @b 176 177 @item Machine State Register 178 179 The MSR contains the processor mode, power management mode, endian mode, 180 exception information, privilege level, floating point available and 181 floating point excepiton mode, address translation information and 182 the exception prefix. 183 184 @item Link Register 185 186 The LR contains the return address after a function call. This register 187 must be saved before a subsequent subroutine call can be made. The 188 use of this register is discussed further in the @b{Call and Return 189 Mechanism} section below. 190 191 @item Count Register 192 193 The CTR contains the iteration variable for some loops. It may also be used 194 for indirect function calls and jumps. 195 196 @end table 197 198 @ifinfo 199 @node Calling Conventions Call and Return Mechanism, Calling Conventions Calling Mechanism, Calling Conventions Special Registers, Calling Conventions 298 200 @end ifinfo 299 201 @section Call and Return Mechanism 300 202 301 The SPARC architecture supports a simple yet 302 effective call and return mechanism. A subroutine is invoked 303 via the call (call) instruction. This instruction places the 304 return address in the caller's output register 7 (o7). After 305 the callee executes a save instruction, this value is available 306 in input register 7 (i7) until the corresponding restore 307 instruction is executed. 308 309 The callee returns to the caller via a jmp to the 310 return address. There is a delay slot following this 311 instruction which is commonly used to execute a restore 312 instruction -- if a register window was allocated by this 313 subroutine. 314 315 It is important to note that the SPARC subroutine 203 The PowerPC architecture supports a simple yet effective call 204 and return mechanism. A subroutine is invoked 205 via the "branch and link" (@code{bl}) and 206 "brank and link absolute" (@code{bla}) 207 instructions. This instructions place the return address 208 in the Link Register (LR). The callee returns to the caller by 209 executing a "branch unconditional to the link register" (@code{blr}) 210 instruction. Thus the callee returns to the caller via a jump 211 to the return address which is stored in the LR. 212 213 The previous contents of the LR are not automatically saved 214 by either the @code{bl} or @code{bla}. It is the responsibility 215 of the callee to save the contents of the LR before invoking 216 another subroutine. If the callee invokes another subroutine, 217 it must restore the LR before executing the @code{blr} instruction 218 to return to the caller. 219 220 It is important to note that the PowerPC subroutine 316 221 call and return mechanism does not automatically save and 317 restore any registers. This is accomplished via the save and 318 restore instructions which manage the set of registers windows. 222 restore any registers. 223 224 The LR may be accessed as special purpose register 8 (@code{SPR8}) using the 225 "move from special register" (@code{mfspr}) and 226 "move to special register" (@code{mtspr}) instructions. 319 227 320 228 @ifinfo … … 324 232 325 233 All RTEMS directives are invoked using the regular 326 SPARC calling convention via the call instruction. 234 PowerPC EABI calling convention via the @code{bl} or 235 @code{bla} instructions. 327 236 328 237 @ifinfo … … 332 241 333 242 As discussed above, the call instruction does not 334 automatically save any registers. The save and restore335 instructions are used to allocate and deallocate register 336 windows. When a register window is allocated, the new set of 337 local registers are available for the exclusive use of the 338 subroutine which allocated this register set.243 automatically save any registers. It is the responsibility 244 of the callee to save and restore any registers which must be preserved 245 across subroutine calls. The callee is responsible for saving 246 callee-preserved registers to the program stack and restoring them 247 before returning to the caller. 339 248 340 249 @ifinfo … … 344 253 345 254 RTEMS assumes that arguments are placed in the 346 caller's output registers with the first argument in output 347 register 0 (o0), the second argument in output register 1 (o1),348 and so forth. Until the callee executes a save instruction, the 349 parameters are still visible in the output registers. After the 350 callee executes a save instruction, the parameters are visible 351 in the corresponding input registers. The following pseudo-code255 general purpose registers with the first argument in 256 register 3 (@code{r3}), the second argument in general purpose 257 register 4 (@code{r4}), and so forth until the seventh 258 argument is in general purpose register 10 (@code{r10}). 259 If there are more than seven arguments, then subsequent arguments 260 are placed on the program stack. The following pseudo-code 352 261 illustrates the typical sequence used to call a RTEMS directive 353 262 with three (3) arguments: 354 263 355 264 @example 356 load third argument into o2357 load second argument into o1358 load first argument into o0265 load third argument into r5 266 load second argument into r4 267 load first argument into r3 359 268 invoke directive 360 269 @end example … … 367 276 All user-provided routines invoked by RTEMS, such as 368 277 user extensions, device drivers, and MPCI routines, must also 369 adhere to these calling conventions. 370 371 372 278 adhere to these same calling conventions. 279 280 -
doc/supplements/powerpc/cpumodel.t
r84b0f7c9 r9aceddaf 15 15 * CPU Model Dependent Features Introduction:: 16 16 * CPU Model Dependent Features CPU Model Feature Flags:: 17 * CPU Model Dependent Features CPU Model Implementation Notes::18 17 @end menu 19 18 @end ifinfo … … 56 55 * CPU Model Dependent Features Has Double Precision Floating Point:: 57 56 * CPU Model Dependent Features Critical Interrupts:: 58 * CPU Model Dependent Features MSR Values::59 57 * CPU Model Dependent Features Use Multiword Load/Store Instructions:: 60 58 * CPU Model Dependent Features Instruction Cache Size:: … … 147 145 148 146 @ifinfo 149 @node CPU Model Dependent Features Critical Interrupts, CPU Model Dependent Features MSR Values, CPU Model Dependent Features Has Double Precision Floating Point, CPU Model Dependent Features CPU Model Feature Flags147 @node CPU Model Dependent Features Critical Interrupts, CPU Model Dependent Features Use Multiword Load/Store Instructions, CPU Model Dependent Features Has Double Precision Floating Point, CPU Model Dependent Features CPU Model Feature Flags 150 148 @end ifinfo 151 149 @subsection Critical Interrupts … … 155 153 156 154 @ifinfo 157 @node CPU Model Dependent Features MSR Values, CPU Model Dependent Features Use Multiword Load/Store Instructions, CPU Model Dependent Features Critical Interrupts, CPU Model Dependent Features CPU Model Feature Flags 158 @end ifinfo 159 @subsection MSR Values 160 161 The macro PPC_MSR_INITIAL is set to 162 163 @ifinfo 164 @node CPU Model Dependent Features Use Multiword Load/Store Instructions, CPU Model Dependent Features Instruction Cache Size, CPU Model Dependent Features MSR Values, CPU Model Dependent Features CPU Model Feature Flags 155 @node CPU Model Dependent Features Use Multiword Load/Store Instructions, CPU Model Dependent Features Instruction Cache Size, CPU Model Dependent Features Critical Interrupts, CPU Model Dependent Features CPU Model Feature Flags 165 156 @end ifinfo 166 157 @subsection Use Multiword Load/Store Instructions … … 191 182 @subsection Debug Model 192 183 193 The macro PPC_DEBUG_MODEL 184 The macro PPC_DEBUG_MODEL is set to indicate the debug support features 185 present in this CPU model. The following debug support feature sets 186 are currently supported: 194 187 195 188 @table @b 196 189 197 190 @item @code{PPC_DEBUG_MODEL_STANDARD} 198 indicates XXX 191 indicates that the single-step trace enable (SE) and branch trace 192 enable (BE) bits in the MSR are supported by this CPU model. 199 193 200 194 @item @code{PPC_DEBUG_MODEL_SINGLE_STEP_ONLY} 201 indicates XXX 195 indicates that only the single-step trace enable (SE) bit in the MSR 196 is supported by this CPU model. 202 197 203 198 @item @code{PPC_DEBUG_MODEL_IBM4xx} 204 indicates XXX 199 indicates that the debug exception enable (DE) bit in the MSR is supported 200 by this CPU model. At this time, this particular debug feature set 201 has only been seen in the IBM 4xx series. 205 202 206 203 @end table 207 204 208 205 @ifinfo 209 @node CPU Model Dependent Features Low Power Model, C PU Model Dependent Features CPU Model Implementation Notes, CPU Model Dependent Features Debug Model, CPU Model Dependent Features CPU Model Feature Flags206 @node CPU Model Dependent Features Low Power Model, Calling Conventions, CPU Model Dependent Features Debug Model, CPU Model Dependent Features CPU Model Feature Flags 210 207 @end ifinfo 211 208 @subsection Low Power Model 212 209 213 The macro PPC_LOW_POWER_MODE 210 The macro PPC_LOW_POWER_MODE is set to indicate the low power model 211 supported by this CPU model. The following low power modes are currently 212 supported. 214 213 215 214 @table @b 216 215 217 216 @item @code{PPC_LOW_POWER_MODE_NONE} 218 indicates XXX217 indicates that this CPU model has no low power mode support. 219 218 220 219 @item @code{PPC_LOW_POWER_MODE_STANDARD} 221 indicates XXX 220 indicates that this CPU model follows the low power model defined for 221 the PPC603e. 222 222 223 223 @end table 224 225 226 @ifinfo227 @node CPU Model Dependent Features CPU Model Implementation Notes, Calling Conventions, CPU Model Dependent Features Low Power Model, CPU Model Dependent Features228 @end ifinfo229 @section CPU Model Implementation Notes230 231 TBD -
doc/supplements/powerpc/cpumodel.texi
r84b0f7c9 r9aceddaf 15 15 * CPU Model Dependent Features Introduction:: 16 16 * CPU Model Dependent Features CPU Model Feature Flags:: 17 * CPU Model Dependent Features CPU Model Implementation Notes::18 17 @end menu 19 18 @end ifinfo … … 56 55 * CPU Model Dependent Features Has Double Precision Floating Point:: 57 56 * CPU Model Dependent Features Critical Interrupts:: 58 * CPU Model Dependent Features MSR Values::59 57 * CPU Model Dependent Features Use Multiword Load/Store Instructions:: 60 58 * CPU Model Dependent Features Instruction Cache Size:: … … 147 145 148 146 @ifinfo 149 @node CPU Model Dependent Features Critical Interrupts, CPU Model Dependent Features MSR Values, CPU Model Dependent Features Has Double Precision Floating Point, CPU Model Dependent Features CPU Model Feature Flags147 @node CPU Model Dependent Features Critical Interrupts, CPU Model Dependent Features Use Multiword Load/Store Instructions, CPU Model Dependent Features Has Double Precision Floating Point, CPU Model Dependent Features CPU Model Feature Flags 150 148 @end ifinfo 151 149 @subsection Critical Interrupts … … 155 153 156 154 @ifinfo 157 @node CPU Model Dependent Features MSR Values, CPU Model Dependent Features Use Multiword Load/Store Instructions, CPU Model Dependent Features Critical Interrupts, CPU Model Dependent Features CPU Model Feature Flags 158 @end ifinfo 159 @subsection MSR Values 160 161 The macro PPC_MSR_INITIAL is set to 162 163 @ifinfo 164 @node CPU Model Dependent Features Use Multiword Load/Store Instructions, CPU Model Dependent Features Instruction Cache Size, CPU Model Dependent Features MSR Values, CPU Model Dependent Features CPU Model Feature Flags 155 @node CPU Model Dependent Features Use Multiword Load/Store Instructions, CPU Model Dependent Features Instruction Cache Size, CPU Model Dependent Features Critical Interrupts, CPU Model Dependent Features CPU Model Feature Flags 165 156 @end ifinfo 166 157 @subsection Use Multiword Load/Store Instructions … … 191 182 @subsection Debug Model 192 183 193 The macro PPC_DEBUG_MODEL 184 The macro PPC_DEBUG_MODEL is set to indicate the debug support features 185 present in this CPU model. The following debug support feature sets 186 are currently supported: 194 187 195 188 @table @b 196 189 197 190 @item @code{PPC_DEBUG_MODEL_STANDARD} 198 indicates XXX 191 indicates that the single-step trace enable (SE) and branch trace 192 enable (BE) bits in the MSR are supported by this CPU model. 199 193 200 194 @item @code{PPC_DEBUG_MODEL_SINGLE_STEP_ONLY} 201 indicates XXX 195 indicates that only the single-step trace enable (SE) bit in the MSR 196 is supported by this CPU model. 202 197 203 198 @item @code{PPC_DEBUG_MODEL_IBM4xx} 204 indicates XXX 199 indicates that the debug exception enable (DE) bit in the MSR is supported 200 by this CPU model. At this time, this particular debug feature set 201 has only been seen in the IBM 4xx series. 205 202 206 203 @end table 207 204 208 205 @ifinfo 209 @node CPU Model Dependent Features Low Power Model, C PU Model Dependent Features CPU Model Implementation Notes, CPU Model Dependent Features Debug Model, CPU Model Dependent Features CPU Model Feature Flags206 @node CPU Model Dependent Features Low Power Model, Calling Conventions, CPU Model Dependent Features Debug Model, CPU Model Dependent Features CPU Model Feature Flags 210 207 @end ifinfo 211 208 @subsection Low Power Model 212 209 213 The macro PPC_LOW_POWER_MODE 210 The macro PPC_LOW_POWER_MODE is set to indicate the low power model 211 supported by this CPU model. The following low power modes are currently 212 supported. 214 213 215 214 @table @b 216 215 217 216 @item @code{PPC_LOW_POWER_MODE_NONE} 218 indicates XXX217 indicates that this CPU model has no low power mode support. 219 218 220 219 @item @code{PPC_LOW_POWER_MODE_STANDARD} 221 indicates XXX 220 indicates that this CPU model follows the low power model defined for 221 the PPC603e. 222 222 223 223 @end table 224 225 226 @ifinfo227 @node CPU Model Dependent Features CPU Model Implementation Notes, Calling Conventions, CPU Model Dependent Features Low Power Model, CPU Model Dependent Features228 @end ifinfo229 @section CPU Model Implementation Notes230 231 TBD -
doc/supplements/powerpc/cputable.t
r84b0f7c9 r9aceddaf 51 51 /* end of fields required on all CPUs */ 52 52 53 unsigned32 clicks_per_usec; /* Timer clicks per microsecond */53 unsigned32 clicks_per_usec; /* Timer clicks per microsecond */ 54 54 void (*spurious_handler)(unsigned32 vector, CPU_Interrupt_frame *); 55 55 boolean exceptions_in_RAM; /* TRUE if in RAM */ 56 unsigned32 serial_per_sec; /* Serial clocks per second */ 56 57 #if defined(ppc403) 58 unsigned32 serial_per_sec; /* Serial clocks per second */ 57 59 boolean serial_external_clock; 58 60 boolean serial_xon_xoff; 59 61 boolean serial_cts_rts; 60 62 unsigned32 serial_rate; 61 unsigned32 timer_average_overhead; /* Average overhead of timer in ticks */ 62 unsigned32 timer_least_valid; /* Least valid number from timer */ 63 void (*spurious_handler)(unsigned32 vector, CPU_Interrupt_frame *); 64 63 unsigned32 timer_average_overhead; /* in ticks */ 64 unsigned32 timer_least_valid; /* Least valid number from timer */ 65 #endif 65 66 @}; 66 67 @end example … … 133 134 134 135 @item serial_per_sec 135 is the number of clock ticks per second for the PPC403 serial timer. 136 is a PPC403 specific field which specifies the number of clock 137 ticks per second for the PPC403 serial timer. 136 138 137 139 @item serial_rate 138 is the baud rate for the PPC403 serial timer. 140 is a PPC403 specific field which specifies the baud rate for the 141 PPC403 serial port. 139 142 140 143 @item serial_external_clock 141 is a flag used by the BSP to indicatewhether or not to mask in a 0x2 into144 is a PPC403 specific field which indicates whether or not to mask in a 0x2 into 142 145 the Input/Output Configuration Register (IOCR) during initialization of the 143 PPC403 console. XXX This bit is defined as "reserved" 6-12?146 PPC403 console. (NOTE: This bit is defined as "reserved" 6-12?) 144 147 145 148 @item serial_xon_xoff 146 is a flag used by the BSP to indicate whether or not XON/XOFF flow control147 is supported for the PPC403 serial timer.149 is a PPC403 specific field which indicates whether or not 150 XON/XOFF flow control is supported for the PPC403 serial port. 148 151 149 152 @item serial_cts_rts 150 is a flag used by the BSP to indicate whether or not to set the lsb ofthe151 Input/Output Configuration Register (IOCR) during initialization of the 152 PPC403 console. XXX This bit is defined as "reserved" 6-12? 153 153 is a PPC403 specific field which indicates whether or not to set the 154 least significant bit of the Input/Output Configuration Register 155 (IOCR) during initialization of the PPC403 console. (NOTE: This 156 bit is defined as "reserved" 6-12?) 154 157 155 158 @item timer_average_overhead 156 is the average number of overhead ticks that occur on the PPC403 timer.159 is a PPC403 specific field which specifies the average number of overhead ticks that occur on the PPC403 timer. 157 160 158 161 @item timer_least_valid 159 is the maximum valid PPC403 timer value.162 is a PPC403 specific field which specifies the maximum valid PPC403 timer value. 160 163 161 164 @end table -
doc/supplements/powerpc/cputable.texi
r84b0f7c9 r9aceddaf 51 51 /* end of fields required on all CPUs */ 52 52 53 unsigned32 clicks_per_usec; /* Timer clicks per microsecond */53 unsigned32 clicks_per_usec; /* Timer clicks per microsecond */ 54 54 void (*spurious_handler)(unsigned32 vector, CPU_Interrupt_frame *); 55 55 boolean exceptions_in_RAM; /* TRUE if in RAM */ 56 unsigned32 serial_per_sec; /* Serial clocks per second */ 56 57 #if defined(ppc403) 58 unsigned32 serial_per_sec; /* Serial clocks per second */ 57 59 boolean serial_external_clock; 58 60 boolean serial_xon_xoff; 59 61 boolean serial_cts_rts; 60 62 unsigned32 serial_rate; 61 unsigned32 timer_average_overhead; /* Average overhead of timer in ticks */ 62 unsigned32 timer_least_valid; /* Least valid number from timer */ 63 void (*spurious_handler)(unsigned32 vector, CPU_Interrupt_frame *); 64 63 unsigned32 timer_average_overhead; /* in ticks */ 64 unsigned32 timer_least_valid; /* Least valid number from timer */ 65 #endif 65 66 @}; 66 67 @end example … … 133 134 134 135 @item serial_per_sec 135 is the number of clock ticks per second for the PPC403 serial timer. 136 is a PPC403 specific field which specifies the number of clock 137 ticks per second for the PPC403 serial timer. 136 138 137 139 @item serial_rate 138 is the baud rate for the PPC403 serial timer. 140 is a PPC403 specific field which specifies the baud rate for the 141 PPC403 serial port. 139 142 140 143 @item serial_external_clock 141 is a flag used by the BSP to indicatewhether or not to mask in a 0x2 into144 is a PPC403 specific field which indicates whether or not to mask in a 0x2 into 142 145 the Input/Output Configuration Register (IOCR) during initialization of the 143 PPC403 console. XXX This bit is defined as "reserved" 6-12?146 PPC403 console. (NOTE: This bit is defined as "reserved" 6-12?) 144 147 145 148 @item serial_xon_xoff 146 is a flag used by the BSP to indicate whether or not XON/XOFF flow control147 is supported for the PPC403 serial timer.149 is a PPC403 specific field which indicates whether or not 150 XON/XOFF flow control is supported for the PPC403 serial port. 148 151 149 152 @item serial_cts_rts 150 is a flag used by the BSP to indicate whether or not to set the lsb ofthe151 Input/Output Configuration Register (IOCR) during initialization of the 152 PPC403 console. XXX This bit is defined as "reserved" 6-12? 153 153 is a PPC403 specific field which indicates whether or not to set the 154 least significant bit of the Input/Output Configuration Register 155 (IOCR) during initialization of the PPC403 console. (NOTE: This 156 bit is defined as "reserved" 6-12?) 154 157 155 158 @item timer_average_overhead 156 is the average number of overhead ticks that occur on the PPC403 timer.159 is a PPC403 specific field which specifies the average number of overhead ticks that occur on the PPC403 timer. 157 160 158 161 @item timer_least_valid 159 is the maximum valid PPC403 timer value.162 is a PPC403 specific field which specifies the maximum valid PPC403 timer value. 160 163 161 164 @end table -
doc/supplements/powerpc/fatalerr.t
r84b0f7c9 r9aceddaf 39 39 40 40 The default fatal error handler which is invoked by 41 the fatal_error_occurreddirective when there is no user handler41 the @code{rtems_fatal_error_occurred} directive when there is no user handler 42 42 configured or the user handler returns control to RTEMS. The 43 default fatal error handler disables all processor exceptions, 44 places the error code in r5, and goes into an infinite 45 loop to simulate a halt processor instruction. 43 default fatal error handler performs the following actions: 46 44 45 @itemize @bullet 46 47 @item places the error code in r3, and 48 49 @item executes a trap instruction which results in a Program Exception. 50 51 @end itemize 52 53 If the Program Exception returns, then the following actions are performed: 54 55 @itemize @bullet 56 57 @item disables all processor exceptions by loading a 0 into the MSR, and 58 59 @item goes into an infinite loop to simulate a halt processor instruction. 60 61 @end itemize 62 -
doc/supplements/powerpc/fatalerr.texi
r84b0f7c9 r9aceddaf 39 39 40 40 The default fatal error handler which is invoked by 41 the fatal_error_occurreddirective when there is no user handler41 the @code{rtems_fatal_error_occurred} directive when there is no user handler 42 42 configured or the user handler returns control to RTEMS. The 43 default fatal error handler disables all processor exceptions, 44 places the error code in r5, and goes into an infinite 45 loop to simulate a halt processor instruction. 43 default fatal error handler performs the following actions: 46 44 45 @itemize @bullet 46 47 @item places the error code in r3, and 48 49 @item executes a trap instruction which results in a Program Exception. 50 51 @end itemize 52 53 If the Program Exception returns, then the following actions are performed: 54 55 @itemize @bullet 56 57 @item disables all processor exceptions by loading a 0 into the MSR, and 58 59 @item goes into an infinite loop to simulate a halt processor instruction. 60 61 @end itemize 62 -
doc/supplements/powerpc/intr.t
r84b0f7c9 r9aceddaf 38 38 details of interrupt processing, it is important to understand 39 39 how the RTEMS interrupt manager is mapped onto the processor's 40 unique architecture. Discussed in this chapter are the P PC's40 unique architecture. Discussed in this chapter are the PowerPC's 41 41 interrupt response and control mechanisms as they pertain to 42 42 RTEMS. 43 43 44 44 RTEMS and associated documentation uses the terms 45 interrupt and vector. In the P PC architecture, these terms45 interrupt and vector. In the PowerPC architecture, these terms 46 46 correspond to exception and exception handler, respectively. The terms will 47 47 be used interchangeably in this manual. … … 52 52 @section Synchronous Versus Asynchronous Exceptions 53 53 54 In the P PC architecture exceptions can be either precise or54 In the PowerPC architecture exceptions can be either precise or 55 55 imprecise and either synchronous or asynchronous. Asynchronous 56 56 exceptions occur when an external event interrupts the processor. … … 78 78 @section Vectoring of Interrupt Handler 79 79 80 Upon determining that an exception can be taken the P PCautomatically80 Upon determining that an exception can be taken the PowerPC automatically 81 81 performs the following actions: 82 82 … … 95 95 96 96 @end itemize 97 98 97 99 98 If the interrupt handler was installed as an RTEMS … … 105 104 @item saves the state of the interrupted task on it's stack, 106 105 107 @item insures that a register window is available for 108 subsequent exceptions, 106 @item saves all registers which are not normally preserved 107 by the calling sequence so the user's interrupt service 108 routine can be written in a high-level language. 109 109 110 110 @item if this is the outermost (i.e. non-nested) interrupt, … … 118 118 119 119 Asynchronous interrupts are ignored while exceptions are 120 disabled. Synchronous interrupts which occur while 120 disabled. Synchronous interrupts which occur while are 121 121 disabled result in the CPU being forced into an error mode. 122 122 … … 130 130 @section Interrupt Levels 131 131 132 TBD levels (0-TBD) of interrupt priorities are 133 supported by the PowerPC architecture with level TBD (TBD) 134 being the highest priority. Level zero (0) indicates that 135 interrupts are fully enabled. Interrupt requests for interrupts 136 with priorities less than or equal to the current interrupt mask 137 level are ignored. 138 139 TBD 140 All other RTEMS interrupt levels are undefined and their behavior is 141 unpredictable. 132 The PowerPC architecture supports only a single external 133 asynchronous interrupt source. This interrupt source 134 may be enabled and disabled via the External Interrupt Enable (EE) 135 bit in the Machine State Register (MSR). Thus only two level (enabled 136 and disabled) of external device interrupt priorities are 137 directly supported by the PowerPC architecture. 138 139 Some PowerPC implementations include a Critical Interrupt capability 140 which is often used to receive interrupts from high priority external 141 devices. 142 143 The RTEMS interrupt level mapping scheme for the PowerPC is not 144 a numeric level as on most RTEMS ports. It is a bit mapping in 145 which the least three significiant bits of the interrupt level 146 are mapped directly to the enabling of specific interrupt 147 sources as follows: 148 149 @table @b 150 151 @item Critical Interrupt 152 Setting bit 0 (the least significant bit) of the interrupt level 153 enables the Critical Interrupt source, if it is available on this 154 CPU model. 155 156 @item Machine Check 157 Setting bit 1 of the interrupt level enables Machine Check execptions. 158 159 @item External Interrupt 160 Setting bit 2 of the interrupt level enables External Interrupt execptions. 161 162 @end table 163 164 All other bits in the RTEMS task interrupt level are ignored. 142 165 143 166 @ifinfo … … 148 171 During the execution of directive calls, critical 149 172 sections of code may be executed. When these sections are 150 encountered, RTEMS disables interrupts to level TBD (TBD)151 before the execution of this section and restores them to the 152 previous level upon completion of the section. RTEMS has been173 encountered, RTEMS disables Critical Interrupts, External Interrupts 174 and Machine Checks before the execution of this section and restores 175 them to the previous level upon completion of the section. RTEMS has been 153 176 optimized to insure that interrupts are disabled for less than 154 177 RTEMS_MAXIMUM_DISABLE_PERIOD microseconds on a … … 160 183 RTEMS_RELEASE_FOR_MAXIMUM_DISABLE_PERIOD.] 161 184 162 [NOTE: It is thought that the length of time at which 163 the processor interrupt level is elevated to fifteen by RTEMS is 164 not anywhere near as long as the length of time ALL exceptions are 165 disabled as part of the "flush all register windows" operation.] 166 167 Non-maskable interrupts (NMI) cannot be disabled, and 168 ISRs which execute at this level MUST NEVER issue RTEMS system 169 calls. If a directive is invoked, unpredictable results may 170 occur due to the inability of RTEMS to protect its critical 171 sections. However, ISRs that make no system calls may safely 172 execute as non-maskable interrupts. 185 If a PowerPC implementation provides non-maskable interrupts (NMI) 186 which cannot be disabled, ISRs which process these interrupts 187 MUST NEVER issue RTEMS system calls. If a directive is invoked, 188 unpredictable results may occur due to the inability of RTEMS 189 to protect its critical sections. However, ISRs that make no 190 system calls may safely execute as non-maskable interrupts. 173 191 174 192 @ifinfo -
doc/supplements/powerpc/intr_NOTIMES.t
r84b0f7c9 r9aceddaf 38 38 details of interrupt processing, it is important to understand 39 39 how the RTEMS interrupt manager is mapped onto the processor's 40 unique architecture. Discussed in this chapter are the P PC's40 unique architecture. Discussed in this chapter are the PowerPC's 41 41 interrupt response and control mechanisms as they pertain to 42 42 RTEMS. 43 43 44 44 RTEMS and associated documentation uses the terms 45 interrupt and vector. In the P PC architecture, these terms45 interrupt and vector. In the PowerPC architecture, these terms 46 46 correspond to exception and exception handler, respectively. The terms will 47 47 be used interchangeably in this manual. … … 52 52 @section Synchronous Versus Asynchronous Exceptions 53 53 54 In the P PC architecture exceptions can be either precise or54 In the PowerPC architecture exceptions can be either precise or 55 55 imprecise and either synchronous or asynchronous. Asynchronous 56 56 exceptions occur when an external event interrupts the processor. … … 78 78 @section Vectoring of Interrupt Handler 79 79 80 Upon determining that an exception can be taken the P PCautomatically80 Upon determining that an exception can be taken the PowerPC automatically 81 81 performs the following actions: 82 82 … … 95 95 96 96 @end itemize 97 98 97 99 98 If the interrupt handler was installed as an RTEMS … … 105 104 @item saves the state of the interrupted task on it's stack, 106 105 107 @item insures that a register window is available for 108 subsequent exceptions, 106 @item saves all registers which are not normally preserved 107 by the calling sequence so the user's interrupt service 108 routine can be written in a high-level language. 109 109 110 110 @item if this is the outermost (i.e. non-nested) interrupt, … … 118 118 119 119 Asynchronous interrupts are ignored while exceptions are 120 disabled. Synchronous interrupts which occur while 120 disabled. Synchronous interrupts which occur while are 121 121 disabled result in the CPU being forced into an error mode. 122 122 … … 130 130 @section Interrupt Levels 131 131 132 TBD levels (0-TBD) of interrupt priorities are 133 supported by the PowerPC architecture with level TBD (TBD) 134 being the highest priority. Level zero (0) indicates that 135 interrupts are fully enabled. Interrupt requests for interrupts 136 with priorities less than or equal to the current interrupt mask 137 level are ignored. 138 139 TBD 140 All other RTEMS interrupt levels are undefined and their behavior is 141 unpredictable. 132 The PowerPC architecture supports only a single external 133 asynchronous interrupt source. This interrupt source 134 may be enabled and disabled via the External Interrupt Enable (EE) 135 bit in the Machine State Register (MSR). Thus only two level (enabled 136 and disabled) of external device interrupt priorities are 137 directly supported by the PowerPC architecture. 138 139 Some PowerPC implementations include a Critical Interrupt capability 140 which is often used to receive interrupts from high priority external 141 devices. 142 143 The RTEMS interrupt level mapping scheme for the PowerPC is not 144 a numeric level as on most RTEMS ports. It is a bit mapping in 145 which the least three significiant bits of the interrupt level 146 are mapped directly to the enabling of specific interrupt 147 sources as follows: 148 149 @table @b 150 151 @item Critical Interrupt 152 Setting bit 0 (the least significant bit) of the interrupt level 153 enables the Critical Interrupt source, if it is available on this 154 CPU model. 155 156 @item Machine Check 157 Setting bit 1 of the interrupt level enables Machine Check execptions. 158 159 @item External Interrupt 160 Setting bit 2 of the interrupt level enables External Interrupt execptions. 161 162 @end table 163 164 All other bits in the RTEMS task interrupt level are ignored. 142 165 143 166 @ifinfo … … 148 171 During the execution of directive calls, critical 149 172 sections of code may be executed. When these sections are 150 encountered, RTEMS disables interrupts to level TBD (TBD)151 before the execution of this section and restores them to the 152 previous level upon completion of the section. RTEMS has been173 encountered, RTEMS disables Critical Interrupts, External Interrupts 174 and Machine Checks before the execution of this section and restores 175 them to the previous level upon completion of the section. RTEMS has been 153 176 optimized to insure that interrupts are disabled for less than 154 177 RTEMS_MAXIMUM_DISABLE_PERIOD microseconds on a … … 160 183 RTEMS_RELEASE_FOR_MAXIMUM_DISABLE_PERIOD.] 161 184 162 [NOTE: It is thought that the length of time at which 163 the processor interrupt level is elevated to fifteen by RTEMS is 164 not anywhere near as long as the length of time ALL exceptions are 165 disabled as part of the "flush all register windows" operation.] 166 167 Non-maskable interrupts (NMI) cannot be disabled, and 168 ISRs which execute at this level MUST NEVER issue RTEMS system 169 calls. If a directive is invoked, unpredictable results may 170 occur due to the inability of RTEMS to protect its critical 171 sections. However, ISRs that make no system calls may safely 172 execute as non-maskable interrupts. 185 If a PowerPC implementation provides non-maskable interrupts (NMI) 186 which cannot be disabled, ISRs which process these interrupts 187 MUST NEVER issue RTEMS system calls. If a directive is invoked, 188 unpredictable results may occur due to the inability of RTEMS 189 to protect its critical sections. However, ISRs that make no 190 system calls may safely execute as non-maskable interrupts. 173 191 174 192 @ifinfo -
doc/supplements/powerpc/memmodel.t
r84b0f7c9 r9aceddaf 42 42 converts every address from a logical to a physical address 43 43 each time it is used. The PowerPC uses information provided 44 in the XXXto convert these addresses.44 in the Block Address Translation (BAT) to convert these addresses. 45 45 46 46 Implementations of the PowerPC architecture may be thirty-two or sixty-four bit. … … 120 120 PowerPC CPU models which are sixty-four bit implementations. 121 121 122 RTEMS does not directly support any PowerPC 122 RTEMS does not directly support any PowerPC Memory Management 123 123 Units, therefore, virtual memory or segmentation systems 124 124 involving the PowerPC are not supported. -
doc/supplements/powerpc/memmodel.texi
r84b0f7c9 r9aceddaf 42 42 converts every address from a logical to a physical address 43 43 each time it is used. The PowerPC uses information provided 44 in the XXXto convert these addresses.44 in the Block Address Translation (BAT) to convert these addresses. 45 45 46 46 Implementations of the PowerPC architecture may be thirty-two or sixty-four bit. … … 120 120 PowerPC CPU models which are sixty-four bit implementations. 121 121 122 RTEMS does not directly support any PowerPC 122 RTEMS does not directly support any PowerPC Memory Management 123 123 Units, therefore, virtual memory or segmentation systems 124 124 involving the PowerPC are not supported. -
doc/supplements/powerpc/preface.texi
r84b0f7c9 r9aceddaf 34 34 35 35 For information on the PowerPC architecture, refer to 36 the following documents available from Motorola 37 (http://www.moto.com): 36 the following documents available from Motorola and IBM: 38 37 39 38 @itemize @bullet 40 @item some PowerPC document shere 39 40 @item @cite{PowerPC Microprocessor Family: The Programming Environment} 41 (Motorola Document MPRPPCFPE-01). 42 43 @item @cite{IBM PPC403GB Embedded Controller User's Manual}. 44 45 @item @cite{PoweRisControl MPC500 Family RCPU RISC Central Processing 46 Unit Reference Manual} (Motorola Document RCPUURM/AD). 47 48 @item @cite{PowerPC 601 RISC Microprocessor User's Manual} 49 (Motorola Document MPR601UM/AD). 50 51 @item @cite{PowerPC 603 RISC Microprocessor User's Manual} 52 (Motorola Document MPR603UM/AD). 53 54 @item @cite{PowerPC 603e RISC Microprocessor User's Manual} 55 (Motorola Document MPR603EUM/AD). 56 57 @item @cite{PowerPC 604 RISC Microprocessor User's Manual} 58 (Motorola Document MPR604UM/AD). 59 60 @item @cite{PowerPC MPC821 Portable Systems Microprocessor User's Manual} 61 (Motorola Document MPC821UM/AD). 62 63 @item @cite{PowerQUICC MPC860 User's Manual} (Motorola Document MPC860UM/AD). 64 65 41 66 @end itemize 67 68 Motorola maintains an on-line electronic library for the PowerPC 69 at the following URL: 70 71 @itemize @code{ } 72 @item @cite{http://www.mot.com/powerpc/library/library.html} 73 @end itemize 74 75 This site has a a wealth of information and examples. Many of the 76 manuals are available from that site in electronic format. 42 77 43 78 @subheading PowerPC Processor Simulator Information -
doc/supplements/sparc/bsp.t
r84b0f7c9 r9aceddaf 71 71 RTEMS installs it's own Trap Table as part of initialization 72 72 which is initialized with the contents of the Trap Table in 73 place when the rtems_initialize_executivedirective was invoked.73 place when the @code{rtems_initialize_executive} directive was invoked. 74 74 Upon completion of executive initialization, interrupts are 75 75 enabled. … … 83 83 Applications User's Manual for the reset code 84 84 which is executed before the call to 85 rtems_initialize executive, the SPARC version has the following85 @code{rtems_initialize_executive}, the SPARC version has the following 86 86 specific requirements: 87 87 … … 92 92 @item Must set stack pointer (sp) such that a minimum stack 93 93 size of MINIMUM_STACK_SIZE bytes is provided for the 94 rtems_initialize executivedirective.94 @code{rtems_initialize_executive} directive. 95 95 96 96 @item Must disable all external interrupts (i.e. set the pil -
doc/supplements/sparc/bsp.texi
r84b0f7c9 r9aceddaf 71 71 RTEMS installs it's own Trap Table as part of initialization 72 72 which is initialized with the contents of the Trap Table in 73 place when the rtems_initialize_executivedirective was invoked.73 place when the @code{rtems_initialize_executive} directive was invoked. 74 74 Upon completion of executive initialization, interrupts are 75 75 enabled. … … 83 83 Applications User's Manual for the reset code 84 84 which is executed before the call to 85 rtems_initialize executive, the SPARC version has the following85 @code{rtems_initialize_executive}, the SPARC version has the following 86 86 specific requirements: 87 87 … … 92 92 @item Must set stack pointer (sp) such that a minimum stack 93 93 size of MINIMUM_STACK_SIZE bytes is provided for the 94 rtems_initialize executivedirective.94 @code{rtems_initialize_executive} directive. 95 95 96 96 @item Must disable all external interrupts (i.e. set the pil
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