Changeset 9a84f983 in rtems


Ignore:
Timestamp:
Jul 17, 2015, 3:04:05 PM (4 years ago)
Author:
Premysl Houdek <kom541000@…>
Branches:
4.11
Children:
49c1d25d
Parents:
3f923fd2
git-author:
Premysl Houdek <kom541000@…> (07/17/15 15:04:05)
git-committer:
Chris Johns <chrisj@…> (07/20/15 11:06:42)
Message:

bsp/tms570: skipped 32bit field definitions and corrected single bit fields

there is no need to define access macros for field covering
whole registers. In addition, BSP_FLD32 does not work right
for field 32bit length.

Signed-off-by: Premysl Houdek <kom541000@…>

Location:
c/src/lib/libbsp/arm/tms570/include/ti_herc
Files:
36 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_adc.h

    r3f923fd2 r9a84f983  
    3737 * either expressed or implied, of the FreeBSD Project.
    3838*/
    39 #ifndef LIBBSP_ARM_tms570_ADC
    40 #define LIBBSP_ARM_tms570_ADC
     39#ifndef LIBBSP_ARM_TMS570_ADC
     40#define LIBBSP_ARM_TMS570_ADC
    4141
    4242#include <bsp/utility.h>
     
    116116
    117117
    118 /*-----------------------TMS570_ADCBUF0-----------------------*/
     118/*----------------------TMS570_ADC_BUFx----------------------*/
    119119/* field: G2_EMPTY_10bit_mode - Group2 FIFO Empty. */
    120 #define TMS570_ADC_BUF0_G2_EMPTY_10bit_mode BSP_FLD32(15)
     120#define TMS570_ADC_BUFx_G2_EMPTY_10bit_mode BSP_BIT32(15)
    121121
    122122/* field: G2_CHID_10bit_mode - Group2 Channel Id. */
    123 #define TMS570_ADC_BUF0_G2_CHID_10bit_mode(val) BSP_FLD32(val,10, 14)
    124 #define TMS570_ADC_BUF0_G2_CHID_10bit_mode_GET(reg) BSP_FLD32GET(reg,10, 14)
    125 #define TMS570_ADC_BUF0_G2_CHID_10bit_mode_SET(reg,val) BSP_FLD32SET(reg, val,10, 14)
     123#define TMS570_ADC_BUFx_G2_CHID_10bit_mode(val) BSP_FLD32(val,10, 14)
     124#define TMS570_ADC_BUFx_G2_CHID_10bit_mode_GET(reg) BSP_FLD32GET(reg,10, 14)
     125#define TMS570_ADC_BUFx_G2_CHID_10bit_mode_SET(reg,val) BSP_FLD32SET(reg, val,10, 14)
    126126
    127127/* field: G2_DR_10bit_mode - Group2 Digital Conversion Result. */
    128 #define TMS570_ADC_BUF0_G2_DR_10bit_mode(val) BSP_FLD32(val,0, 9)
    129 #define TMS570_ADC_BUF0_G2_DR_10bit_mode_GET(reg) BSP_FLD32GET(reg,0, 9)
    130 #define TMS570_ADC_BUF0_G2_DR_10bit_mode_SET(reg,val) BSP_FLD32SET(reg, val,0, 9)
     128#define TMS570_ADC_BUFx_G2_DR_10bit_mode(val) BSP_FLD32(val,0, 9)
     129#define TMS570_ADC_BUFx_G2_DR_10bit_mode_GET(reg) BSP_FLD32GET(reg,0, 9)
     130#define TMS570_ADC_BUFx_G2_DR_10bit_mode_SET(reg,val) BSP_FLD32SET(reg, val,0, 9)
    131131
    132132/* field: G2_EMPTY_12bit_mode - Group2 FIFO Empty. */
    133 #define TMS570_ADC_BUF0_G2_EMPTY_12bit_mode BSP_FLD32(31)
     133#define TMS570_ADC_BUFx_G2_EMPTY_12bit_mode BSP_BIT32(31)
    134134
    135135/* field: G2_CHID_12bit_mode - Group2 Channel Id. */
    136 #define TMS570_ADC_BUF0_G2_CHID_12bit_mode(val) BSP_FLD32(val,16, 20)
    137 #define TMS570_ADC_BUF0_G2_CHID_12bit_mode_GET(reg) BSP_FLD32GET(reg,16, 20)
    138 #define TMS570_ADC_BUF0_G2_CHID_12bit_mode_SET(reg,val) BSP_FLD32SET(reg, val,16, 20)
     136#define TMS570_ADC_BUFx_G2_CHID_12bit_mode(val) BSP_FLD32(val,16, 20)
     137#define TMS570_ADC_BUFx_G2_CHID_12bit_mode_GET(reg) BSP_FLD32GET(reg,16, 20)
     138#define TMS570_ADC_BUFx_G2_CHID_12bit_mode_SET(reg,val) BSP_FLD32SET(reg, val,16, 20)
    139139
    140140/* field: G2_DR_12bit_mode - Group2 Digital Conversion Result. */
    141 #define TMS570_ADC_BUF0_G2_DR_12bit_mode(val) BSP_FLD32(val,0, 11)
    142 #define TMS570_ADC_BUF0_G2_DR_12bit_mode_GET(reg) BSP_FLD32GET(reg,0, 11)
    143 #define TMS570_ADC_BUF0_G2_DR_12bit_mode_SET(reg,val) BSP_FLD32SET(reg, val,0, 11)
    144 
    145 
    146 /*----------------------TMS570_ADCRSTCR----------------------*/
     141#define TMS570_ADC_BUFx_G2_DR_12bit_mode(val) BSP_FLD32(val,0, 11)
     142#define TMS570_ADC_BUFx_G2_DR_12bit_mode_GET(reg) BSP_FLD32GET(reg,0, 11)
     143#define TMS570_ADC_BUFx_G2_DR_12bit_mode_SET(reg,val) BSP_FLD32SET(reg, val,0, 11)
     144
     145
     146/*----------------------TMS570_ADC_RSTCR----------------------*/
    147147/* field: RESET - This bit is used to reset the ADC internal state machines and control/status registers. */
    148 #define TMS570_ADC_RSTCR_RESET BSP_FLD32(0)
    149 
    150 
    151 /*---------------------TMS570_ADCOPMODECR---------------------*/
     148#define TMS570_ADC_RSTCR_RESET BSP_BIT32(0)
     149
     150
     151/*--------------------TMS570_ADC_OPMODECR--------------------*/
    152152/* field: 10_12_BIT - This bit controls the resolution of the ADC core. */
    153 #define TMS570_ADC_OPMODECR_10_12_BIT BSP_FLD32(31)
    154 
    155 
    156 /*---------------------TMS570_ADCCLOCKCR---------------------*/
     153#define TMS570_ADC_OPMODECR_10_12_BIT BSP_BIT32(31)
     154
     155
     156/*---------------------TMS570_ADC_CLOCKCR---------------------*/
    157157/* field: PS - ADC Clock Prescaler. These bits define the prescaler value for the ADC core clock (ADCLK). */
    158158#define TMS570_ADC_CLOCKCR_PS(val) BSP_FLD32(val,0, 4)
     
    161161
    162162
    163 /*----------------------TMS570_ADCCALCR----------------------*/
     163/*----------------------TMS570_ADC_CALCR----------------------*/
    164164/* field: SELF_TEST - ADC Self Test Enable. */
    165 #define TMS570_ADC_CALCR_SELF_TEST BSP_FLD32(24)
     165#define TMS570_ADC_CALCR_SELF_TEST BSP_BIT32(24)
    166166
    167167/* field: CAL_ST - ADC Calibration Conversion Start. */
    168 #define TMS570_ADC_CALCR_CAL_ST BSP_FLD32(16)
     168#define TMS570_ADC_CALCR_CAL_ST BSP_BIT32(16)
    169169
    170170/* field: BRIDGE_EN - Bridge Enable. */
    171 #define TMS570_ADC_CALCR_BRIDGE_EN BSP_FLD32(9)
     171#define TMS570_ADC_CALCR_BRIDGE_EN BSP_BIT32(9)
    172172
    173173/* field: HILO - ADC Self Test mode and Calibration Mode Reference Source Selection. */
    174 #define TMS570_ADC_CALCR_HILO BSP_FLD32(8)
     174#define TMS570_ADC_CALCR_HILO BSP_BIT32(8)
    175175
    176176/* field: CAL_EN - ADC Calibration Enable. */
    177 #define TMS570_ADC_CALCR_CAL_EN BSP_FLD32(0)
    178 
    179 
    180 /*---------------------TMS570_ADCGxMODECR---------------------*/
     177#define TMS570_ADC_CALCR_CAL_EN BSP_BIT32(0)
     178
     179
     180/*--------------------TMS570_ADC_GxMODECR--------------------*/
    181181/* field: No_Reset_on_ChnSel - No Event Group Results Memory Reset on New Channel Select. */
    182 #define TMS570_ADC_GxMODECR_No_Reset_on_ChnSel BSP_FLD32(16)
     182#define TMS570_ADC_GxMODECR_No_Reset_on_ChnSel BSP_BIT32(16)
    183183
    184184/* field: EV_DATA_FMT - Event Group Read Data Format. */
     
    188188
    189189
    190 /*----------------------TMS570_ADCEVSRC----------------------*/
     190/*----------------------TMS570_ADC_EVSRC----------------------*/
    191191/* field: EV_EDG_BOTH - rising and falling edge detected on the selected trigger source. */
    192 #define TMS570_ADC_EVSRC_EV_EDG_BOTH BSP_FLD32(4)
     192#define TMS570_ADC_EVSRC_EV_EDG_BOTH BSP_BIT32(4)
    193193
    194194/* field: EV_EDG_SEL - Event Group Trigger Edge Polarity Select. */
    195 #define TMS570_ADC_EVSRC_EV_EDG_SEL BSP_FLD32(3)
     195#define TMS570_ADC_EVSRC_EV_EDG_SEL BSP_BIT32(3)
    196196
    197197/* field: EV_SRC - Event Group Trigger Source. */
     
    201201
    202202
    203 /*----------------------TMS570_ADCG1SRC----------------------*/
     203/*----------------------TMS570_ADC_G1SRC----------------------*/
    204204/* field: GI_EDG_BOTH - Group1 Trigger Edge Polarity Select. */
    205 #define TMS570_ADC_G1SRC_GI_EDG_BOTH BSP_FLD32(4)
     205#define TMS570_ADC_G1SRC_GI_EDG_BOTH BSP_BIT32(4)
    206206
    207207/* field: G1_EDG_SEL - Group1 Trigger Edge Polarity Select. */
    208 #define TMS570_ADC_G1SRC_G1_EDG_SEL BSP_FLD32(3)
     208#define TMS570_ADC_G1SRC_G1_EDG_SEL BSP_BIT32(3)
    209209
    210210/* field: G1_SRC - Group1 Trigger Source. */
     
    214214
    215215
    216 /*----------------------TMS570_ADCG2SRC----------------------*/
     216/*----------------------TMS570_ADC_G2SRC----------------------*/
    217217/* field: G2_EDG_BOTH - Group2 Trigger Edge Polarity Select. */
    218 #define TMS570_ADC_G2SRC_G2_EDG_BOTH BSP_FLD32(4)
     218#define TMS570_ADC_G2SRC_G2_EDG_BOTH BSP_BIT32(4)
    219219
    220220/* field: G2_EDG_SEL - Group2 Trigger Edge Polarity Select. */
    221 #define TMS570_ADC_G2SRC_G2_EDG_SEL BSP_FLD32(3)
     221#define TMS570_ADC_G2SRC_G2_EDG_SEL BSP_BIT32(3)
    222222
    223223/* field: G2_SRC - Group2 Trigger Source. */
     
    227227
    228228
    229 /*---------------------TMS570_ADCGxINTENA---------------------*/
     229/*--------------------TMS570_ADC_GxINTENA--------------------*/
    230230/* field: EV_END_INT_EN - Event Group Conversion End Interrupt Enable. Please refer to Section 19.5. */
    231 #define TMS570_ADC_GxINTENA_EV_END_INT_EN BSP_FLD32(3)
     231#define TMS570_ADC_GxINTENA_EV_END_INT_EN BSP_BIT32(3)
    232232
    233233/* field: EV_OVR_INT_EN - write a new conversion result to the Event Group results memory which is already full. */
    234 #define TMS570_ADC_GxINTENA_EV_OVR_INT_EN BSP_FLD32(1)
     234#define TMS570_ADC_GxINTENA_EV_OVR_INT_EN BSP_BIT32(1)
    235235
    236236/* field: EV_THR_INT_EN - Event Group Threshold Interrupt Enable. */
    237 #define TMS570_ADC_GxINTENA_EV_THR_INT_EN BSP_FLD32(0)
    238 
    239 
    240 /*---------------------TMS570_ADCGxINTFLG---------------------*/
     237#define TMS570_ADC_GxINTENA_EV_THR_INT_EN BSP_BIT32(0)
     238
     239
     240/*--------------------TMS570_ADC_GxINTFLG--------------------*/
    241241/* field: EV_END - Event Group Conversion End. */
    242 #define TMS570_ADC_GxINTFLG_EV_END BSP_FLD32(3)
     242#define TMS570_ADC_GxINTFLG_EV_END BSP_BIT32(3)
    243243
    244244/* field: EV_MEM_EMPTY - Event Group Results Memory Empty. This is a read-only bit; writes have no effect. It is not asource of an interrupt from the ADC module. */
    245 #define TMS570_ADC_GxINTFLG_EV_MEM_EMPTY BSP_FLD32(2)
     245#define TMS570_ADC_GxINTFLG_EV_MEM_EMPTY BSP_BIT32(2)
    246246
    247247/* field: EV_MEM_OVERRUN - Event Group Memory Overrun. This is a read-only bit; writes have no effect. */
    248 #define TMS570_ADC_GxINTFLG_EV_MEM_OVERRUN BSP_FLD32(1)
     248#define TMS570_ADC_GxINTFLG_EV_MEM_OVERRUN BSP_BIT32(1)
    249249
    250250/* field: EV_THR_INT_FLG - Event Group Threshold Interrupt Flag. */
    251 #define TMS570_ADC_GxINTFLG_EV_THR_INT_FLG BSP_FLD32(0)
    252 
    253 
    254 /*---------------------TMS570_ADCGxINTCR---------------------*/
     251#define TMS570_ADC_GxINTFLG_EV_THR_INT_FLG BSP_BIT32(0)
     252
     253
     254/*---------------------TMS570_ADC_GxINTCR---------------------*/
    255255/* field: Sign_Extension - These bits always read the same as the bit 8 of this register. */
    256256#define TMS570_ADC_GxINTCR_Sign_Extension(val) BSP_FLD32(val,9, 15)
     
    264264
    265265
    266 /*---------------------TMS570_ADCEVDMACR---------------------*/
     266/*---------------------TMS570_ADC_EVDMACR---------------------*/
    267267/* field: EV_BLOCKS - Number of Event Group Result buffers to be transferred using DMA if the ADC module is */
    268268#define TMS570_ADC_EVDMACR_EV_BLOCKS(val) BSP_FLD32(val,16, 24)
     
    271271
    272272/* field: DMA_EV_END - Event Group Conversion End DMA Transfer Enable. */
    273 #define TMS570_ADC_EVDMACR_DMA_EV_END BSP_FLD32(3)
     273#define TMS570_ADC_EVDMACR_DMA_EV_END BSP_BIT32(3)
    274274
    275275/* field: EV_BLK_XFER - Event Group Block DMA Transfer Enable. */
    276 #define TMS570_ADC_EVDMACR_EV_BLK_XFER BSP_FLD32(2)
     276#define TMS570_ADC_EVDMACR_EV_BLK_XFER BSP_BIT32(2)
    277277
    278278/* field: EV_DMA_EN - Event Group DMA Transfer Enable. */
    279 #define TMS570_ADC_EVDMACR_EV_DMA_EN BSP_FLD32(0)
    280 
    281 
    282 /*---------------------TMS570_ADCG1DMACR---------------------*/
     279#define TMS570_ADC_EVDMACR_EV_DMA_EN BSP_BIT32(0)
     280
     281
     282/*---------------------TMS570_ADC_G1DMACR---------------------*/
    283283/* field: G1_BLOCKS - Number of Group1 Result buffers to be transferred using DMA if the ADC module is configured */
    284284#define TMS570_ADC_G1DMACR_G1_BLOCKS(val) BSP_FLD32(val,16, 24)
     
    287287
    288288/* field: DMA_G1_END - Group1 Conversion End DMA Transfer Enable. */
    289 #define TMS570_ADC_G1DMACR_DMA_G1_END BSP_FLD32(3)
     289#define TMS570_ADC_G1DMACR_DMA_G1_END BSP_BIT32(3)
    290290
    291291/* field: G1_BLK_XFER - Group1 Block DMA Transfer Enable. */
    292 #define TMS570_ADC_G1DMACR_G1_BLK_XFER BSP_FLD32(2)
     292#define TMS570_ADC_G1DMACR_G1_BLK_XFER BSP_BIT32(2)
    293293
    294294/* field: G1_DMA_EN - Group1 DMA Transfer Enable. */
    295 #define TMS570_ADC_G1DMACR_G1_DMA_EN BSP_FLD32(0)
    296 
    297 
    298 /*---------------------TMS570_ADCG2DMACR---------------------*/
     295#define TMS570_ADC_G1DMACR_G1_DMA_EN BSP_BIT32(0)
     296
     297
     298/*---------------------TMS570_ADC_G2DMACR---------------------*/
    299299/* field: G2_BLOCKS - Number of Group2 Result buffers to be transferred using DMA if the ADC module is configured */
    300300#define TMS570_ADC_G2DMACR_G2_BLOCKS(val) BSP_FLD32(val,16, 24)
     
    303303
    304304/* field: DMA_G2_END - Group2 Conversion End DMA Transfer Enable. */
    305 #define TMS570_ADC_G2DMACR_DMA_G2_END BSP_FLD32(3)
     305#define TMS570_ADC_G2DMACR_DMA_G2_END BSP_BIT32(3)
    306306
    307307/* field: G2_BLK_XFER - Group2 Block DMA Transfer Enable. */
    308 #define TMS570_ADC_G2DMACR_G2_BLK_XFER BSP_FLD32(2)
     308#define TMS570_ADC_G2DMACR_G2_BLK_XFER BSP_BIT32(2)
    309309
    310310/* field: G2_DMA_EN - Group2 DMA Transfer Enable. */
    311 #define TMS570_ADC_G2DMACR_G2_DMA_EN BSP_FLD32(0)
    312 
    313 
    314 /*----------------------TMS570_ADCBNDCR----------------------*/
     311#define TMS570_ADC_G2DMACR_G2_DMA_EN BSP_BIT32(0)
     312
     313
     314/*----------------------TMS570_ADC_BNDCR----------------------*/
    315315/* field: BNDA - Buffer Boundary A. */
    316316#define TMS570_ADC_BNDCR_BNDA(val) BSP_FLD32(val,16, 24)
     
    324324
    325325
    326 /*----------------------TMS570_ADCBNDEND----------------------*/
     326/*---------------------TMS570_ADC_BNDEND---------------------*/
    327327/* field: BUF_INIT_ACTIVE - ADC Results Memory Auto-initialization Status. */
    328 #define TMS570_ADC_BNDEND_BUF_INIT_ACTIVE BSP_FLD32(16)
     328#define TMS570_ADC_BNDEND_BUF_INIT_ACTIVE BSP_BIT32(16)
    329329
    330330/* field: BNDEND - Buffer Boundary End. */
     
    334334
    335335
    336 /*----------------------TMS570_ADCEVSAMP----------------------*/
     336/*---------------------TMS570_ADC_EVSAMP---------------------*/
    337337/* field: EV_ACQ - Event Group Acquisition Time. */
    338338#define TMS570_ADC_EVSAMP_EV_ACQ(val) BSP_FLD32(val,0, 11)
     
    341341
    342342
    343 /*----------------------TMS570_ADCG1SAMP----------------------*/
     343/*---------------------TMS570_ADC_G1SAMP---------------------*/
    344344/* field: G1_ACQ - Group1 Acquisition Time. These bits define the sampling window (SW) for the Group1 conversions. */
    345345#define TMS570_ADC_G1SAMP_G1_ACQ(val) BSP_FLD32(val,0, 11)
     
    348348
    349349
    350 /*----------------------TMS570_ADCG2SAMP----------------------*/
     350/*---------------------TMS570_ADC_G2SAMP---------------------*/
    351351/* field: G2_ACQ - Group2 Acquisition Time. These bits define the sampling window (SW) for the Group2 conversions. */
    352352#define TMS570_ADC_G2SAMP_G2_ACQ(val) BSP_FLD32(val,0, 11)
     
    355355
    356356
    357 /*-----------------------TMS570_ADCEVSR-----------------------*/
     357/*----------------------TMS570_ADC_EVSR----------------------*/
    358358/* field: EV_MEM_EMPTY - Event Group Results Memory Empty. */
    359 #define TMS570_ADC_EVSR_EV_MEM_EMPTY BSP_FLD32(3)
     359#define TMS570_ADC_EVSR_EV_MEM_EMPTY BSP_BIT32(3)
    360360
    361361/* field: EV_BUSY - Event Group Conversion Busy. */
    362 #define TMS570_ADC_EVSR_EV_BUSY BSP_FLD32(2)
     362#define TMS570_ADC_EVSR_EV_BUSY BSP_BIT32(2)
    363363
    364364/* field: EV_STOP - Event Group Conversion Stopped. */
    365 #define TMS570_ADC_EVSR_EV_STOP BSP_FLD32(1)
     365#define TMS570_ADC_EVSR_EV_STOP BSP_BIT32(1)
    366366
    367367/* field: EV_END - Event Group Conversions Ended. */
    368 #define TMS570_ADC_EVSR_EV_END BSP_FLD32(0)
    369 
    370 
    371 /*-----------------------TMS570_ADCG1SR-----------------------*/
     368#define TMS570_ADC_EVSR_EV_END BSP_BIT32(0)
     369
     370
     371/*----------------------TMS570_ADC_G1SR----------------------*/
    372372/* field: G1_MEM_EMPTY - Group1 Results Memory Empty. */
    373 #define TMS570_ADC_G1SR_G1_MEM_EMPTY BSP_FLD32(3)
     373#define TMS570_ADC_G1SR_G1_MEM_EMPTY BSP_BIT32(3)
    374374
    375375/* field: G1_BUSY - Group1 Conversion Busy. */
    376 #define TMS570_ADC_G1SR_G1_BUSY BSP_FLD32(2)
     376#define TMS570_ADC_G1SR_G1_BUSY BSP_BIT32(2)
    377377
    378378/* field: G1_STOP - Group1 Conversion Stopped. */
    379 #define TMS570_ADC_G1SR_G1_STOP BSP_FLD32(1)
     379#define TMS570_ADC_G1SR_G1_STOP BSP_BIT32(1)
    380380
    381381/* field: G1_END - Group1 Conversions Ended. */
    382 #define TMS570_ADC_G1SR_G1_END BSP_FLD32(0)
    383 
    384 
    385 /*-----------------------TMS570_ADCG2SR-----------------------*/
     382#define TMS570_ADC_G1SR_G1_END BSP_BIT32(0)
     383
     384
     385/*----------------------TMS570_ADC_G2SR----------------------*/
    386386/* field: G2_MEM_EMPTY - Group2 Results Memory Empty. */
    387 #define TMS570_ADC_G2SR_G2_MEM_EMPTY BSP_FLD32(3)
     387#define TMS570_ADC_G2SR_G2_MEM_EMPTY BSP_BIT32(3)
    388388
    389389/* field: G2_BUSY - Group2 Conversion Busy. */
    390 #define TMS570_ADC_G2SR_G2_BUSY BSP_FLD32(2)
     390#define TMS570_ADC_G2SR_G2_BUSY BSP_BIT32(2)
    391391
    392392/* field: G2_STOP - Group2 Conversion Stopped. */
    393 #define TMS570_ADC_G2SR_G2_STOP BSP_FLD32(1)
     393#define TMS570_ADC_G2SR_G2_STOP BSP_BIT32(1)
    394394
    395395/* field: G2_END - Group2 Conversions Ended. */
    396 #define TMS570_ADC_G2SR_G2_END BSP_FLD32(0)
    397 
    398 
    399 /*----------------------TMS570_ADCGxSEL----------------------*/
     396#define TMS570_ADC_G2SR_G2_END BSP_BIT32(0)
     397
     398
     399/*----------------------TMS570_ADC_GxSEL----------------------*/
    400400/* field: EV_SEL - Event Group channels selected. */
    401401#define TMS570_ADC_GxSEL_EV_SEL(val) BSP_FLD32(val,0, 15)
     
    404404
    405405
    406 /*-----------------------TMS570_ADCCALR-----------------------*/
     406/*----------------------TMS570_ADC_CALR----------------------*/
    407407/* field: ADCALR - ADC Calibration Result and Offset Error Correction Value. */
    408408#define TMS570_ADC_CALR_ADCALR(val) BSP_FLD32(val,0, 11)
     
    411411
    412412
    413 /*---------------------TMS570_ADCSMSTATE---------------------*/
     413/*---------------------TMS570_ADC_SMSTATE---------------------*/
    414414/* field: LAST_CONV - ADC Input Channel's Last Converted Value. */
    415415#define TMS570_ADC_SMSTATE_LAST_CONV(val) BSP_FLD32(val,0, 23)
     
    418418
    419419
    420 /*---------------------TMS570_ADCLASTCONV---------------------*/
     420/*--------------------TMS570_ADC_LASTCONV--------------------*/
    421421/* field: LAST_CONV - ADC Input Channel's Last Converted Value. */
    422422#define TMS570_ADC_LASTCONV_LAST_CONV(val) BSP_FLD32(val,0, 23)
     
    425425
    426426
    427 /*----------------------TMS570_ADCGxBUF----------------------*/
     427/*----------------------TMS570_ADC_GxBUF----------------------*/
    428428/* field: ADEVT_DIR - ADEVT Pin Direction. */
    429 #define TMS570_ADC_GxBUF_ADEVT_DIR BSP_FLD32(0)
    430 
    431 
    432 /*-------------------TMS570_ADCEVEMUBUFFER-------------------*/
     429#define TMS570_ADC_GxBUF_ADEVT_DIR BSP_BIT32(0)
     430
     431
     432/*-------------------TMS570_ADC_EVEMUBUFFER-------------------*/
    433433/* field: ADEVT_DIR - ADEVT Pin Direction. */
    434 #define TMS570_ADC_EVEMUBUFFER_ADEVT_DIR BSP_FLD32(0)
    435 
    436 
    437 /*-------------------TMS570_ADCG1EMUBUFFER-------------------*/
     434#define TMS570_ADC_EVEMUBUFFER_ADEVT_DIR BSP_BIT32(0)
     435
     436
     437/*-------------------TMS570_ADC_G1EMUBUFFER-------------------*/
    438438/* field: ADEVT_DIR - ADEVT Pin Direction. */
    439 #define TMS570_ADC_G1EMUBUFFER_ADEVT_DIR BSP_FLD32(0)
    440 
    441 
    442 /*-------------------TMS570_ADCG2EMUBUFFER-------------------*/
     439#define TMS570_ADC_G1EMUBUFFER_ADEVT_DIR BSP_BIT32(0)
     440
     441
     442/*-------------------TMS570_ADC_G2EMUBUFFER-------------------*/
    443443/* field: ADEVT_DIR - ADEVT Pin Direction. */
    444 #define TMS570_ADC_G2EMUBUFFER_ADEVT_DIR BSP_FLD32(0)
    445 
    446 
    447 /*----------------------TMS570_ADCEVTDIR----------------------*/
     444#define TMS570_ADC_G2EMUBUFFER_ADEVT_DIR BSP_BIT32(0)
     445
     446
     447/*---------------------TMS570_ADC_EVTDIR---------------------*/
    448448/* field: ADEVT_DIR - ADEVT Pin Direction. */
    449 #define TMS570_ADC_EVTDIR_ADEVT_DIR BSP_FLD32(0)
    450 
    451 
    452 /*----------------------TMS570_ADCEVTOUT----------------------*/
     449#define TMS570_ADC_EVTDIR_ADEVT_DIR BSP_BIT32(0)
     450
     451
     452/*---------------------TMS570_ADC_EVTOUT---------------------*/
    453453/* field: ADEVT_OUT - ADEVT Pin Output Value. */
    454 #define TMS570_ADC_EVTOUT_ADEVT_OUT BSP_FLD32(0)
    455 
    456 
    457 /*----------------------TMS570_ADCEVTIN----------------------*/
     454#define TMS570_ADC_EVTOUT_ADEVT_OUT BSP_BIT32(0)
     455
     456
     457/*----------------------TMS570_ADC_EVTIN----------------------*/
    458458/* field: ADEVT_IN - ADEVT Pin Input Value. This is a read-only bit which reflects the logic level on the ADEVT pin. */
    459 #define TMS570_ADC_EVTIN_ADEVT_IN BSP_FLD32(0)
    460 
    461 
    462 /*----------------------TMS570_ADCEVTSET----------------------*/
     459#define TMS570_ADC_EVTIN_ADEVT_IN BSP_BIT32(0)
     460
     461
     462/*---------------------TMS570_ADC_EVTSET---------------------*/
    463463/* field: ADEVT_SET - ADEVT Pin Set. This bit drives the output of the ADEVT pin high. */
    464 #define TMS570_ADC_EVTSET_ADEVT_SET BSP_FLD32(0)
    465 
    466 
    467 /*----------------------TMS570_ADCEVTCLR----------------------*/
     464#define TMS570_ADC_EVTSET_ADEVT_SET BSP_BIT32(0)
     465
     466
     467/*---------------------TMS570_ADC_EVTCLR---------------------*/
    468468/* field: ADEVT_CLR - ADEVT Pin Clear. A read from this bit always returns the current state of the ADEVT pin. */
    469 #define TMS570_ADC_EVTCLR_ADEVT_CLR BSP_FLD32(0)
    470 
    471 
    472 /*----------------------TMS570_ADCEVTPDR----------------------*/
     469#define TMS570_ADC_EVTCLR_ADEVT_CLR BSP_BIT32(0)
     470
     471
     472/*---------------------TMS570_ADC_EVTPDR---------------------*/
    473473/* field: ADEVT_PDR - ADEVT Pin Open Drain Enable. */
    474 #define TMS570_ADC_EVTPDR_ADEVT_PDR BSP_FLD32(0)
    475 
    476 
    477 /*---------------------TMS570_ADCEVTPDIS---------------------*/
     474#define TMS570_ADC_EVTPDR_ADEVT_PDR BSP_BIT32(0)
     475
     476
     477/*---------------------TMS570_ADC_EVTPDIS---------------------*/
    478478/* field: ADEVT_PDIS - ADEVT Pin Pull Control Disable. */
    479 #define TMS570_ADC_EVTPDIS_ADEVT_PDIS BSP_FLD32(0)
    480 
    481 
    482 /*---------------------TMS570_ADCEVTPSEL---------------------*/
     479#define TMS570_ADC_EVTPDIS_ADEVT_PDIS BSP_BIT32(0)
     480
     481
     482/*---------------------TMS570_ADC_EVTPSEL---------------------*/
    483483/* field: ADEVT_PSEL - ADEVT Pin Pull Control Select. */
    484 #define TMS570_ADC_EVTPSEL_ADEVT_PSEL BSP_FLD32(0)
    485 
    486 
    487 /*-------------------TMS570_ADCEVSAMPDISEN-------------------*/
     484#define TMS570_ADC_EVTPSEL_ADEVT_PSEL BSP_BIT32(0)
     485
     486
     487/*-------------------TMS570_ADC_EVSAMPDISEN-------------------*/
    488488/* field: EV_SAMP_DIS_CYC - Event Group sample cap discharge cycles. */
    489489#define TMS570_ADC_EVSAMPDISEN_EV_SAMP_DIS_CYC(val) BSP_FLD32(val,8, 15)
     
    492492
    493493/* field: EV_SAMP_DIS_EN - Event Group sample cap discharge enable. */
    494 #define TMS570_ADC_EVSAMPDISEN_EV_SAMP_DIS_EN BSP_FLD32(0)
    495 
    496 
    497 /*-------------------TMS570_ADCG1SAMPDISEN-------------------*/
     494#define TMS570_ADC_EVSAMPDISEN_EV_SAMP_DIS_EN BSP_BIT32(0)
     495
     496
     497/*-------------------TMS570_ADC_G1SAMPDISEN-------------------*/
    498498/* field: G1_SAMP_DIS_CYC - Group1 sample cap discharge cycles. */
    499499#define TMS570_ADC_G1SAMPDISEN_G1_SAMP_DIS_CYC(val) BSP_FLD32(val,8, 15)
     
    502502
    503503/* field: G1_SAMP_DIS_EN - Group1 sample cap discharge enable. */
    504 #define TMS570_ADC_G1SAMPDISEN_G1_SAMP_DIS_EN BSP_FLD32(0)
    505 
    506 
    507 /*-------------------TMS570_ADCG2SAMPDISEN-------------------*/
     504#define TMS570_ADC_G1SAMPDISEN_G1_SAMP_DIS_EN BSP_BIT32(0)
     505
     506
     507/*-------------------TMS570_ADC_G2SAMPDISEN-------------------*/
    508508/* field: G2_SAMP_DIS_CYC - for which the ADC internal sampling capacitor is allowed to discharge before sampling the input */
    509509#define TMS570_ADC_G2SAMPDISEN_G2_SAMP_DIS_CYC(val) BSP_FLD32(val,8, 15)
     
    512512
    513513/* field: G2_SAMP_DIS_EN - Group2 sample cap discharge enable. */
    514 #define TMS570_ADC_G2SAMPDISEN_G2_SAMP_DIS_EN BSP_FLD32(0)
    515 
    516 
    517 /*--------------------TMS570_ADCMAGINTCR1--------------------*/
     514#define TMS570_ADC_G2SAMPDISEN_G2_SAMP_DIS_EN BSP_BIT32(0)
     515
     516
     517/*--------------------TMS570_ADC_MAGINTCRx--------------------*/
    518518/* field: MAG_CHID2 - These bits specify the channel number from 0 to 31 for which the conversion result needs to be */
    519 #define TMS570_ADC_MAGINTCR1_MAG_CHID2(val) BSP_FLD32(val,26, 30)
    520 #define TMS570_ADC_MAGINTCR1_MAG_CHID2_GET(reg) BSP_FLD32GET(reg,26, 30)
    521 #define TMS570_ADC_MAGINTCR1_MAG_CHID2_SET(reg,val) BSP_FLD32SET(reg, val,26, 30)
     519#define TMS570_ADC_MAGINTCRx_MAG_CHID2(val) BSP_FLD32(val,26, 30)
     520#define TMS570_ADC_MAGINTCRx_MAG_CHID2_GET(reg) BSP_FLD32GET(reg,26, 30)
     521#define TMS570_ADC_MAGINTCRx_MAG_CHID2_SET(reg,val) BSP_FLD32SET(reg, val,26, 30)
    522522
    523523/* field: MAG_THR2 - These bits specify the 10-bit compare value which the ADC will use for the comparison with the */
    524 #define TMS570_ADC_MAGINTCR1_MAG_THR2(val) BSP_FLD32(val,16, 25)
    525 #define TMS570_ADC_MAGINTCR1_MAG_THR2_GET(reg) BSP_FLD32GET(reg,16, 25)
    526 #define TMS570_ADC_MAGINTCR1_MAG_THR2_SET(reg,val) BSP_FLD32SET(reg, val,16, 25)
     524#define TMS570_ADC_MAGINTCRx_MAG_THR2(val) BSP_FLD32(val,16, 25)
     525#define TMS570_ADC_MAGINTCRx_MAG_THR2_GET(reg) BSP_FLD32GET(reg,16, 25)
     526#define TMS570_ADC_MAGINTCRx_MAG_THR2_SET(reg,val) BSP_FLD32SET(reg, val,16, 25)
    527527
    528528/* field: COMP_CHID2 - These bits specify the channel number from 0 to 31 whose last conversion result is compared */
    529 #define TMS570_ADC_MAGINTCR1_COMP_CHID2(val) BSP_FLD32(val,8, 12)
    530 #define TMS570_ADC_MAGINTCR1_COMP_CHID2_GET(reg) BSP_FLD32GET(reg,8, 12)
    531 #define TMS570_ADC_MAGINTCR1_COMP_CHID2_SET(reg,val) BSP_FLD32SET(reg, val,8, 12)
     529#define TMS570_ADC_MAGINTCRx_COMP_CHID2(val) BSP_FLD32(val,8, 12)
     530#define TMS570_ADC_MAGINTCRx_COMP_CHID2_GET(reg) BSP_FLD32GET(reg,8, 12)
     531#define TMS570_ADC_MAGINTCRx_COMP_CHID2_SET(reg,val) BSP_FLD32SET(reg, val,8, 12)
    532532
    533533/* field: CHN_THR_COMP2 - Channel OR Threshold comparison. */
    534 #define TMS570_ADC_MAGINTCR1_CHN_THR_COMP2 BSP_FLD32(1)
     534#define TMS570_ADC_MAGINTCRx_CHN_THR_COMP2 BSP_BIT32(1)
    535535
    536536/* field: CMP_GE_LT2 - Greater than or equal to OR Less than comparison operator. */
    537 #define TMS570_ADC_MAGINTCR1_CMP_GE_LT2 BSP_FLD32(0)
    538 
    539 
    540 /*-------------------TMS570_ADCMAGINT1MASK-------------------*/
     537#define TMS570_ADC_MAGINTCRx_CMP_GE_LT2 BSP_BIT32(0)
     538
     539
     540/*-------------------TMS570_ADC_MAGINTxMASK-------------------*/
    541541/* field: MAG_INT0_MASK - These bits specify the mask for the comparison in order to generate the magnitude compare */
    542 #define TMS570_ADC_MAGINT1MASK_MAG_INT0_MASK(val) BSP_FLD32(val,0, 9)
    543 #define TMS570_ADC_MAGINT1MASK_MAG_INT0_MASK_GET(reg) BSP_FLD32GET(reg,0, 9)
    544 #define TMS570_ADC_MAGINT1MASK_MAG_INT0_MASK_SET(reg,val) BSP_FLD32SET(reg, val,0, 9)
    545 
    546 
    547 /*-----------------TMS570_ADCMAGTHRINTENASET-----------------*/
     542#define TMS570_ADC_MAGINTxMASK_MAG_INT0_MASK(val) BSP_FLD32(val,0, 9)
     543#define TMS570_ADC_MAGINTxMASK_MAG_INT0_MASK_GET(reg) BSP_FLD32GET(reg,0, 9)
     544#define TMS570_ADC_MAGINTxMASK_MAG_INT0_MASK_SET(reg,val) BSP_FLD32SET(reg, val,0, 9)
     545
     546
     547/*-----------------TMS570_ADC_MAGTHRINTENASET-----------------*/
    548548/* field: MAG_INT_ENA_SET - Each of these three bits, when set, enable the corresponding magnitude compare interrupt. */
    549549#define TMS570_ADC_MAGTHRINTENASET_MAG_INT_ENA_SET(val) BSP_FLD32(val,0, 2)
     
    552552
    553553
    554 /*-----------------TMS570_ADCMAGTHRINTENACLR-----------------*/
     554/*-----------------TMS570_ADC_MAGTHRINTENACLR-----------------*/
    555555/* field: MAG_INT_ENA_CLR - Each of these three bits, when set, enable the corresponding magnitude compare interrupt. */
    556556#define TMS570_ADC_MAGTHRINTENACLR_MAG_INT_ENA_CLR(val) BSP_FLD32(val,0, 2)
     
    559559
    560560
    561 /*-------------------TMS570_ADCMAGTHRINTFLG-------------------*/
     561/*------------------TMS570_ADC_MAGTHRINTFLG------------------*/
    562562/* field: MAG_INT_FLG - Magnitude Compare Interrupt Flags. */
    563563#define TMS570_ADC_MAGTHRINTFLG_MAG_INT_FLG(val) BSP_FLD32(val,0, 2)
     
    566566
    567567
    568 /*-----------------TMS570_ADCMAGTHRINTOFFSET-----------------*/
     568/*-----------------TMS570_ADC_MAGTHRINTOFFSET-----------------*/
    569569/* field: MAG_INT_OFF - Magnitude Compare Interrupt Offset. */
    570570#define TMS570_ADC_MAGTHRINTOFFSET_MAG_INT_OFF(val) BSP_FLD32(val,0, 3)
     
    573573
    574574
    575 /*------------------TMS570_ADCGxFIFORESETCR------------------*/
     575/*------------------TMS570_ADC_GxFIFORESETCR------------------*/
    576576/* field: EV_FIFO_RESET - allows the ADC module to overwrite the contents of the Event Group results memory starting from */
    577 #define TMS570_ADC_GxFIFORESETCR_EV_FIFO_RESET BSP_FLD32(0)
    578 
    579 
    580 /*-------------------TMS570_ADCEVRAMWRADDR-------------------*/
     577#define TMS570_ADC_GxFIFORESETCR_EV_FIFO_RESET BSP_BIT32(0)
     578
     579
     580/*-------------------TMS570_ADC_EVRAMWRADDR-------------------*/
    581581/* field: G1_RAM_ADDR - Group1 results memory write pointer. */
    582582#define TMS570_ADC_EVRAMWRADDR_G1_RAM_ADDR(val) BSP_FLD32(val,0, 8)
     
    585585
    586586
    587 /*-------------------TMS570_ADCG1RAMWRADDR-------------------*/
     587/*-------------------TMS570_ADC_G1RAMWRADDR-------------------*/
    588588/* field: G1_RAM_ADDR - Group1 results memory write pointer. */
    589589#define TMS570_ADC_G1RAMWRADDR_G1_RAM_ADDR(val) BSP_FLD32(val,0, 8)
     
    592592
    593593
    594 /*-------------------TMS570_ADCG2RAMWRADDR-------------------*/
     594/*-------------------TMS570_ADC_G2RAMWRADDR-------------------*/
    595595/* field: G2_RAM_ADDR - Group2 results memory write pointer. */
    596596#define TMS570_ADC_G2RAMWRADDR_G2_RAM_ADDR(val) BSP_FLD32(val,0, 8)
     
    599599
    600600
    601 /*----------------------TMS570_ADCPARCR----------------------*/
     601/*----------------------TMS570_ADC_PARCR----------------------*/
    602602/* field: TEST - This bit maps the parity bits into the ADC results' RAM frame so that the application can access */
    603 #define TMS570_ADC_PARCR_TEST BSP_FLD32(8)
     603#define TMS570_ADC_PARCR_TEST BSP_BIT32(8)
    604604
    605605/* field: PARITY_ENA - PARITY ENA */
     
    609609
    610610
    611 /*---------------------TMS570_ADCPARADDR---------------------*/
     611/*---------------------TMS570_ADC_PARADDR---------------------*/
    612612/* field: ERROR_ADDRESS - These bits hold the address of the first parity error generated in the ADC results' RAM. */
    613613#define TMS570_ADC_PARADDR_ERROR_ADDRESS(val) BSP_FLD32(val,2, 11)
     
    616616
    617617
    618 /*-------------------TMS570_ADCPWRUPDLYCTRL-------------------*/
     618/*------------------TMS570_ADC_PWRUPDLYCTRL------------------*/
    619619/* field: PWRUP_DLY - This register defines the number of VCLK cycles that the ADC state machine has to wait after */
    620620#define TMS570_ADC_PWRUPDLYCTRL_PWRUP_DLY(val) BSP_FLD32(val,0, 9)
     
    624624
    625625
    626 #endif /* LIBBSP_ARM_tms570_ADC */
     626#endif /* LIBBSP_ARM_TMS570_ADC */
  • c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_ccmsr.h

    r3f923fd2 r9a84f983  
    3737 * either expressed or implied, of the FreeBSD Project.
    3838*/
    39 #ifndef LIBBSP_ARM_tms570_CCMSR
    40 #define LIBBSP_ARM_tms570_CCMSR
     39#ifndef LIBBSP_ARM_TMS570_CCMSR
     40#define LIBBSP_ARM_TMS570_CCMSR
    4141
    4242#include <bsp/utility.h>
     
    4848
    4949
    50 /*---------------------TMS570_CCMSRCCMSR---------------------*/
     50/*---------------------TMS570_CCMSR_CCMSR---------------------*/
    5151/* field: CMPE - Compare Error */
    52 #define TMS570_CCMSR_CCMSR_CMPE BSP_FLD32(16)
     52#define TMS570_CCMSR_CCMSR_CMPE BSP_BIT32(16)
    5353
    5454/* field: STC - Self-test Complete */
    55 #define TMS570_CCMSR_CCMSR_STC BSP_FLD32(8)
     55#define TMS570_CCMSR_CCMSR_STC BSP_BIT32(8)
    5656
    5757/* field: STET - Self-test Error Type */
    58 #define TMS570_CCMSR_CCMSR_STET BSP_FLD32(1)
     58#define TMS570_CCMSR_CCMSR_STET BSP_BIT32(1)
    5959
    6060/* field: STE - Self-test Error */
    61 #define TMS570_CCMSR_CCMSR_STE BSP_FLD32(0)
     61#define TMS570_CCMSR_CCMSR_STE BSP_BIT32(0)
    6262
    6363
    64 /*--------------------TMS570_CCMSRCCMKEYR--------------------*/
     64/*--------------------TMS570_CCMSR_CCMKEYR--------------------*/
    6565/* field: MKEY - Mode Key */
    6666#define TMS570_CCMSR_CCMKEYR_MKEY(val) BSP_FLD32(val,0, 3)
     
    7070
    7171
    72 #endif /* LIBBSP_ARM_tms570_CCMSR */
     72#endif /* LIBBSP_ARM_TMS570_CCMSR */
  • c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_crc.h

    r3f923fd2 r9a84f983  
    3737 * either expressed or implied, of the FreeBSD Project.
    3838*/
    39 #ifndef LIBBSP_ARM_tms570_CRC
    40 #define LIBBSP_ARM_tms570_CRC
     39#ifndef LIBBSP_ARM_TMS570_CRC
     40#define LIBBSP_ARM_TMS570_CRC
    4141
    4242#include <bsp/utility.h>
     
    9292
    9393
    94 /*----------------------TMS570_CRCCTRL0----------------------*/
     94/*----------------------TMS570_CRC_CTRL0----------------------*/
    9595/* field: CH2_PSA_SWREST - Channel 2 PSA Software Reset. When set, the PSA Signature Register is reset to all zero. */
    96 #define TMS570_CRC_CTRL0_CH2_PSA_SWREST BSP_FLD32(8)
     96#define TMS570_CRC_CTRL0_CH2_PSA_SWREST BSP_BIT32(8)
    9797
    9898/* field: CH1_PSA_SWREST - Channel 1 PSA Software Reset. When set, the PSA Signature Register is reset to all zero. */
    99 #define TMS570_CRC_CTRL0_CH1_PSA_SWREST BSP_FLD32(0)
    100 
    101 
    102 /*----------------------TMS570_CRCCTRL1----------------------*/
     99#define TMS570_CRC_CTRL0_CH1_PSA_SWREST BSP_BIT32(0)
     100
     101
     102/*----------------------TMS570_CRC_CTRL1----------------------*/
    103103/* field: PWDN - Power Down. */
    104 #define TMS570_CRC_CTRL1_PWDN BSP_FLD32(0)
    105 
    106 
    107 /*----------------------TMS570_CRCCTRL2----------------------*/
     104#define TMS570_CRC_CTRL1_PWDN BSP_BIT32(0)
     105
     106
     107/*----------------------TMS570_CRC_CTRL2----------------------*/
    108108/* field: CH2_MODE - Channel 2 Mode Selection */
    109109#define TMS570_CRC_CTRL2_CH2_MODE(val) BSP_FLD32(val,8, 9)
     
    112112
    113113/* field: CH1_TRACEEN - Channel 1 Data Trace Enable. When set, the channel is put into data trace mode. */
    114 #define TMS570_CRC_CTRL2_CH1_TRACEEN BSP_FLD32(4)
     114#define TMS570_CRC_CTRL2_CH1_TRACEEN BSP_BIT32(4)
    115115
    116116/* field: CH1_MODE - Channel 1 Mode Selection */
     
    120120
    121121
    122 /*-----------------------TMS570_CRCINTS-----------------------*/
     122/*----------------------TMS570_CRC_INTS----------------------*/
    123123/* field: CH2_TIMEOUTENS - Channel 2 Timeout Interrupt Enable Bit. */
    124 #define TMS570_CRC_INTS_CH2_TIMEOUTENS BSP_FLD32(12)
     124#define TMS570_CRC_INTS_CH2_TIMEOUTENS BSP_BIT32(12)
    125125
    126126/* field: CH2_UNDERENS - Channel 2 Underrun Interrupt Enable Bit. */
    127 #define TMS570_CRC_INTS_CH2_UNDERENS BSP_FLD32(11)
     127#define TMS570_CRC_INTS_CH2_UNDERENS BSP_BIT32(11)
    128128
    129129/* field: CH2_OVERENS - Channel 2 Overrun Interrupt Enable Bit. */
    130 #define TMS570_CRC_INTS_CH2_OVERENS BSP_FLD32(10)
     130#define TMS570_CRC_INTS_CH2_OVERENS BSP_BIT32(10)
    131131
    132132/* field: CH2_CRCFAILENS - Channel 2 CRC Fail Interrupt Enable Bit. */
    133 #define TMS570_CRC_INTS_CH2_CRCFAILENS BSP_FLD32(9)
     133#define TMS570_CRC_INTS_CH2_CRCFAILENS BSP_BIT32(9)
    134134
    135135/* field: CH2_CCITENS - Channel 2 Compression Complete Interrupt Enable Bit. */
    136 #define TMS570_CRC_INTS_CH2_CCITENS BSP_FLD32(8)
     136#define TMS570_CRC_INTS_CH2_CCITENS BSP_BIT32(8)
    137137
    138138/* field: CH1_TIMEOUTENS - Channel 1 Timeout Interrupt Enable Bit. */
    139 #define TMS570_CRC_INTS_CH1_TIMEOUTENS BSP_FLD32(4)
     139#define TMS570_CRC_INTS_CH1_TIMEOUTENS BSP_BIT32(4)
    140140
    141141/* field: CH1_UNDERENS - Channel 1 Underrun Interrupt Enable Bit. */
    142 #define TMS570_CRC_INTS_CH1_UNDERENS BSP_FLD32(3)
     142#define TMS570_CRC_INTS_CH1_UNDERENS BSP_BIT32(3)
    143143
    144144/* field: CH1_OVERENS - CH1_OVERENS Channel 1 Overrun Interrupt Enable Bit. */
    145 #define TMS570_CRC_INTS_CH1_OVERENS BSP_FLD32(2)
     145#define TMS570_CRC_INTS_CH1_OVERENS BSP_BIT32(2)
    146146
    147147/* field: CH1_CRCFAILENS - Channel 1 CRC Fail Interrupt Enable Bit. */
    148 #define TMS570_CRC_INTS_CH1_CRCFAILENS BSP_FLD32(1)
     148#define TMS570_CRC_INTS_CH1_CRCFAILENS BSP_BIT32(1)
    149149
    150150/* field: CH1_CCITENS - Channel 1 Compression Complete Interrupt Enable Bit. */
    151 #define TMS570_CRC_INTS_CH1_CCITENS BSP_FLD32(0)
    152 
    153 
    154 /*-----------------------TMS570_CRCINTR-----------------------*/
     151#define TMS570_CRC_INTS_CH1_CCITENS BSP_BIT32(0)
     152
     153
     154/*----------------------TMS570_CRC_INTR----------------------*/
    155155/* field: CH2_TIMEOUTENR - Channel 2 Timeout Interrupt Enable Bit. */
    156 #define TMS570_CRC_INTR_CH2_TIMEOUTENR BSP_FLD32(12)
     156#define TMS570_CRC_INTR_CH2_TIMEOUTENR BSP_BIT32(12)
    157157
    158158/* field: CH2_UNDERENR - Channel 2 Underrun Interrupt Enable Bit. */
    159 #define TMS570_CRC_INTR_CH2_UNDERENR BSP_FLD32(11)
     159#define TMS570_CRC_INTR_CH2_UNDERENR BSP_BIT32(11)
    160160
    161161/* field: CH2_OVERENR - Channel 2 Overrun Interrupt Enable Bit. */
    162 #define TMS570_CRC_INTR_CH2_OVERENR BSP_FLD32(10)
     162#define TMS570_CRC_INTR_CH2_OVERENR BSP_BIT32(10)
    163163
    164164/* field: CH2_CRCFAILENR - Channel 2 CRC Fail Interrupt Enable Bit. */
    165 #define TMS570_CRC_INTR_CH2_CRCFAILENR BSP_FLD32(9)
     165#define TMS570_CRC_INTR_CH2_CRCFAILENR BSP_BIT32(9)
    166166
    167167/* field: CH2_CCITENR - Channel 2 Compression Complete Interrupt Enable Bit. */
    168 #define TMS570_CRC_INTR_CH2_CCITENR BSP_FLD32(8)
     168#define TMS570_CRC_INTR_CH2_CCITENR BSP_BIT32(8)
    169169
    170170/* field: CH1_TIMEOUTENR - Channel 1 Timeout Interrupt Enable Bit. */
    171 #define TMS570_CRC_INTR_CH1_TIMEOUTENR BSP_FLD32(4)
     171#define TMS570_CRC_INTR_CH1_TIMEOUTENR BSP_BIT32(4)
    172172
    173173/* field: CH1_UNDERENR - interrupt. Writing a zero has no effect. */
    174 #define TMS570_CRC_INTR_CH1_UNDERENR BSP_FLD32(3)
     174#define TMS570_CRC_INTR_CH1_UNDERENR BSP_BIT32(3)
    175175
    176176/* field: CH1_OVERENR - CH1_OVERENR */
    177 #define TMS570_CRC_INTR_CH1_OVERENR BSP_FLD32(2)
     177#define TMS570_CRC_INTR_CH1_OVERENR BSP_BIT32(2)
    178178
    179179/* field: CH1_CRCFAILENR - Channel 1 CRC Fail Interrupt Enable Bit. */
    180 #define TMS570_CRC_INTR_CH1_CRCFAILENR BSP_FLD32(1)
     180#define TMS570_CRC_INTR_CH1_CRCFAILENR BSP_BIT32(1)
    181181
    182182/* field: CH1_CCITENR - Channel 1 Compression Complete Interrupt Enable Bit. */
    183 #define TMS570_CRC_INTR_CH1_CCITENR BSP_FLD32(0)
    184 
    185 
    186 /*----------------------TMS570_CRCSTATUS----------------------*/
     183#define TMS570_CRC_INTR_CH1_CCITENR BSP_BIT32(0)
     184
     185
     186/*---------------------TMS570_CRC_STATUS---------------------*/
    187187/* field: CH2_TIMEOUT - Channel 2 CRC Timeout Status Flag. This bit is cleared by writing a '1' to it only. */
    188 #define TMS570_CRC_STATUS_CH2_TIMEOUT BSP_FLD32(12)
     188#define TMS570_CRC_STATUS_CH2_TIMEOUT BSP_BIT32(12)
    189189
    190190/* field: CH2_UNDER - Channel 2 CRC Underrun Status Flag. This bit is cleared by writing a '1' to it only. */
    191 #define TMS570_CRC_STATUS_CH2_UNDER BSP_FLD32(11)
     191#define TMS570_CRC_STATUS_CH2_UNDER BSP_BIT32(11)
    192192
    193193/* field: CH2_OVER - Channel 2 CRC Overrun Status Flag. This bit is cleared by writing a '1' to it only. */
    194 #define TMS570_CRC_STATUS_CH2_OVER BSP_FLD32(10)
     194#define TMS570_CRC_STATUS_CH2_OVER BSP_BIT32(10)
    195195
    196196/* field: CH2_CRCFAIL - Channel 2 CRC Compare Fail Status Flag. This bit is cleared by writing a '1' to it only. */
    197 #define TMS570_CRC_STATUS_CH2_CRCFAIL BSP_FLD32(9)
     197#define TMS570_CRC_STATUS_CH2_CRCFAIL BSP_BIT32(9)
    198198
    199199/* field: CH2_CCIT - Channel 2 CRC Pattern Compression Complete Status Flag. */
    200 #define TMS570_CRC_STATUS_CH2_CCIT BSP_FLD32(8)
     200#define TMS570_CRC_STATUS_CH2_CCIT BSP_BIT32(8)
    201201
    202202/* field: CH1_TIMEOUT - Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). */
    203 #define TMS570_CRC_STATUS_CH1_TIMEOUT BSP_FLD32(4)
     203#define TMS570_CRC_STATUS_CH1_TIMEOUT BSP_BIT32(4)
    204204
    205205/* field: CH1_UNDER - Channel 1 Underrun Interrupt Enable Bit. */
    206 #define TMS570_CRC_STATUS_CH1_UNDER BSP_FLD32(3)
     206#define TMS570_CRC_STATUS_CH1_UNDER BSP_BIT32(3)
    207207
    208208/* field: CH1_OVER - Channel 1 Overrun Interrupt Enable Bit. Writing a one to this bit disable the overrun interrupt. */
    209 #define TMS570_CRC_STATUS_CH1_OVER BSP_FLD32(2)
     209#define TMS570_CRC_STATUS_CH1_OVER BSP_BIT32(2)
    210210
    211211/* field: CH1_CRCFAIL - Channel 1 CRC Fail Interrupt Enable Bit. */
    212 #define TMS570_CRC_STATUS_CH1_CRCFAIL BSP_FLD32(1)
     212#define TMS570_CRC_STATUS_CH1_CRCFAIL BSP_BIT32(1)
    213213
    214214/* field: CH1_CCIT - Channel 1 CRC Pattern Compression Complete Status Flag. */
    215 #define TMS570_CRC_STATUS_CH1_CCIT BSP_FLD32(0)
    216 
    217 
    218 /*-------------------TMS570_CRCINT_OFFS_REG-------------------*/
     215#define TMS570_CRC_STATUS_CH1_CCIT BSP_BIT32(0)
     216
     217
     218/*------------------TMS570_CRC_INT_OFFS_REG------------------*/
    219219/* field: OFSTREG - CRC Interrupt Offset. This register indicates the highest priority pending interrupt vector address. */
    220220#define TMS570_CRC_INT_OFFS_REG_OFSTREG(val) BSP_FLD32(val,0, 7)
     
    223223
    224224
    225 /*-----------------------TMS570_CRCBUSY-----------------------*/
     225/*----------------------TMS570_CRC_BUSY----------------------*/
    226226/* field: CH2_BUSY - CH2_BUSY. */
    227 #define TMS570_CRC_BUSY_CH2_BUSY BSP_FLD32(8)
     227#define TMS570_CRC_BUSY_CH2_BUSY BSP_BIT32(8)
    228228
    229229/* field: CH1_BUSY - CH1_BUSY. */
    230 #define TMS570_CRC_BUSY_CH1_BUSY BSP_FLD32(0)
    231 
    232 
    233 /*-------------------TMS570_CRCPCOUNT_REG1-------------------*/
     230#define TMS570_CRC_BUSY_CH1_BUSY BSP_BIT32(0)
     231
     232
     233/*-------------------TMS570_CRC_PCOUNT_REG1-------------------*/
    234234/* field: CRC_PAT_COUNT1 - Channel 1 Pattern Counter Preload Register. */
    235235#define TMS570_CRC_PCOUNT_REG1_CRC_PAT_COUNT1(val) BSP_FLD32(val,0, 19)
     
    238238
    239239
    240 /*-------------------TMS570_CRCSCOUNT_REG1-------------------*/
     240/*-------------------TMS570_CRC_SCOUNT_REG1-------------------*/
    241241/* field: CRC_SEC_COUNT1 - Channel 1 Sector Counter Preload Register. */
    242242#define TMS570_CRC_SCOUNT_REG1_CRC_SEC_COUNT1(val) BSP_FLD32(val,0, 15)
     
    245245
    246246
    247 /*-------------------TMS570_CRCCURSEC_REG1-------------------*/
     247/*-------------------TMS570_CRC_CURSEC_REG1-------------------*/
    248248/* field: CRC_CURSEC1 - Channel 1 Current Sector ID Register. */
    249249#define TMS570_CRC_CURSEC_REG1_CRC_CURSEC1(val) BSP_FLD32(val,0, 15)
     
    252252
    253253
    254 /*---------------------TMS570_CRCWDTOPLD1---------------------*/
     254/*--------------------TMS570_CRC_WDTOPLD1--------------------*/
    255255/* field: CRC_WDTOPLD1 - CRC_WDTOPLD1 */
    256256#define TMS570_CRC_WDTOPLD1_CRC_WDTOPLD1(val) BSP_FLD32(val,0, 23)
     
    259259
    260260
    261 /*---------------------TMS570_CRCBCTOPLD1---------------------*/
     261/*--------------------TMS570_CRC_BCTOPLD1--------------------*/
    262262/* field: CRC_BCTOPLD1 - Channel 1 Block Complete Timeout Counter Preload Register. */
    263263#define TMS570_CRC_BCTOPLD1_CRC_BCTOPLD1(val) BSP_FLD32(val,0, 23)
     
    266266
    267267
    268 /*-------------------TMS570_CRCPSA_SIGREGL1-------------------*/
     268/*------------------TMS570_CRC_PSA_SIGREGL1------------------*/
    269269/* field: PSASIG1 - Channel 1 PSA Signature Low Register. */
    270 #define TMS570_CRC_PSA_SIGREGL1_PSASIG1(val) BSP_FLD32(val,0, 31)
    271 #define TMS570_CRC_PSA_SIGREGL1_PSASIG1_GET(reg) BSP_FLD32GET(reg,0, 31)
    272 #define TMS570_CRC_PSA_SIGREGL1_PSASIG1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
    273 
    274 
    275 /*-------------------TMS570_CRCPSA_SIGREGH1-------------------*/
     270/* Whole 32 bits */
     271
     272/*------------------TMS570_CRC_PSA_SIGREGH1------------------*/
    276273/* field: PSASIG1 - register. */
    277 #define TMS570_CRC_PSA_SIGREGH1_PSASIG1(val) BSP_FLD32(val,0, 31)
    278 #define TMS570_CRC_PSA_SIGREGH1_PSASIG1_GET(reg) BSP_FLD32GET(reg,0, 31)
    279 #define TMS570_CRC_PSA_SIGREGH1_PSASIG1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
    280 
    281 
    282 /*----------------------TMS570_CRCREGL1----------------------*/
     274/* Whole 32 bits */
     275
     276/*----------------------TMS570_CRC_REGL1----------------------*/
    283277/* field: CRC1 - Channel 1 CRC Value Low Register. */
    284 #define TMS570_CRC_REGL1_CRC1(val) BSP_FLD32(val,0, 31)
    285 #define TMS570_CRC_REGL1_CRC1_GET(reg) BSP_FLD32GET(reg,0, 31)
    286 #define TMS570_CRC_REGL1_CRC1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
    287 
    288 
    289 /*----------------------TMS570_CRCREGH1----------------------*/
     278/* Whole 32 bits */
     279
     280/*----------------------TMS570_CRC_REGH1----------------------*/
    290281/* field: CRC1 - Channel 1 CRC Value Low Register. */
    291 #define TMS570_CRC_REGH1_CRC1(val) BSP_FLD32(val,0, 31)
    292 #define TMS570_CRC_REGH1_CRC1_GET(reg) BSP_FLD32GET(reg,0, 31)
    293 #define TMS570_CRC_REGH1_CRC1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
    294 
    295 
    296 /*-----------------TMS570_CRCPSA_SECSIGREGL1-----------------*/
     282/* Whole 32 bits */
     283
     284/*-----------------TMS570_CRC_PSA_SECSIGREGL1-----------------*/
    297285/* field: PSASECSIG1 - Channel 1 PSA Sector Signature Low Register. */
    298 #define TMS570_CRC_PSA_SECSIGREGL1_PSASECSIG1(val) BSP_FLD32(val,0, 31)
    299 #define TMS570_CRC_PSA_SECSIGREGL1_PSASECSIG1_GET(reg) BSP_FLD32GET(reg,0, 31)
    300 #define TMS570_CRC_PSA_SECSIGREGL1_PSASECSIG1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
    301 
    302 
    303 /*-----------------TMS570_CRCPSA_SECSIGREGH1-----------------*/
     286/* Whole 32 bits */
     287
     288/*-----------------TMS570_CRC_PSA_SECSIGREGH1-----------------*/
    304289/* field: PSASECSIG1 - Channel 1 PSA Sector Signature High Register. */
    305 #define TMS570_CRC_PSA_SECSIGREGH1_PSASECSIG1(val) BSP_FLD32(val,0, 31)
    306 #define TMS570_CRC_PSA_SECSIGREGH1_PSASECSIG1_GET(reg) BSP_FLD32GET(reg,0, 31)
    307 #define TMS570_CRC_PSA_SECSIGREGH1_PSASECSIG1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
    308 
    309 
    310 /*------------------TMS570_CRCRAW_DATAREGL1------------------*/
     290/* Whole 32 bits */
     291
     292/*------------------TMS570_CRC_RAW_DATAREGL1------------------*/
    311293/* field: RAW_DATA1 - hannel 1 Raw Data Low Register.This register contains bits 31:0 of the uncompressed raw data. */
    312 #define TMS570_CRC_RAW_DATAREGL1_RAW_DATA1(val) BSP_FLD32(val,0, 31)
    313 #define TMS570_CRC_RAW_DATAREGL1_RAW_DATA1_GET(reg) BSP_FLD32GET(reg,0, 31)
    314 #define TMS570_CRC_RAW_DATAREGL1_RAW_DATA1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
    315 
    316 
    317 /*------------------TMS570_CRCRAW_DATAREGH1------------------*/
     294/* Whole 32 bits */
     295
     296/*------------------TMS570_CRC_RAW_DATAREGH1------------------*/
    318297/* field: RAW_DATA1 - Channel 1 Raw Data High Register. This register contains bits 63:32 of the uncompressed raw data. */
    319 #define TMS570_CRC_RAW_DATAREGH1_RAW_DATA1(val) BSP_FLD32(val,0, 31)
    320 #define TMS570_CRC_RAW_DATAREGH1_RAW_DATA1_GET(reg) BSP_FLD32GET(reg,0, 31)
    321 #define TMS570_CRC_RAW_DATAREGH1_RAW_DATA1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
    322 
    323 
    324 /*-------------------TMS570_CRCPCOUNT_REG2-------------------*/
     298/* Whole 32 bits */
     299
     300/*-------------------TMS570_CRC_PCOUNT_REG2-------------------*/
    325301/* field: CRC_PAT_COUNT2 - Channel 2 Pattern Counter Preload Register. */
    326302#define TMS570_CRC_PCOUNT_REG2_CRC_PAT_COUNT2(val) BSP_FLD32(val,0, 19)
     
    329305
    330306
    331 /*-------------------TMS570_CRCSCOUNT_REG2-------------------*/
     307/*-------------------TMS570_CRC_SCOUNT_REG2-------------------*/
    332308/* field: CRC_SEC_COUNT2 - Channel 2 Sector Counter Preload Register. */
    333309#define TMS570_CRC_SCOUNT_REG2_CRC_SEC_COUNT2(val) BSP_FLD32(val,0, 15)
     
    336312
    337313
    338 /*-------------------TMS570_CRCCURSEC_REG2-------------------*/
     314/*-------------------TMS570_CRC_CURSEC_REG2-------------------*/
    339315/* field: CRC_CURSEC2 - Channel 2 Current Sector ID Register. */
    340316#define TMS570_CRC_CURSEC_REG2_CRC_CURSEC2(val) BSP_FLD32(val,0, 15)
     
    343319
    344320
    345 /*---------------------TMS570_CRCWDTOPLD2---------------------*/
     321/*--------------------TMS570_CRC_WDTOPLD2--------------------*/
    346322/* field: CRC_WDTOPLD2 - Channel 2 Watchdog Timeout Counter Preload Register. */
    347323#define TMS570_CRC_WDTOPLD2_CRC_WDTOPLD2(val) BSP_FLD32(val,0, 23)
     
    350326
    351327
    352 /*---------------------TMS570_CRCBCTOPLD2---------------------*/
     328/*--------------------TMS570_CRC_BCTOPLD2--------------------*/
    353329/* field: CRC_BCTOPLD2 - Channel 2 Block Complete Timeout Counter Preload Register. */
    354330#define TMS570_CRC_BCTOPLD2_CRC_BCTOPLD2(val) BSP_FLD32(val,0, 23)
     
    357333
    358334
    359 /*-------------------TMS570_CRCPSA_SIGREGL2-------------------*/
     335/*------------------TMS570_CRC_PSA_SIGREGL2------------------*/
    360336/* field: PSASIG2 - Channel 2 PSA Signature Low Register. */
    361 #define TMS570_CRC_PSA_SIGREGL2_PSASIG2(val) BSP_FLD32(val,0, 31)
    362 #define TMS570_CRC_PSA_SIGREGL2_PSASIG2_GET(reg) BSP_FLD32GET(reg,0, 31)
    363 #define TMS570_CRC_PSA_SIGREGL2_PSASIG2_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
    364 
    365 
    366 /*-------------------TMS570_CRCPSA_SIGREGH2-------------------*/
     337/* Whole 32 bits */
     338
     339/*------------------TMS570_CRC_PSA_SIGREGH2------------------*/
    367340/* field: PSASIG2 - Channel 2 PSA Signature High Register. */
    368 #define TMS570_CRC_PSA_SIGREGH2_PSASIG2(val) BSP_FLD32(val,0, 31)
    369 #define TMS570_CRC_PSA_SIGREGH2_PSASIG2_GET(reg) BSP_FLD32GET(reg,0, 31)
    370 #define TMS570_CRC_PSA_SIGREGH2_PSASIG2_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
    371 
    372 
    373 /*----------------------TMS570_CRCREGL2----------------------*/
     341/* Whole 32 bits */
     342
     343/*----------------------TMS570_CRC_REGL2----------------------*/
    374344/* field: CRC2 - stored at CRC2[31:0] register. */
    375 #define TMS570_CRC_REGL2_CRC2(val) BSP_FLD32(val,0, 31)
    376 #define TMS570_CRC_REGL2_CRC2_GET(reg) BSP_FLD32GET(reg,0, 31)
    377 #define TMS570_CRC_REGL2_CRC2_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
    378 
    379 
    380 /*----------------------TMS570_CRCREGH2----------------------*/
     345/* Whole 32 bits */
     346
     347/*----------------------TMS570_CRC_REGH2----------------------*/
    381348/* field: CRC2 - Channel 2 CRC Value High Register. */
    382 #define TMS570_CRC_REGH2_CRC2(val) BSP_FLD32(val,0, 31)
    383 #define TMS570_CRC_REGH2_CRC2_GET(reg) BSP_FLD32GET(reg,0, 31)
    384 #define TMS570_CRC_REGH2_CRC2_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
    385 
    386 
    387 /*-----------------TMS570_CRCPSA_SECSIGREGL2-----------------*/
     349/* Whole 32 bits */
     350
     351/*-----------------TMS570_CRC_PSA_SECSIGREGL2-----------------*/
    388352/* field: PSASECSIG2 - Channel 2 PSA Sector Signature Low Register. */
    389 #define TMS570_CRC_PSA_SECSIGREGL2_PSASECSIG2(val) BSP_FLD32(val,0, 31)
    390 #define TMS570_CRC_PSA_SECSIGREGL2_PSASECSIG2_GET(reg) BSP_FLD32GET(reg,0, 31)
    391 #define TMS570_CRC_PSA_SECSIGREGL2_PSASECSIG2_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
    392 
    393 
    394 /*-----------------TMS570_CRCPSA_SECSIGREGH2-----------------*/
     353/* Whole 32 bits */
     354
     355/*-----------------TMS570_CRC_PSA_SECSIGREGH2-----------------*/
    395356/* field: PSASECSIG2 - Channel 2 PSA Sector Signature High Register. */
    396 #define TMS570_CRC_PSA_SECSIGREGH2_PSASECSIG2(val) BSP_FLD32(val,0, 31)
    397 #define TMS570_CRC_PSA_SECSIGREGH2_PSASECSIG2_GET(reg) BSP_FLD32GET(reg,0, 31)
    398 #define TMS570_CRC_PSA_SECSIGREGH2_PSASECSIG2_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
    399 
    400 
    401 /*------------------TMS570_CRCRAW_DATAREGL2------------------*/
     357/* Whole 32 bits */
     358
     359/*------------------TMS570_CRC_RAW_DATAREGL2------------------*/
    402360/* field: RAW_DATA2 - Channel 2 Raw Data Low Register. This register contains bits 31:0 of the uncompressed raw data.. */
    403 #define TMS570_CRC_RAW_DATAREGL2_RAW_DATA2(val) BSP_FLD32(val,0, 31)
    404 #define TMS570_CRC_RAW_DATAREGL2_RAW_DATA2_GET(reg) BSP_FLD32GET(reg,0, 31)
    405 #define TMS570_CRC_RAW_DATAREGL2_RAW_DATA2_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
    406 
    407 
    408 /*------------------TMS570_CRCRAW_DATAREGH2------------------*/
     361/* Whole 32 bits */
     362
     363/*------------------TMS570_CRC_RAW_DATAREGH2------------------*/
    409364/* field: RAW_DATA2 - Channel 2 Raw Data High Register. This register contains bits 63:32 of the uncompressed raw data.. */
    410 #define TMS570_CRC_RAW_DATAREGH2_RAW_DATA2(val) BSP_FLD32(val,0, 31)
    411 #define TMS570_CRC_RAW_DATAREGH2_RAW_DATA2_GET(reg) BSP_FLD32GET(reg,0, 31)
    412 #define TMS570_CRC_RAW_DATAREGH2_RAW_DATA2_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
    413 
    414 
    415 /*---------------------TMS570_CRCBUS_SEL---------------------*/
     365/* Whole 32 bits */
     366
     367/*---------------------TMS570_CRC_BUS_SEL---------------------*/
    416368/* field: MEn - Enable/disables the tracing of Peripheral Bus Master */
    417 #define TMS570_CRC_BUS_SEL_MEn BSP_FLD32(2)
     369#define TMS570_CRC_BUS_SEL_MEn BSP_BIT32(2)
    418370
    419371/* field: DTCMEn - Enable/disables the tracing of data TCM */
    420 #define TMS570_CRC_BUS_SEL_DTCMEn BSP_FLD32(1)
     372#define TMS570_CRC_BUS_SEL_DTCMEn BSP_BIT32(1)
    421373
    422374/* field: ITCMEn - Enable/disables the tracing of instruction TCM */
    423 #define TMS570_CRC_BUS_SEL_ITCMEn BSP_FLD32(0)
    424 
    425 
    426 
    427 #endif /* LIBBSP_ARM_tms570_CRC */
     375#define TMS570_CRC_BUS_SEL_ITCMEn BSP_BIT32(0)
     376
     377
     378
     379#endif /* LIBBSP_ARM_TMS570_CRC */
  • c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_dcan.h

    r3f923fd2 r9a84f983  
    3737 * either expressed or implied, of the FreeBSD Project.
    3838*/
    39 #ifndef LIBBSP_ARM_tms570_DCAN
    40 #define LIBBSP_ARM_tms570_DCAN
     39#ifndef LIBBSP_ARM_TMS570_DCAN
     40#define LIBBSP_ARM_TMS570_DCAN
    4141
    4242#include <bsp/utility.h>
     
    9292
    9393
    94 /*-----------------------TMS570_DCANCTL-----------------------*/
     94/*----------------------TMS570_DCAN_CTL----------------------*/
    9595/* field: WUBA - Automatic wake up on bus activity when in local power down mode */
    96 #define TMS570_DCAN_CTL_WUBA BSP_FLD32(25)
     96#define TMS570_DCAN_CTL_WUBA BSP_BIT32(25)
    9797
    9898/* field: PDR - Request for local low power down mode */
    99 #define TMS570_DCAN_CTL_PDR BSP_FLD32(24)
     99#define TMS570_DCAN_CTL_PDR BSP_BIT32(24)
    100100
    101101/* field: DE3 - Enable DMA request line for IF3 */
    102 #define TMS570_DCAN_CTL_DE3 BSP_FLD32(20)
     102#define TMS570_DCAN_CTL_DE3 BSP_BIT32(20)
    103103
    104104/* field: DE2 - Enable DMA request line for IF2 */
    105 #define TMS570_DCAN_CTL_DE2 BSP_FLD32(19)
     105#define TMS570_DCAN_CTL_DE2 BSP_BIT32(19)
    106106
    107107/* field: DE1 - Enable DMA request line for IF1 */
    108 #define TMS570_DCAN_CTL_DE1 BSP_FLD32(18)
     108#define TMS570_DCAN_CTL_DE1 BSP_BIT32(18)
    109109
    110110/* field: IE1 - Interrupt line 1 Enable */
    111 #define TMS570_DCAN_CTL_IE1 BSP_FLD32(17)
     111#define TMS570_DCAN_CTL_IE1 BSP_BIT32(17)
    112112
    113113/* field: InitDbg - Internal Init state while debug access */
    114 #define TMS570_DCAN_CTL_InitDbg BSP_FLD32(16)
     114#define TMS570_DCAN_CTL_InitDbg BSP_BIT32(16)
    115115
    116116/* field: SWR - SW Reset Enable */
    117 #define TMS570_DCAN_CTL_SWR BSP_FLD32(15)
     117#define TMS570_DCAN_CTL_SWR BSP_BIT32(15)
    118118
    119119/* field: PMD - Parity on/off */
     
    123123
    124124/* field: ABO - Auto-Bus-On Enable */
    125 #define TMS570_DCAN_CTL_ABO BSP_FLD32(9)
     125#define TMS570_DCAN_CTL_ABO BSP_BIT32(9)
    126126
    127127/* field: IDS - Interruption Debug Support Enable */
    128 #define TMS570_DCAN_CTL_IDS BSP_FLD32(8)
     128#define TMS570_DCAN_CTL_IDS BSP_BIT32(8)
    129129
    130130/* field: Test - Test Mode Enable */
    131 #define TMS570_DCAN_CTL_Test BSP_FLD32(7)
     131#define TMS570_DCAN_CTL_Test BSP_BIT32(7)
    132132
    133133/* field: CCE - Configuration Change Enable */
    134 #define TMS570_DCAN_CTL_CCE BSP_FLD32(6)
     134#define TMS570_DCAN_CTL_CCE BSP_BIT32(6)
    135135
    136136/* field: DAR - Disable Automatic Retransmission */
    137 #define TMS570_DCAN_CTL_DAR BSP_FLD32(5)
     137#define TMS570_DCAN_CTL_DAR BSP_BIT32(5)
    138138
    139139/* field: EIE - Error Interrupt Enable */
    140 #define TMS570_DCAN_CTL_EIE BSP_FLD32(3)
     140#define TMS570_DCAN_CTL_EIE BSP_BIT32(3)
    141141
    142142/* field: SIE - Status Change Interrupt Enable */
    143 #define TMS570_DCAN_CTL_SIE BSP_FLD32(2)
     143#define TMS570_DCAN_CTL_SIE BSP_BIT32(2)
    144144
    145145/* field: IE0 - Interrupt line 0 Enable */
    146 #define TMS570_DCAN_CTL_IE0 BSP_FLD32(1)
     146#define TMS570_DCAN_CTL_IE0 BSP_BIT32(1)
    147147
    148148/* field: Init - Initialization */
    149 #define TMS570_DCAN_CTL_Init BSP_FLD32(0)
    150 
    151 
    152 /*-----------------------TMS570_DCANES-----------------------*/
     149#define TMS570_DCAN_CTL_Init BSP_BIT32(0)
     150
     151
     152/*-----------------------TMS570_DCAN_ES-----------------------*/
    153153/* field: PDA - Local power down mode acknowledge */
    154 #define TMS570_DCAN_ES_PDA BSP_FLD32(10)
     154#define TMS570_DCAN_ES_PDA BSP_BIT32(10)
    155155
    156156/* field: WakeUp_Pnd - Wake Up Pending */
    157 #define TMS570_DCAN_ES_WakeUp_Pnd BSP_FLD32(9)
     157#define TMS570_DCAN_ES_WakeUp_Pnd BSP_BIT32(9)
    158158
    159159/* field: PER - Parity Error Detected */
    160 #define TMS570_DCAN_ES_PER BSP_FLD32(8)
     160#define TMS570_DCAN_ES_PER BSP_BIT32(8)
    161161
    162162/* field: BOff - Bus-Off State */
    163 #define TMS570_DCAN_ES_BOff BSP_FLD32(7)
     163#define TMS570_DCAN_ES_BOff BSP_BIT32(7)
    164164
    165165/* field: EWarn - Warning State */
    166 #define TMS570_DCAN_ES_EWarn BSP_FLD32(6)
     166#define TMS570_DCAN_ES_EWarn BSP_BIT32(6)
    167167
    168168/* field: EPass - Error Passive State */
    169 #define TMS570_DCAN_ES_EPass BSP_FLD32(5)
     169#define TMS570_DCAN_ES_EPass BSP_BIT32(5)
    170170
    171171/* field: RxOK - Received a message successfully */
    172 #define TMS570_DCAN_ES_RxOK BSP_FLD32(4)
     172#define TMS570_DCAN_ES_RxOK BSP_BIT32(4)
    173173
    174174/* field: TxOK - Transmitted a message successfully */
    175 #define TMS570_DCAN_ES_TxOK BSP_FLD32(3)
     175#define TMS570_DCAN_ES_TxOK BSP_BIT32(3)
    176176
    177177/* field: LEC - Last Error Code */
     
    181181
    182182
    183 /*----------------------TMS570_DCANERRC----------------------*/
     183/*----------------------TMS570_DCAN_ERRC----------------------*/
    184184/* field: RP - Receive Error Passive */
    185 #define TMS570_DCAN_ERRC_RP BSP_FLD32(15)
     185#define TMS570_DCAN_ERRC_RP BSP_BIT32(15)
    186186
    187187/* field: REC - Receive Error Counter. Actual state of the Receive Error Counter. (values from 0 to 255). */
     
    196196
    197197
    198 /*-----------------------TMS570_DCANBTR-----------------------*/
     198/*----------------------TMS570_DCAN_BTR----------------------*/
    199199/* field: BRPE - Baud Rate Prescaler Extension. */
    200200#define TMS570_DCAN_BTR_BRPE(val) BSP_FLD32(val,16, 19)
     
    223223
    224224
    225 /*-----------------------TMS570_DCANINT-----------------------*/
     225/*----------------------TMS570_DCAN_INT----------------------*/
    226226/* field: Int1ID - Interrupt 1 Identifier (indicates the message object with the highest pending interrupt) */
    227227#define TMS570_DCAN_INT_Int1ID(val) BSP_FLD32(val,16, 23)
     
    235235
    236236
    237 /*----------------------TMS570_DCANTEST----------------------*/
     237/*----------------------TMS570_DCAN_TEST----------------------*/
    238238/* field: RDA - RAM Direct Access Enable */
    239 #define TMS570_DCAN_TEST_RDA BSP_FLD32(9)
     239#define TMS570_DCAN_TEST_RDA BSP_BIT32(9)
    240240
    241241/* field: EXL - External Loop Back Mode */
    242 #define TMS570_DCAN_TEST_EXL BSP_FLD32(8)
     242#define TMS570_DCAN_TEST_EXL BSP_BIT32(8)
    243243
    244244/* field: Rx - Receive Pin. Monitors the actual value of the CAN_RX pin. */
    245 #define TMS570_DCAN_TEST_Rx BSP_FLD32(7)
     245#define TMS570_DCAN_TEST_Rx BSP_BIT32(7)
    246246
    247247/* field: Tx - Control of CAN_TX pin */
     
    251251
    252252/* field: LBack - Loop Back Mode */
    253 #define TMS570_DCAN_TEST_LBack BSP_FLD32(4)
     253#define TMS570_DCAN_TEST_LBack BSP_BIT32(4)
    254254
    255255/* field: Silent - Silent Mode */
    256 #define TMS570_DCAN_TEST_Silent BSP_FLD32(3)
    257 
    258 
    259 /*----------------------TMS570_DCANPERR----------------------*/
     256#define TMS570_DCAN_TEST_Silent BSP_BIT32(3)
     257
     258
     259/*----------------------TMS570_DCAN_PERR----------------------*/
    260260/* field: Word_Number - Word number where parity error has been detected */
    261261#define TMS570_DCAN_PERR_Word_Number(val) BSP_FLD32(val,8, 10)
     
    269269
    270270
    271 /*----------------------TMS570_DCANABOTR----------------------*/
     271/*---------------------TMS570_DCAN_ABOTR---------------------*/
    272272/* field: ABO_Time - Number of VBUS clock cycles before a Bus-Off recovery sequence is */
    273 #define TMS570_DCAN_ABOTR_ABO_Time(val) BSP_FLD32(val,0, 31)
    274 #define TMS570_DCAN_ABOTR_ABO_Time_GET(reg) BSP_FLD32GET(reg,0, 31)
    275 #define TMS570_DCAN_ABOTR_ABO_Time_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
    276 
    277 
    278 /*----------------------TMS570_DCANTXRQX----------------------*/
     273/* Whole 32 bits */
     274
     275/*---------------------TMS570_DCAN_TXRQX---------------------*/
    279276/* field: TxRqstReg8 - TxRqstReg8 */
    280277#define TMS570_DCAN_TXRQX_TxRqstReg8(val) BSP_FLD32(val,14, 15)
     
    318315
    319316
    320 /*----------------------TMS570_DCANTXRQx----------------------*/
     317/*---------------------TMS570_DCAN_TXRQx---------------------*/
    321318/* field: TxRqsX - Transmission Request Bits (for all message objects) */
    322 #define TMS570_DCAN_TXRQx_TxRqsX(val) BSP_FLD32(val,0, 31)
    323 #define TMS570_DCAN_TXRQx_TxRqsX_GET(reg) BSP_FLD32GET(reg,0, 31)
    324 #define TMS570_DCAN_TXRQx_TxRqsX_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
    325 
    326 
    327 /*---------------------TMS570_DCANNWDATX---------------------*/
     319/* Whole 32 bits */
     320
     321/*---------------------TMS570_DCAN_NWDATX---------------------*/
    328322/* field: NewDatReg8 - TxRqstReg8 */
    329323#define TMS570_DCAN_NWDATX_NewDatReg8(val) BSP_FLD32(val,14, 15)
     
    367361
    368362
    369 /*---------------------TMS570_DCANNWDATx---------------------*/
     363/*---------------------TMS570_DCAN_NWDATx---------------------*/
    370364/* field: NewDatX - New Data Bits (for all message objects) */
    371 #define TMS570_DCAN_NWDATx_NewDatX(val) BSP_FLD32(val,0, 31)
    372 #define TMS570_DCAN_NWDATx_NewDatX_GET(reg) BSP_FLD32GET(reg,0, 31)
    373 #define TMS570_DCAN_NWDATx_NewDatX_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
    374 
    375 
    376 /*---------------------TMS570_DCANINTPNDX---------------------*/
     365/* Whole 32 bits */
     366
     367/*--------------------TMS570_DCAN_INTPNDX--------------------*/
    377368/* field: IntPndReg8 - If at least one of the IntPnd bits of these message objects are set, the corresponding bit in the Interrupt Pending X Register will be set. */
    378369#define TMS570_DCAN_INTPNDX_IntPndReg8(val) BSP_FLD32(val,14, 15)
     
    416407
    417408
    418 /*---------------------TMS570_DCANINTPNDx---------------------*/
     409/*--------------------TMS570_DCAN_INTPNDx--------------------*/
    419410/* field: IntPndX - Interrupt Pending Bits (for all message objects) */
    420 #define TMS570_DCAN_INTPNDx_IntPndX(val) BSP_FLD32(val,0, 31)
    421 #define TMS570_DCAN_INTPNDx_IntPndX_GET(reg) BSP_FLD32GET(reg,0, 31)
    422 #define TMS570_DCAN_INTPNDx_IntPndX_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
    423 
    424 
    425 /*---------------------TMS570_DCANMSGVALX---------------------*/
     411/* Whole 32 bits */
     412
     413/*--------------------TMS570_DCAN_MSGVALX--------------------*/
    426414/* field: MsgValReg8 - If at least one of the IntPnd bits of these message objects are set, the corresponding bit in the Message Valid X Register will be set. */
    427415#define TMS570_DCAN_MSGVALX_MsgValReg8(val) BSP_FLD32(val,14, 15)
     
    465453
    466454
    467 /*---------------------TMS570_DCANMSGVALx---------------------*/
     455/*--------------------TMS570_DCAN_MSGVALx--------------------*/
    468456/* field: MsgVal1To32 - Message Valid Bits (for all message objects) */
    469 #define TMS570_DCAN_MSGVALx_MsgVal1To32(val) BSP_FLD32(val,0, 31)
    470 #define TMS570_DCAN_MSGVALx_MsgVal1To32_GET(reg) BSP_FLD32GET(reg,0, 31)
    471 #define TMS570_DCAN_MSGVALx_MsgVal1To32_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
    472 
    473 
    474 /*---------------------TMS570_DCANINTMUXx---------------------*/
     457/* Whole 32 bits */
     458
     459/*--------------------TMS570_DCAN_INTMUXx--------------------*/
    475460/* field: IntMux1To32 - Multiplexes IntPnd value to either DCAN0INT or DCAN1INT interrupt lines. */
    476 #define TMS570_DCAN_INTMUXx_IntMux1To32(val) BSP_FLD32(val,0, 31)
    477 #define TMS570_DCAN_INTMUXx_IntMux1To32_GET(reg) BSP_FLD32GET(reg,0, 31)
    478 #define TMS570_DCAN_INTMUXx_IntMux1To32_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
    479 
    480 
    481 /*---------------------TMS570_DCANIF1CMD---------------------*/
     461/* Whole 32 bits */
     462
     463/*---------------------TMS570_DCAN_IF1CMD---------------------*/
    482464/* field: WR_RD - Write/Read */
    483 #define TMS570_DCAN_IF1CMD_WR_RD BSP_FLD32(23)
     465#define TMS570_DCAN_IF1CMD_WR_RD BSP_BIT32(23)
    484466
    485467/* field: Mask - Access Mask bits */
    486 #define TMS570_DCAN_IF1CMD_Mask BSP_FLD32(22)
     468#define TMS570_DCAN_IF1CMD_Mask BSP_BIT32(22)
    487469
    488470/* field: Arb - Access Arbitration bits */
    489 #define TMS570_DCAN_IF1CMD_Arb BSP_FLD32(21)
     471#define TMS570_DCAN_IF1CMD_Arb BSP_BIT32(21)
    490472
    491473/* field: Control - Access Control bits */
    492 #define TMS570_DCAN_IF1CMD_Control BSP_FLD32(20)
     474#define TMS570_DCAN_IF1CMD_Control BSP_BIT32(20)
    493475
    494476/* field: ClrIntPnd - Clear Interrupt Pending bit */
    495 #define TMS570_DCAN_IF1CMD_ClrIntPnd BSP_FLD32(19)
     477#define TMS570_DCAN_IF1CMD_ClrIntPnd BSP_BIT32(19)
    496478
    497479/* field: TxRqst_NewDat - Access Transmission Request bit */
    498 #define TMS570_DCAN_IF1CMD_TxRqst_NewDat BSP_FLD32(18)
     480#define TMS570_DCAN_IF1CMD_TxRqst_NewDat BSP_BIT32(18)
    499481
    500482/* field: Data_A - Access Data Bytes 0-3 */
    501 #define TMS570_DCAN_IF1CMD_Data_A BSP_FLD32(17)
     483#define TMS570_DCAN_IF1CMD_Data_A BSP_BIT32(17)
    502484
    503485/* field: Data_B - Access Data Bytes 4-7 */
    504 #define TMS570_DCAN_IF1CMD_Data_B BSP_FLD32(16)
     486#define TMS570_DCAN_IF1CMD_Data_B BSP_BIT32(16)
    505487
    506488/* field: Busy - Busy flag */
    507 #define TMS570_DCAN_IF1CMD_Busy BSP_FLD32(15)
     489#define TMS570_DCAN_IF1CMD_Busy BSP_BIT32(15)
    508490
    509491/* field: DMA_Active - Activation of DMA feature for subsequent internal IF1/IF2 update */
    510 #define TMS570_DCAN_IF1CMD_DMA_Active BSP_FLD32(14)
     492#define TMS570_DCAN_IF1CMD_DMA_Active BSP_BIT32(14)
    511493
    512494/* field: Message_Number - Number of message object in Message RAM that is used for data transfer */
     
    516498
    517499
    518 /*---------------------TMS570_DCANIF1MSK---------------------*/
     500/*---------------------TMS570_DCAN_IF1MSK---------------------*/
    519501/* field: MXtd - Mask Extended Identifier */
    520 #define TMS570_DCAN_IF1MSK_MXtd BSP_FLD32(31)
     502#define TMS570_DCAN_IF1MSK_MXtd BSP_BIT32(31)
    521503
    522504/* field: MDir - Mask Message Direction */
    523 #define TMS570_DCAN_IF1MSK_MDir BSP_FLD32(30)
     505#define TMS570_DCAN_IF1MSK_MDir BSP_BIT32(30)
    524506
    525507/* field: Msk - Identifier Mask */
     
    529511
    530512
    531 /*---------------------TMS570_DCANIF1ARB---------------------*/
     513/*---------------------TMS570_DCAN_IF1ARB---------------------*/
    532514/* field: MsgVal - Message Valid */
    533 #define TMS570_DCAN_IF1ARB_MsgVal BSP_FLD32(31)
     515#define TMS570_DCAN_IF1ARB_MsgVal BSP_BIT32(31)
    534516
    535517/* field: Xtd - Extended Identifier */
    536 #define TMS570_DCAN_IF1ARB_Xtd BSP_FLD32(30)
     518#define TMS570_DCAN_IF1ARB_Xtd BSP_BIT32(30)
    537519
    538520/* field: Dir - Message direction */
    539 #define TMS570_DCAN_IF1ARB_Dir BSP_FLD32(29)
     521#define TMS570_DCAN_IF1ARB_Dir BSP_BIT32(29)
    540522
    541523/* field: ID - Message Identifier */
     
    545527
    546528
    547 /*---------------------TMS570_DCANIF1MCTL---------------------*/
     529/*--------------------TMS570_DCAN_IF1MCTL--------------------*/
    548530/* field: NewDat - New Data */
    549 #define TMS570_DCAN_IF1MCTL_NewDat BSP_FLD32(15)
     531#define TMS570_DCAN_IF1MCTL_NewDat BSP_BIT32(15)
    550532
    551533/* field: MsgLst - Message Lost (only valid for message objects with direction = receive) */
    552 #define TMS570_DCAN_IF1MCTL_MsgLst BSP_FLD32(14)
     534#define TMS570_DCAN_IF1MCTL_MsgLst BSP_BIT32(14)
    553535
    554536/* field: IntPnd - Interrupt Pending */
    555 #define TMS570_DCAN_IF1MCTL_IntPnd BSP_FLD32(13)
     537#define TMS570_DCAN_IF1MCTL_IntPnd BSP_BIT32(13)
    556538
    557539/* field: UMask - Use Acceptance Mask */
    558 #define TMS570_DCAN_IF1MCTL_UMask BSP_FLD32(12)
     540#define TMS570_DCAN_IF1MCTL_UMask BSP_BIT32(12)
    559541
    560542/* field: TxIE - Transmit Interrupt Enable */
    561 #define TMS570_DCAN_IF1MCTL_TxIE BSP_FLD32(11)
     543#define TMS570_DCAN_IF1MCTL_TxIE BSP_BIT32(11)
    562544
    563545/* field: RxIE - Receive Interrupt Enable */
    564 #define TMS570_DCAN_IF1MCTL_RxIE BSP_FLD32(10)
     546#define TMS570_DCAN_IF1MCTL_RxIE BSP_BIT32(10)
    565547
    566548/* field: RmtEn - Remote Enable */
    567 #define TMS570_DCAN_IF1MCTL_RmtEn BSP_FLD32(9)
     549#define TMS570_DCAN_IF1MCTL_RmtEn BSP_BIT32(9)
    568550
    569551/* field: TxRqst - Transmit Request */
    570 #define TMS570_DCAN_IF1MCTL_TxRqst BSP_FLD32(8)
     552#define TMS570_DCAN_IF1MCTL_TxRqst BSP_BIT32(8)
    571553
    572554/* field: EoB - Data Frame has 0-8 data bits */
    573 #define TMS570_DCAN_IF1MCTL_EoB BSP_FLD32(7)
     555#define TMS570_DCAN_IF1MCTL_EoB BSP_BIT32(7)
    574556
    575557/* field: DLC - Data Length Code */
     
    579561
    580562
    581 /*---------------------TMS570_DCANIF1DATA---------------------*/
     563/*--------------------TMS570_DCAN_IF1DATA--------------------*/
    582564/* field: Data0 - Data 0 */
    583565#define TMS570_DCAN_IF1DATA_Data0(val) BSP_FLD32(val,0, 7)
     
    601583
    602584
    603 /*---------------------TMS570_DCANIF1DATB---------------------*/
     585/*--------------------TMS570_DCAN_IF1DATB--------------------*/
    604586/* field: Data4 - Data 4 */
    605587#define TMS570_DCAN_IF1DATB_Data4(val) BSP_FLD32(val,0, 7)
     
    623605
    624606
    625 /*---------------------TMS570_DCANIF2CMD---------------------*/
     607/*---------------------TMS570_DCAN_IF2CMD---------------------*/
    626608/* field: WR_RD - Write/Read */
    627 #define TMS570_DCAN_IF2CMD_WR_RD BSP_FLD32(23)
     609#define TMS570_DCAN_IF2CMD_WR_RD BSP_BIT32(23)
    628610
    629611/* field: Mask - Access Mask bits */
    630 #define TMS570_DCAN_IF2CMD_Mask BSP_FLD32(22)
     612#define TMS570_DCAN_IF2CMD_Mask BSP_BIT32(22)
    631613
    632614/* field: Arb - Access Arbitration bits */
    633 #define TMS570_DCAN_IF2CMD_Arb BSP_FLD32(21)
     615#define TMS570_DCAN_IF2CMD_Arb BSP_BIT32(21)
    634616
    635617/* field: Control - Access Control bits */
    636 #define TMS570_DCAN_IF2CMD_Control BSP_FLD32(20)
     618#define TMS570_DCAN_IF2CMD_Control BSP_BIT32(20)
    637619
    638620/* field: ClrIntPnd - Clear Interrupt Pending bit */
    639 #define TMS570_DCAN_IF2CMD_ClrIntPnd BSP_FLD32(19)
     621#define TMS570_DCAN_IF2CMD_ClrIntPnd BSP_BIT32(19)
    640622
    641623/* field: TxRqst_NewDat - Access Transmission Request bit */
    642 #define TMS570_DCAN_IF2CMD_TxRqst_NewDat BSP_FLD32(18)
     624#define TMS570_DCAN_IF2CMD_TxRqst_NewDat BSP_BIT32(18)
    643625
    644626/* field: Data_A - Access Data Bytes 0-3 */
    645 #define TMS570_DCAN_IF2CMD_Data_A BSP_FLD32(17)
     627#define TMS570_DCAN_IF2CMD_Data_A BSP_BIT32(17)
    646628
    647629/* field: Data_B - Access Data Bytes 4-7 */
    648 #define TMS570_DCAN_IF2CMD_Data_B BSP_FLD32(16)
     630#define TMS570_DCAN_IF2CMD_Data_B BSP_BIT32(16)
    649631
    650632/* field: Busy - Busy flag */
    651 #define TMS570_DCAN_IF2CMD_Busy BSP_FLD32(15)
     633#define TMS570_DCAN_IF2CMD_Busy BSP_BIT32(15)
    652634
    653635/* field: DMA_Active - Activation of DMA feature for subsequent internal IF1/IF2 update */
    654 #define TMS570_DCAN_IF2CMD_DMA_Active BSP_FLD32(14)
     636#define TMS570_DCAN_IF2CMD_DMA_Active BSP_BIT32(14)
    655637
    656638/* field: Message_Number - Number of message object in Message RAM that is used for data transfer */
     
    660642
    661643
    662 /*---------------------TMS570_DCANIF2MSK---------------------*/
     644/*---------------------TMS570_DCAN_IF2MSK---------------------*/
    663645/* field: MXtd - Mask Extended Identifier */
    664 #define TMS570_DCAN_IF2MSK_MXtd BSP_FLD32(31)
     646#define TMS570_DCAN_IF2MSK_MXtd BSP_BIT32(31)
    665647
    666648/* field: MDir - Mask Message Direction */
    667 #define TMS570_DCAN_IF2MSK_MDir BSP_FLD32(30)
     649#define TMS570_DCAN_IF2MSK_MDir BSP_BIT32(30)
    668650
    669651/* field: Msk - Identifier Mask */
     
    673655
    674656
    675 /*---------------------TMS570_DCANIF2ARB---------------------*/
     657/*---------------------TMS570_DCAN_IF2ARB---------------------*/
    676658/* field: MsgVal - Message Valid */
    677 #define TMS570_DCAN_IF2ARB_MsgVal BSP_FLD32(31)
     659#define TMS570_DCAN_IF2ARB_MsgVal BSP_BIT32(31)
    678660
    679661/* field: Xtd - Extended Identifier */
    680 #define TMS570_DCAN_IF2ARB_Xtd BSP_FLD32(30)
     662#define TMS570_DCAN_IF2ARB_Xtd BSP_BIT32(30)
    681663
    682664/* field: Dir - Message direction */
    683 #define TMS570_DCAN_IF2ARB_Dir BSP_FLD32(29)
     665#define TMS570_DCAN_IF2ARB_Dir BSP_BIT32(29)
    684666
    685667/* field: ID - Message Identifier */
     
    689671
    690672
    691 /*---------------------TMS570_DCANIF2MCTL---------------------*/
     673/*--------------------TMS570_DCAN_IF2MCTL--------------------*/
    692674/* field: NewDat - New Data */
    693 #define TMS570_DCAN_IF2MCTL_NewDat BSP_FLD32(15)
     675#define TMS570_DCAN_IF2MCTL_NewDat BSP_BIT32(15)
    694676
    695677/* field: MsgLst - Message Lost (only valid for message objects with direction = receive) */
    696 #define TMS570_DCAN_IF2MCTL_MsgLst BSP_FLD32(14)
     678#define TMS570_DCAN_IF2MCTL_MsgLst BSP_BIT32(14)
    697679
    698680/* field: IntPnd - Interrupt Pending */
    699 #define TMS570_DCAN_IF2MCTL_IntPnd BSP_FLD32(13)
     681#define TMS570_DCAN_IF2MCTL_IntPnd BSP_BIT32(13)
    700682
    701683/* field: UMask - Use Acceptance Mask */
    702 #define TMS570_DCAN_IF2MCTL_UMask BSP_FLD32(12)
     684#define TMS570_DCAN_IF2MCTL_UMask BSP_BIT32(12)
    703685
    704686/* field: TxIE - Transmit Interrupt Enable */
    705 #define TMS570_DCAN_IF2MCTL_TxIE BSP_FLD32(11)
     687#define TMS570_DCAN_IF2MCTL_TxIE BSP_BIT32(11)
    706688
    707689/* field: RxIE - Receive Interrupt Enable */
    708 #define TMS570_DCAN_IF2MCTL_RxIE BSP_FLD32(10)
     690#define TMS570_DCAN_IF2MCTL_RxIE BSP_BIT32(10)
    709691
    710692/* field: RmtEn - Remote Enable */
    711 #define TMS570_DCAN_IF2MCTL_RmtEn BSP_FLD32(9)
     693#define TMS570_DCAN_IF2MCTL_RmtEn BSP_BIT32(9)
    712694
    713695/* field: TxRqst - Transmit Request */
    714 #define TMS570_DCAN_IF2MCTL_TxRqst BSP_FLD32(8)
     696#define TMS570_DCAN_IF2MCTL_TxRqst BSP_BIT32(8)
    715697
    716698/* field: EoB - Data Frame has 0-8 data bits */
    717 #define TMS570_DCAN_IF2MCTL_EoB BSP_FLD32(7)
     699#define TMS570_DCAN_IF2MCTL_EoB BSP_BIT32(7)
    718700
    719701/* field: DLC - Data Length Code */
     
    723705
    724706
    725 /*---------------------TMS570_DCANIF2DATA---------------------*/
     707/*--------------------TMS570_DCAN_IF2DATA--------------------*/
    726708/* field: Data0 - Data 0 */
    727709#define TMS570_DCAN_IF2DATA_Data0(val) BSP_FLD32(val,0, 7)
     
    745727
    746728
    747 /*---------------------TMS570_DCANIF2DATB---------------------*/
     729/*--------------------TMS570_DCAN_IF2DATB--------------------*/
    748730/* field: Data4 - Data 4 */
    749731#define TMS570_DCAN_IF2DATB_Data4(val) BSP_FLD32(val,0, 7)
     
    767749
    768750
    769 /*---------------------TMS570_DCANIF3OBS---------------------*/
     751/*---------------------TMS570_DCAN_IF3OBS---------------------*/
    770752/* field: IF3_Upd - IF3 Update Data */
    771 #define TMS570_DCAN_IF3OBS_IF3_Upd BSP_FLD32(15)
     753#define TMS570_DCAN_IF3OBS_IF3_Upd BSP_BIT32(15)
    772754
    773755/* field: IF3_SDB - IF3 Status of Data B read access */
    774 #define TMS570_DCAN_IF3OBS_IF3_SDB BSP_FLD32(12)
     756#define TMS570_DCAN_IF3OBS_IF3_SDB BSP_BIT32(12)
    775757
    776758/* field: IF3_SDA - IF3 Status of Data A read access */
    777 #define TMS570_DCAN_IF3OBS_IF3_SDA BSP_FLD32(11)
     759#define TMS570_DCAN_IF3OBS_IF3_SDA BSP_BIT32(11)
    778760
    779761/* field: IF3_SC - IF3 Status of Control bits read access */
    780 #define TMS570_DCAN_IF3OBS_IF3_SC BSP_FLD32(10)
     762#define TMS570_DCAN_IF3OBS_IF3_SC BSP_BIT32(10)
    781763
    782764/* field: IF3_SA - IF3 Status of Arbitration data read access */
    783 #define TMS570_DCAN_IF3OBS_IF3_SA BSP_FLD32(9)
     765#define TMS570_DCAN_IF3OBS_IF3_SA BSP_BIT32(9)
    784766
    785767/* field: IF3_SM - IF3 Status of Mask data read access */
    786 #define TMS570_DCAN_IF3OBS_IF3_SM BSP_FLD32(8)
     768#define TMS570_DCAN_IF3OBS_IF3_SM BSP_BIT32(8)
    787769
    788770/* field: Data_B - Data B read observation */
    789 #define TMS570_DCAN_IF3OBS_Data_B BSP_FLD32(4)
     771#define TMS570_DCAN_IF3OBS_Data_B BSP_BIT32(4)
    790772
    791773/* field: Data_A - Data A read observation */
    792 #define TMS570_DCAN_IF3OBS_Data_A BSP_FLD32(3)
     774#define TMS570_DCAN_IF3OBS_Data_A BSP_BIT32(3)
    793775
    794776/* field: Ctrl - Ctrl read observation */
    795 #define TMS570_DCAN_IF3OBS_Ctrl BSP_FLD32(2)
     777#define TMS570_DCAN_IF3OBS_Ctrl BSP_BIT32(2)
    796778
    797779/* field: Arb - Arbitration data read observation */
    798 #define TMS570_DCAN_IF3OBS_Arb BSP_FLD32(1)
     780#define TMS570_DCAN_IF3OBS_Arb BSP_BIT32(1)
    799781
    800782/* field: Mask - Mask data read observation */
    801 #define TMS570_DCAN_IF3OBS_Mask BSP_FLD32(0)
    802 
    803 
    804 /*---------------------TMS570_DCANIF3MSK---------------------*/
     783#define TMS570_DCAN_IF3OBS_Mask BSP_BIT32(0)
     784
     785
     786/*---------------------TMS570_DCAN_IF3MSK---------------------*/
    805787/* field: MXtd - Mask Extended Identifier */
    806 #define TMS570_DCAN_IF3MSK_MXtd BSP_FLD32(31)
     788#define TMS570_DCAN_IF3MSK_MXtd BSP_BIT32(31)
    807789
    808790/* field: MDir - Mask Message Direction */
    809 #define TMS570_DCAN_IF3MSK_MDir BSP_FLD32(30)
     791#define TMS570_DCAN_IF3MSK_MDir BSP_BIT32(30)
    810792
    811793/* field: Msk - Identifier Mask */
     
    815797
    816798
    817 /*---------------------TMS570_DCANIF3ARB---------------------*/
     799/*---------------------TMS570_DCAN_IF3ARB---------------------*/
    818800/* field: MsgVal - Message Valid */
    819 #define TMS570_DCAN_IF3ARB_MsgVal BSP_FLD32(31)
     801#define TMS570_DCAN_IF3ARB_MsgVal BSP_BIT32(31)
    820802
    821803/* field: Xtd - Extended Identifier */
    822 #define TMS570_DCAN_IF3ARB_Xtd BSP_FLD32(30)
     804#define TMS570_DCAN_IF3ARB_Xtd BSP_BIT32(30)
    823805
    824806/* field: Dir - Message direction */
    825 #define TMS570_DCAN_IF3ARB_Dir BSP_FLD32(29)
     807#define TMS570_DCAN_IF3ARB_Dir BSP_BIT32(29)
    826808
    827809/* field: ID - Message Identifier */
     
    831813
    832814
    833 /*---------------------TMS570_DCANIF3MCTL---------------------*/
     815/*--------------------TMS570_DCAN_IF3MCTL--------------------*/
    834816/* field: NewDat - New Data */
    835 #define TMS570_DCAN_IF3MCTL_NewDat BSP_FLD32(15)
     817#define TMS570_DCAN_IF3MCTL_NewDat BSP_BIT32(15)
    836818
    837819/* field: MsgLst - Message Lost (only valid for message objects with direction = receive) */
    838 #define TMS570_DCAN_IF3MCTL_MsgLst BSP_FLD32(14)
     820#define TMS570_DCAN_IF3MCTL_MsgLst BSP_BIT32(14)
    839821
    840822/* field: IntPnd - Interrupt Pending */
    841 #define TMS570_DCAN_IF3MCTL_IntPnd BSP_FLD32(13)
     823#define TMS570_DCAN_IF3MCTL_IntPnd BSP_BIT32(13)
    842824
    843825/* field: UMask - Use Acceptance Mask */
    844 #define TMS570_DCAN_IF3MCTL_UMask BSP_FLD32(12)
     826#define TMS570_DCAN_IF3MCTL_UMask BSP_BIT32(12)
    845827
    846828/* field: TxIE - Transmit Interrupt Enable */
    847 #define TMS570_DCAN_IF3MCTL_TxIE BSP_FLD32(11)
     829#define TMS570_DCAN_IF3MCTL_TxIE BSP_BIT32(11)
    848830
    849831/* field: RxIE - Receive Interrupt Enable */
    850 #define TMS570_DCAN_IF3MCTL_RxIE BSP_FLD32(10)
     832#define TMS570_DCAN_IF3MCTL_RxIE BSP_BIT32(10)
    851833
    852834/* field: RmtEn - Remote Enable */
    853 #define TMS570_DCAN_IF3MCTL_RmtEn BSP_FLD32(9)
     835#define TMS570_DCAN_IF3MCTL_RmtEn BSP_BIT32(9)
    854836
    855837/* field: TxRqst - TxRqst */
    856 #define TMS570_DCAN_IF3MCTL_TxRqst BSP_FLD32(8)
     838#define TMS570_DCAN_IF3MCTL_TxRqst BSP_BIT32(8)
    857839
    858840/* field: EoB - End of Block */
    859 #define TMS570_DCAN_IF3MCTL_EoB BSP_FLD32(7)
     841#define TMS570_DCAN_IF3MCTL_EoB BSP_BIT32(7)
    860842
    861843/* field: DLC - Data Length Code */
     
    865847
    866848
    867 /*---------------------TMS570_DCANIF3DATA---------------------*/
     849/*--------------------TMS570_DCAN_IF3DATA--------------------*/
    868850/* field: Data0 - Data 0 */
    869851#define TMS570_DCAN_IF3DATA_Data0(val) BSP_FLD32(val,0, 7)
     
    887869
    888870
    889 /*---------------------TMS570_DCANIF3DATB---------------------*/
     871/*--------------------TMS570_DCAN_IF3DATB--------------------*/
    890872/* field: Data4 - Data 4 */
    891873#define TMS570_DCAN_IF3DATB_Data4(val) BSP_FLD32(val,0, 7)
     
    909891
    910892
    911 /*---------------------TMS570_DCANIF3UEy---------------------*/
     893/*---------------------TMS570_DCAN_IF3UEy---------------------*/
    912894/* field: IF3UpdEn - IF3 Update Enabled (for all message objects) */
    913 #define TMS570_DCAN_IF3UEy_IF3UpdEn(val) BSP_FLD32(val,0, 31)
    914 #define TMS570_DCAN_IF3UEy_IF3UpdEn_GET(reg) BSP_FLD32GET(reg,0, 31)
    915 #define TMS570_DCAN_IF3UEy_IF3UpdEn_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
    916 
    917 
    918 /*----------------------TMS570_DCANTIOC----------------------*/
     895/* Whole 32 bits */
     896
     897/*----------------------TMS570_DCAN_TIOC----------------------*/
    919898/* field: PU - CAN_TX Pullup/Pulldown select. This bit is only active when CAN_TX is configured to be an input. */
    920 #define TMS570_DCAN_TIOC_PU BSP_FLD32(18)
     899#define TMS570_DCAN_TIOC_PU BSP_BIT32(18)
    921900
    922901/* field: PD - CAN_TX pull disable. This bit is only active when CAN_TX is configured to be an input. */
    923 #define TMS570_DCAN_TIOC_PD BSP_FLD32(17)
     902#define TMS570_DCAN_TIOC_PD BSP_BIT32(17)
    924903
    925904/* field: OD - CAN_TX open drain enable. */
    926 #define TMS570_DCAN_TIOC_OD BSP_FLD32(16)
     905#define TMS570_DCAN_TIOC_OD BSP_BIT32(16)
    927906
    928907/* field: Func - CAN_TX function. This bit changes the function of the CAN_TX pin. */
    929 #define TMS570_DCAN_TIOC_Func BSP_FLD32(3)
     908#define TMS570_DCAN_TIOC_Func BSP_BIT32(3)
    930909
    931910/* field: Dir - CAN_TX data direction. */
    932 #define TMS570_DCAN_TIOC_Dir BSP_FLD32(2)
     911#define TMS570_DCAN_TIOC_Dir BSP_BIT32(2)
    933912
    934913/* field: Out - CAN_TX data out write. */
    935 #define TMS570_DCAN_TIOC_Out BSP_FLD32(1)
    936 
    937 
    938 /*----------------------TMS570_DCANRIOC----------------------*/
     914#define TMS570_DCAN_TIOC_Out BSP_BIT32(1)
     915
     916
     917/*----------------------TMS570_DCAN_RIOC----------------------*/
    939918/* field: PU - CAN_RX Pullup/Pulldown select. This bit is only active when CAN_RX is configured to be an input. */
    940 #define TMS570_DCAN_RIOC_PU BSP_FLD32(18)
     919#define TMS570_DCAN_RIOC_PU BSP_BIT32(18)
    941920
    942921/* field: PD - CAN_RX pull disable. This bit is only active when CAN_RX is configured to be an input. */
    943 #define TMS570_DCAN_RIOC_PD BSP_FLD32(17)
     922#define TMS570_DCAN_RIOC_PD BSP_BIT32(17)
    944923
    945924/* field: OD - CAN_RX open drain enable. */
    946 #define TMS570_DCAN_RIOC_OD BSP_FLD32(16)
     925#define TMS570_DCAN_RIOC_OD BSP_BIT32(16)
    947926
    948927/* field: Func - CAN_RX function. This bit changes the function of the CAN_RX pin. */
    949 #define TMS570_DCAN_RIOC_Func BSP_FLD32(3)
     928#define TMS570_DCAN_RIOC_Func BSP_BIT32(3)
    950929
    951930/* field: Dir - CAN_RX data direction. */
    952 #define TMS570_DCAN_RIOC_Dir BSP_FLD32(2)
     931#define TMS570_DCAN_RIOC_Dir BSP_BIT32(2)
    953932
    954933/* field: Out - CAN_RX data out write. */
    955 #define TMS570_DCAN_RIOC_Out BSP_FLD32(1)
     934#define TMS570_DCAN_RIOC_Out BSP_BIT32(1)
    956935
    957936/* field: In - CAN_RX data in. */
    958 #define TMS570_DCAN_RIOC_In BSP_FLD32(0)
    959 
    960 
    961 
    962 #endif /* LIBBSP_ARM_tms570_DCAN */
     937#define TMS570_DCAN_RIOC_In BSP_BIT32(0)
     938
     939
     940
     941#endif /* LIBBSP_ARM_TMS570_DCAN */
  • c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_dcc.h

    r3f923fd2 r9a84f983  
    3737 * either expressed or implied, of the FreeBSD Project.
    3838*/
    39 #ifndef LIBBSP_ARM_tms570_DCC
    40 #define LIBBSP_ARM_tms570_DCC
     39#ifndef LIBBSP_ARM_TMS570_DCC
     40#define LIBBSP_ARM_TMS570_DCC
    4141
    4242#include <bsp/utility.h>
     
    5757
    5858
    59 /*----------------------TMS570_DCCGCTRL----------------------*/
     59/*----------------------TMS570_DCC_GCTRL----------------------*/
    6060/* field: DONE_INT_ENA - Done Interrupt Enable. */
    6161#define TMS570_DCC_GCTRL_DONE_INT_ENA(val) BSP_FLD32(val,12, 15)
     
    7979
    8080
    81 /*-----------------------TMS570_DCCREV-----------------------*/
     81/*-----------------------TMS570_DCC_REV-----------------------*/
    8282/* field: SCHEME - Reads return 01, writes have no effect. */
    8383#define TMS570_DCC_REV_SCHEME(val) BSP_FLD32(val,30, 31)
     
    111111
    112112
    113 /*---------------------TMS570_DCCCNT0SEED---------------------*/
     113/*--------------------TMS570_DCC_CNT0SEED--------------------*/
    114114/* field: COUNT0_SEED - Seed value for DCC Counter0. */
    115115#define TMS570_DCC_CNT0SEED_COUNT0_SEED(val) BSP_FLD32(val,0, 19)
     
    118118
    119119
    120 /*--------------------TMS570_DCCVALID0SEED--------------------*/
     120/*-------------------TMS570_DCC_VALID0SEED-------------------*/
    121121/* field: VALID0_SEED - XXX */
    122122#define TMS570_DCC_VALID0SEED_VALID0_SEED(val) BSP_FLD32(val,0, 15)
     
    125125
    126126
    127 /*---------------------TMS570_DCCCNT1SEED---------------------*/
     127/*--------------------TMS570_DCC_CNT1SEED--------------------*/
    128128/* field: COUNT1_SEED - Seed value for DCC Counter1. */
    129129#define TMS570_DCC_CNT1SEED_COUNT1_SEED(val) BSP_FLD32(val,0, 19)
     
    132132
    133133
    134 /*-----------------------TMS570_DCCSTAT-----------------------*/
     134/*----------------------TMS570_DCC_STAT----------------------*/
    135135/* field: DONE_FLG - Single-Shot Sequence Done flag. */
    136 #define TMS570_DCC_STAT_DONE_FLG BSP_FLD32(1)
     136#define TMS570_DCC_STAT_DONE_FLG BSP_BIT32(1)
    137137
    138138/* field: ERR_FLG - Error flag. Indicates that a DCC error has occurred. */
    139 #define TMS570_DCC_STAT_ERR_FLG BSP_FLD32(0)
     139#define TMS570_DCC_STAT_ERR_FLG BSP_BIT32(0)
    140140
    141141
    142 /*-----------------------TMS570_DCCCNT0-----------------------*/
     142/*----------------------TMS570_DCC_CNT0----------------------*/
    143143/* field: COUNT0 - Current value of DCC Counter0. */
    144144#define TMS570_DCC_CNT0_COUNT0(val) BSP_FLD32(val,0, 19)
     
    147147
    148148
    149 /*----------------------TMS570_DCCVALID0----------------------*/
     149/*---------------------TMS570_DCC_VALID0---------------------*/
    150150/* field: VALID0 - Current value for DCC Valid0. */
    151151#define TMS570_DCC_VALID0_VALID0(val) BSP_FLD32(val,0, 15)
     
    154154
    155155
    156 /*-----------------------TMS570_DCCCNT1-----------------------*/
     156/*----------------------TMS570_DCC_CNT1----------------------*/
    157157/* field: COUNT1 - Current value for DCC Counter1. */
    158158#define TMS570_DCC_CNT1_COUNT1(val) BSP_FLD32(val,0, 19)
     
    161161
    162162
    163 /*--------------------TMS570_DCCCNT1CLKSRC--------------------*/
     163/*-------------------TMS570_DCC_CNT1CLKSRC-------------------*/
    164164/* field: KEY - Key to enable clock source selection for Counter1. */
    165165#define TMS570_DCC_CNT1CLKSRC_KEY(val) BSP_FLD32(val,12, 15)
     
    173173
    174174
    175 /*--------------------TMS570_DCCCNT0CLKSRC--------------------*/
     175/*-------------------TMS570_DCC_CNT0CLKSRC-------------------*/
    176176/* field: CNT0_CLKSRC - Clock Source for Counter0 */
    177177#define TMS570_DCC_CNT0CLKSRC_CNT0_CLKSRC(val) BSP_FLD32(val,0, 3)
     
    181181
    182182
    183 #endif /* LIBBSP_ARM_tms570_DCC */
     183#endif /* LIBBSP_ARM_TMS570_DCC */
  • c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_dma.h

    r3f923fd2 r9a84f983  
    3737 * either expressed or implied, of the FreeBSD Project.
    3838*/
    39 #ifndef LIBBSP_ARM_tms570_DMA
    40 #define LIBBSP_ARM_tms570_DMA
     39#ifndef LIBBSP_ARM_TMS570_DMA
     40#define LIBBSP_ARM_TMS570_DMA
    4141
    4242#include <bsp/utility.h>
     
    141141
    142142
    143 /*---------------------TMS570_DMASTARTADD---------------------*/
     143/*--------------------TMS570_DMA_STARTADD--------------------*/
    144144/* field: STARTADDRESS - Start Address defines the address at which the region begins. */
    145 #define TMS570_DMA_STARTADD_STARTADDRESS(val) BSP_FLD32(val,0, 31)
    146 #define TMS570_DMA_STARTADD_STARTADDRESS_GET(reg) BSP_FLD32GET(reg,0, 31)
    147 #define TMS570_DMA_STARTADD_STARTADDRESS_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
    148 
    149 
    150 /*----------------------TMS570_DMAENDADD----------------------*/
     145/* Whole 32 bits */
     146
     147/*---------------------TMS570_DMA_ENDADD---------------------*/
    151148/* field: ENDADDRESS - End Address defines the address at which the region ends. */
    152 #define TMS570_DMA_ENDADD_ENDADDRESS(val) BSP_FLD32(val,0, 31)
    153 #define TMS570_DMA_ENDADD_ENDADDRESS_GET(reg) BSP_FLD32GET(reg,0, 31)
    154 #define TMS570_DMA_ENDADD_ENDADDRESS_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
    155 
    156 
    157 /*----------------------TMS570_DMAGCTRL----------------------*/
     149/* Whole 32 bits */
     150
     151/*----------------------TMS570_DMA_GCTRL----------------------*/
    158152/* field: DMA_EN - DMA enable bit. */
    159 #define TMS570_DMA_GCTRL_DMA_EN BSP_FLD32(16)
     153#define TMS570_DMA_GCTRL_DMA_EN BSP_BIT32(16)
    160154
    161155/* field: BUS_BUSY - This bit indicates status of DMA external AHB bus status. */
    162 #define TMS570_DMA_GCTRL_BUS_BUSY BSP_FLD32(14)
     156#define TMS570_DMA_GCTRL_BUS_BUSY BSP_BIT32(14)
    163157
    164158/* field: DEBUG_MODE - Debug Mode. */
     
    168162
    169163/* field: DMA_RES - DMA software reset */
    170 #define TMS570_DMA_GCTRL_DMA_RES BSP_FLD32(0)
    171 
    172 
    173 /*-----------------------TMS570_DMAPEND-----------------------*/
     164#define TMS570_DMA_GCTRL_DMA_RES BSP_BIT32(0)
     165
     166
     167/*----------------------TMS570_DMA_PEND----------------------*/
    174168/* field: PEND - Channel pending register. */
    175169#define TMS570_DMA_PEND_PEND(val) BSP_FLD32(val,0, 15)
     
    178172
    179173
    180 /*---------------------TMS570_DMADMASTAT---------------------*/
     174/*---------------------TMS570_DMA_DMASTAT---------------------*/
    181175/* field: STCH - Status of DMA channels. */
    182176#define TMS570_DMA_DMASTAT_STCH(val) BSP_FLD32(val,0, 15)
     
    185179
    186180
    187 /*---------------------TMS570_DMAHWCHENAS---------------------*/
     181/*--------------------TMS570_DMA_HWCHENAS--------------------*/
    188182/* field: HWCHENA - Hardware channel enable bit. */
    189183#define TMS570_DMA_HWCHENAS_HWCHENA(val) BSP_FLD32(val,0, 15)
     
    192186
    193187
    194 /*---------------------TMS570_DMAHWCHENAR---------------------*/
     188/*--------------------TMS570_DMA_HWCHENAR--------------------*/
    195189/* field: HWCHDIS - HW channel disable bit. */
    196190#define TMS570_DMA_HWCHENAR_HWCHDIS(val) BSP_FLD32(val,0, 15)
     
    199193
    200194
    201 /*---------------------TMS570_DMASWCHENAS---------------------*/
     195/*--------------------TMS570_DMA_SWCHENAS--------------------*/
    202196/* field: SWCHENA - SW channel enable bit. */
    203197#define TMS570_DMA_SWCHENAS_SWCHENA(val) BSP_FLD32(val,0, 15)
     
    206200
    207201
    208 /*---------------------TMS570_DMASWCHENAR---------------------*/
     202/*--------------------TMS570_DMA_SWCHENAR--------------------*/
    209203/* field: SWCHDIS - SW channel disable bit. */
    210204#define TMS570_DMA_SWCHENAR_SWCHDIS(val) BSP_FLD32(val,0, 15)
     
    213207
    214208
    215 /*---------------------TMS570_DMACHPRIOS---------------------*/
     209/*---------------------TMS570_DMA_CHPRIOS---------------------*/
    216210/* field: CPS - Channel priority set bit. */
    217211#define TMS570_DMA_CHPRIOS_CPS(val) BSP_FLD32(val,0, 15)
     
    220214
    221215
    222 /*---------------------TMS570_DMACHPRIOR---------------------*/
     216/*---------------------TMS570_DMA_CHPRIOR---------------------*/
    223217/* field: CPR - Channel priority reset bit. */
    224218#define TMS570_DMA_CHPRIOR_CPR(val) BSP_FLD32(val,0, 15)
     
    227221
    228222
    229 /*---------------------TMS570_DMAGCHIENAS---------------------*/
     223/*--------------------TMS570_DMA_GCHIENAS--------------------*/
    230224/* field: GCHIE - Global channel interrupt enable bit. */
    231225#define TMS570_DMA_GCHIENAS_GCHIE(val) BSP_FLD32(val,0, 15)
     
    234228
    235229
    236 /*---------------------TMS570_DMAGCHIENAR---------------------*/
     230/*--------------------TMS570_DMA_GCHIENAR--------------------*/
    237231/* field: GCHID - Global channel interrupt disable bit. */
    238232#define TMS570_DMA_GCHIENAR_GCHID(val) BSP_FLD32(val,0, 15)
     
    241235
    242236
    243 /*---------------------TMS570_DMADREQASI---------------------*/
     237/*---------------------TMS570_DMA_DREQASI---------------------*/
    244238/* field: CH0ASI - Channel 0 assignment. This bit field chooses the DMA request assignment for channel 0. */
    245239#define TMS570_DMA_DREQASI_CH0ASI(val) BSP_FLD32(val,24, 29)
     
    263257
    264258
    265 /*-----------------------TMS570_DMAPAR0-----------------------*/
     259/*----------------------TMS570_DMA_PAR0----------------------*/
    266260/* field: CH0PA - These bit fields determine to which port channel 0 is assigned. */
    267261#define TMS570_DMA_PAR0_CH0PA(val) BSP_FLD32(val,28, 30)
     
    305299
    306300
    307 /*-----------------------TMS570_DMAPAR1-----------------------*/
     301/*----------------------TMS570_DMA_PAR1----------------------*/
    308302/* field: CH8PA - These bit fields determine to which port channel 8 is assigned. */
    309303#define TMS570_DMA_PAR1_CH8PA(val) BSP_FLD32(val,28, 30)
     
    347341
    348342
    349 /*----------------------TMS570_DMAFTCMAP----------------------*/
     343/*---------------------TMS570_DMA_FTCMAP---------------------*/
    350344/* field: FTCAB - Frame transfer complete (FTC) interrupt to Group A or Group B. */
    351345#define TMS570_DMA_FTCMAP_FTCAB(val) BSP_FLD32(val,0, 15)
     
    354348
    355349
    356 /*----------------------TMS570_DMALFSMAP----------------------*/
     350/*---------------------TMS570_DMA_LFSMAP---------------------*/
    357351/* field: LFSAB - Last frame started (LFS) interrupt to Group A or Group B. */
    358352#define TMS570_DMA_LFSMAP_LFSAB(val) BSP_FLD32(val,0, 15)
     
    361355
    362356
    363 /*----------------------TMS570_DMAHBCMAP----------------------*/
     357/*---------------------TMS570_DMA_HBCMAP---------------------*/
    364358/* field: HBCAB - Half block complete (HBC) interrupt to Group A or Group B. */
    365359#define TMS570_DMA_HBCMAP_HBCAB(val) BSP_FLD32(val,0, 15)
     
    368362
    369363
    370 /*----------------------TMS570_DMABTCMAP----------------------*/
     364/*---------------------TMS570_DMA_BTCMAP---------------------*/
    371365/* field: BTCAB - Block transfer complete (BTC) interrupt to Group A or Group B */
    372366#define TMS570_DMA_BTCMAP_BTCAB(val) BSP_FLD32(val,0, 15)
     
    375369
    376370
    377 /*----------------------TMS570_DMABERMAP----------------------*/
     371/*---------------------TMS570_DMA_BERMAP---------------------*/
    378372/* field: BERAB - Bus error (BER) interrupt to Group A or Group B. */
    379373#define TMS570_DMA_BERMAP_BERAB(val) BSP_FLD32(val,0, 15)
     
    382376
    383377
    384 /*--------------------TMS570_DMAFTCINTENAS--------------------*/
     378/*-------------------TMS570_DMA_FTCINTENAS-------------------*/
    385379/* field: FTCINTENA - Frame transfer complete (FTC) interrupt enable. */
    386380#define TMS570_DMA_FTCINTENAS_FTCINTENA(val) BSP_FLD32(val,0, 15)
     
    389383
    390384
    391 /*--------------------TMS570_DMAFTCINTENAR--------------------*/
     385/*-------------------TMS570_DMA_FTCINTENAR-------------------*/
    392386/* field: FTCINTDIS - Frame transfer complete (FTC) interrupt disable. */
    393387#define TMS570_DMA_FTCINTENAR_FTCINTDIS(val) BSP_FLD32(val,0, 15)
     
    396390
    397391
    398 /*--------------------TMS570_DMALFSINTENAS--------------------*/
     392/*-------------------TMS570_DMA_LFSINTENAS-------------------*/
    399393/* field: LFSINTENA - Last frame started (LFS) interrupt enable. */
    400394#define TMS570_DMA_LFSINTENAS_LFSINTENA(val) BSP_FLD32(val,0, 15)
     
    403397
    404398
    405 /*--------------------TMS570_DMALFSINTENAR--------------------*/
     399/*-------------------TMS570_DMA_LFSINTENAR-------------------*/
    406400/* field: LFSINTDIS - Last frame started (LFS) interrupt disable. */
    407401#define TMS570_DMA_LFSINTENAR_LFSINTDIS(val) BSP_FLD32(val,0, 15)
     
    410404
    411405
    412 /*--------------------TMS570_DMAHBCINTENAS--------------------*/
     406/*-------------------TMS570_DMA_HBCINTENAS-------------------*/
    413407/* field: HBCINTENA - Half block complete (HBC) interrupt enable. */
    414408#define TMS570_DMA_HBCINTENAS_HBCINTENA(val) BSP_FLD32(val,0, 15)
     
    417411
    418412
    419 /*--------------------TMS570_DMAHBCINTENAR--------------------*/
     413/*-------------------TMS570_DMA_HBCINTENAR-------------------*/
    420414/* field: HBCINTDIS - Half block complete (HBC) interrupt disable. */
    421415#define TMS570_DMA_HBCINTENAR_HBCINTDIS(val) BSP_FLD32(val,0, 15)
     
    424418
    425419
    426 /*--------------------TMS570_DMABTCINTENAS--------------------*/
     420/*-------------------TMS570_DMA_BTCINTENAS-------------------*/
    427421/* field: BTCINTENA - Block transfer complete (BTC) interrupt enable. */
    428422#define TMS570_DMA_BTCINTENAS_BTCINTENA(val) BSP_FLD32(val,0, 15)
     
    431425
    432426
    433 /*--------------------TMS570_DMABTCINTENAR--------------------*/
     427/*-------------------TMS570_DMA_BTCINTENAR-------------------*/
    434428/* field: BTCINTDIS - Block transfer complete (BTC) interurpt disable. */
    435429#define TMS570_DMA_BTCINTENAR_BTCINTDIS(val) BSP_FLD32(val,0, 15)
     
    438432
    439433
    440 /*---------------------TMS570_DMAGINTFLAG---------------------*/
     434/*--------------------TMS570_DMA_GINTFLAG--------------------*/
    441435/* field: GINT - Global interrupt flags. */
    442436#define TMS570_DMA_GINTFLAG_GINT(val) BSP_FLD32(val,0, 15)
     
    445439
    446440
    447 /*---------------------TMS570_DMAFTCFLAG---------------------*/
     441/*---------------------TMS570_DMA_FTCFLAG---------------------*/
    448442/* field: FTCI - Frame transfer complete (FTC) flags. */
    449443#define TMS570_DMA_FTCFLAG_FTCI(val) BSP_FLD32(val,0, 15)
     
    452446
    453447
    454 /*---------------------TMS570_DMALFSFLAG---------------------*/
     448/*---------------------TMS570_DMA_LFSFLAG---------------------*/
    455449/* field: LFSI - Last frame started (LFS) flags. */
    456450#define TMS570_DMA_LFSFLAG_LFSI(val) BSP_FLD32(val,0, 15)
     
    459453
    460454
    461 /*---------------------TMS570_DMAHBCFLAG---------------------*/
     455/*---------------------TMS570_DMA_HBCFLAG---------------------*/
    462456/* field: HBCI - Half block transfer (HBC) complete flags. */
    463457#define TMS570_DMA_HBCFLAG_HBCI(val) BSP_FLD32(val,0, 15)
     
    466460
    467461
    468 /*---------------------TMS570_DMABTCFLAG---------------------*/
     462/*---------------------TMS570_DMA_BTCFLAG---------------------*/
    469463/* field: BTCI - Block transfer complete (BTC) flags. */
    470464#define TMS570_DMA_BTCFLAG_BTCI(val) BSP_FLD32(val,0, 15)
     
    473467
    474468
    475 /*---------------------TMS570_DMABERFLAG---------------------*/
     469/*---------------------TMS570_DMA_BERFLAG---------------------*/
    476470/* field: BERI - Bus error (BER) flags. */
    477471#define TMS570_DMA_BERFLAG_BERI(val) BSP_FLD32(val,0, 15)
     
    480474
    481475
    482 /*--------------------TMS570_DMAFTCAOFFSET--------------------*/
     476/*-------------------TMS570_DMA_FTCAOFFSET-------------------*/
    483477/* field: sbz - These bits should always be programmed as zero. */
    484478#define TMS570_DMA_FTCAOFFSET_sbz(val) BSP_FLD32(val,6, 7)
     
    492486
    493487
    494 /*--------------------TMS570_DMALFSAOFFSET--------------------*/
     488/*-------------------TMS570_DMA_LFSAOFFSET-------------------*/
    495489/* field: LFSA - Channel causing LFS interrupt Group A. */
    496490#define TMS570_DMA_LFSAOFFSET_LFSA(val) BSP_FLD32(val,0, 5)
     
    499493
    500494
    501 /*--------------------TMS570_DMAHBCAOFFSET--------------------*/
     495/*-------------------TMS570_DMA_HBCAOFFSET-------------------*/
    502496/* field: HBCA - Channel causing HBC interrupt Group A. */
    503497#define TMS570_DMA_HBCAOFFSET_HBCA(val) BSP_FLD32(val,0, 5)
     
    506500
    507501
    508 /*--------------------TMS570_DMABTCAOFFSET--------------------*/
     502/*-------------------TMS570_DMA_BTCAOFFSET-------------------*/
    509503/* field: BTCA - Channel causing BTC interrupt Group A. */
    510504#define TMS570_DMA_BTCAOFFSET_BTCA(val) BSP_FLD32(val,0, 5)
     
    513507
    514508
    515 /*--------------------TMS570_DMABERAOFFSET--------------------*/
     509/*-------------------TMS570_DMA_BERAOFFSET-------------------*/
    516510/* field: BERA - Channel causing BER interrupt Group A. */
    517511#define TMS570_DMA_BERAOFFSET_BERA(val) BSP_FLD32(val,0, 5)
     
    520514
    521515
    522 /*--------------------TMS570_DMAFTCBOFFSET--------------------*/
     516/*-------------------TMS570_DMA_FTCBOFFSET-------------------*/
    523517/* field: FTCB - Channel causing FTC interrupt Group B. */
    524518#define TMS570_DMA_FTCBOFFSET_FTCB(val) BSP_FLD32(val,0, 5)
     
    527521
    528522
    529 /*--------------------TMS570_DMALFSBOFFSET--------------------*/
     523/*-------------------TMS570_DMA_LFSBOFFSET-------------------*/
    530524/* field: LFSB - Channel causing LFS interrupt Group B. */
    531525#define TMS570_DMA_LFSBOFFSET_LFSB(val) BSP_FLD32(val,0, 5)
     
    534528
    535529
    536 /*--------------------TMS570_DMAHBCBOFFSET--------------------*/
     530/*-------------------TMS570_DMA_HBCBOFFSET-------------------*/
    537531/* field: HBCB - Channel causing HBC interrupt Group B. */
    538532#define TMS570_DMA_HBCBOFFSET_HBCB(val) BSP_FLD32(val,0, 5)
     
    541535
    542536
    543 /*--------------------TMS570_DMABTCBOFFSET--------------------*/
     537/*-------------------TMS570_DMA_BTCBOFFSET-------------------*/
    544538/* field: BTCB - interrupt for Group B if the corresponding interrupt enable is set. */
    545539#define TMS570_DMA_BTCBOFFSET_BTCB(val) BSP_FLD32(val,0, 5)
     
    548542
    549543
    550 /*--------------------TMS570_DMABERBOFFSET--------------------*/
     544/*-------------------TMS570_DMA_BERBOFFSET-------------------*/
    551545/* field: BERB - Channel causing BER interrupt Group B. */
    552546#define TMS570_DMA_BERBOFFSET_BERB(val) BSP_FLD32(val,0, 5)
     
    555549
    556550
    557 /*----------------------TMS570_DMAPTCRL----------------------*/
     551/*----------------------TMS570_DMA_PTCRL----------------------*/
    558552/* field: PENDB - Transfers pending for Port B. This flag determines if transfers are ongoing on port B. */
    559 #define TMS570_DMA_PTCRL_PENDB BSP_FLD32(24)
     553#define TMS570_DMA_PTCRL_PENDB BSP_BIT32(24)
    560554
    561555/* field: BYB - Bypass FIFO B. */
    562 #define TMS570_DMA_PTCRL_BYB BSP_FLD32(18)
     556#define TMS570_DMA_PTCRL_BYB BSP_BIT32(18)
    563557
    564558/* field: PSFRHQPB - Priority scheme fix or rotate for high priority queue of Port B. */
    565 #define TMS570_DMA_PTCRL_PSFRHQPB BSP_FLD32(17)
     559#define TMS570_DMA_PTCRL_PSFRHQPB BSP_BIT32(17)
    566560
    567561/* field: PSFRLQPB - Priority scheme fix or rotate for low priority queue of Port B. */
    568 #define TMS570_DMA_PTCRL_PSFRLQPB BSP_FLD32(16)
    569 
    570 
    571 /*----------------------TMS570_DMARTCTRL----------------------*/
     562#define TMS570_DMA_PTCRL_PSFRLQPB BSP_BIT32(16)
     563
     564
     565/*---------------------TMS570_DMA_RTCTRL---------------------*/
    572566/* field: RTC - RAM Test Control. */
    573 #define TMS570_DMA_RTCTRL_RTC BSP_FLD32(0)
    574 
    575 
    576 /*----------------------TMS570_DMADCTRL----------------------*/
     567#define TMS570_DMA_RTCTRL_RTC BSP_BIT32(0)
     568
     569
     570/*----------------------TMS570_DMA_DCTRL----------------------*/
    577571/* field: CHNUM - Channel Number. */
    578572#define TMS570_DMA_DCTRL_CHNUM(val) BSP_FLD32(val,24, 28)
     
    581575
    582576/* field: DMADBGS - DMA debug status. */
    583 #define TMS570_DMA_DCTRL_DMADBGS BSP_FLD32(16)
     577#define TMS570_DMA_DCTRL_DMADBGS BSP_BIT32(16)
    584578
    585579/* field: DBGEN - Debug Enable. */
    586 #define TMS570_DMA_DCTRL_DBGEN BSP_FLD32(0)
    587 
    588 
    589 /*-----------------------TMS570_DMAWPR-----------------------*/
     580#define TMS570_DMA_DCTRL_DBGEN BSP_BIT32(0)
     581
     582
     583/*-----------------------TMS570_DMA_WPR-----------------------*/
    590584/* field: WP - Watch point. */
    591 #define TMS570_DMA_WPR_WP(val) BSP_FLD32(val,0, 31)
    592 #define TMS570_DMA_WPR_WP_GET(reg) BSP_FLD32GET(reg,0, 31)
    593 #define TMS570_DMA_WPR_WP_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
    594 
    595 
    596 /*-----------------------TMS570_DMAWMR-----------------------*/
     585/* Whole 32 bits */
     586
     587/*-----------------------TMS570_DMA_WMR-----------------------*/
    597588/* field: WM - Watch mask. */
    598 #define TMS570_DMA_WMR_WM(val) BSP_FLD32(val,0, 31)
    599 #define TMS570_DMA_WMR_WM_GET(reg) BSP_FLD32GET(reg,0, 31)
    600 #define TMS570_DMA_WMR_WM_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
    601 
    602 
    603 /*--------------------TMS570_DMAPBACSADDR--------------------*/
     589/* Whole 32 bits */
     590
     591/*--------------------TMS570_DMA_PBACSADDR--------------------*/
    604592/* field: PBACSA - Port B Active Channel Source Address. */
    605 #define TMS570_DMA_PBACSADDR_PBACSA(val) BSP_FLD32(val,0, 31)
    606 #define TMS570_DMA_PBACSADDR_PBACSA_GET(reg) BSP_FLD32GET(reg,0, 31)
    607 #define TMS570_DMA_PBACSADDR_PBACSA_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
    608 
    609 
    610 /*--------------------TMS570_DMAPBACDADDR--------------------*/
     593/* Whole 32 bits */
     594
     595/*--------------------TMS570_DMA_PBACDADDR--------------------*/
    611596/* field: PBACDA - address of the active channel as broadcasted in Section 16.3.1.3 for Port B. */
    612 #define TMS570_DMA_PBACDADDR_PBACDA(val) BSP_FLD32(val,0, 31)
    613 #define TMS570_DMA_PBACDADDR_PBACDA_GET(reg) BSP_FLD32GET(reg,0, 31)
    614 #define TMS570_DMA_PBACDADDR_PBACDA_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
    615 
    616 
    617 /*----------------------TMS570_DMAPBACTC----------------------*/
     597/* Whole 32 bits */
     598
     599/*---------------------TMS570_DMA_PBACTC---------------------*/
    618600/* field: PBFTCOUNT - Port B active channel frame count. */
    619601#define TMS570_DMA_PBACTC_PBFTCOUNT(val) BSP_FLD32(val,16, 28)
     
    627609
    628610
    629 /*----------------------TMS570_DMADMAPCR----------------------*/
     611/*---------------------TMS570_DMA_DMAPCR---------------------*/
    630612/* field: ERRA - Error action. */
    631 #define TMS570_DMA_DMAPCR_ERRA BSP_FLD32(16)
     613#define TMS570_DMA_DMAPCR_ERRA BSP_BIT32(16)
    632614
    633615/* field: TEST - When this bit is set, the parity bits are memory mapped to make them accessible by the CPU. */
    634 #define TMS570_DMA_DMAPCR_TEST BSP_FLD32(8)
     616#define TMS570_DMA_DMAPCR_TEST BSP_BIT32(8)
    635617
    636618/* field: PARITY_ENA - Parity error detection enable. */
     
    640622
    641623
    642 /*----------------------TMS570_DMADMAPAR----------------------*/
     624/*---------------------TMS570_DMA_DMAPAR---------------------*/
    643625/* field: EDFLAG - Parity Error Detection Flag. */
    644 #define TMS570_DMA_DMAPAR_EDFLAG BSP_FLD32(24)
     626#define TMS570_DMA_DMAPAR_EDFLAG BSP_BIT32(24)
    645627
    646628/* field: ERRORADDRESS - Error address. These bits hold the address of the first parity error generated in the RAM. */
     
    650632
    651633
    652 /*--------------------TMS570_DMADMAMPCTRL--------------------*/
     634/*--------------------TMS570_DMA_DMAMPCTRL--------------------*/
    653635/* field: INT3AB - Interrupt assignment of region 3 to Group A or Group B. */
    654 #define TMS570_DMA_DMAMPCTRL_INT3AB BSP_FLD32(28)
     636#define TMS570_DMA_DMAMPCTRL_INT3AB BSP_BIT32(28)
    655637
    656638/* field: INT3ENA - Interrupt enable of region 3. */
    657 #define TMS570_DMA_DMAMPCTRL_INT3ENA BSP_FLD32(27)
     639#define TMS570_DMA_DMAMPCTRL_INT3ENA BSP_BIT32(27)
    658640
    659641/* field: REG3AP - Region 3 access permission. */
     
    663645
    664646/* field: REG3ENA - Region 3 enable. */
    665 #define TMS570_DMA_DMAMPCTRL_REG3ENA BSP_FLD32(24)
     647#define TMS570_DMA_DMAMPCTRL_REG3ENA BSP_BIT32(24)
    666648
    667649/* field: INT2AB - Interrupt assignment of region 2 to Group A or Group B. */
    668 #define TMS570_DMA_DMAMPCTRL_INT2AB BSP_FLD32(20)
     650#define TMS570_DMA_DMAMPCTRL_INT2AB BSP_BIT32(20)
    669651
    670652/* field: INT2ENA - Interrupt enable of region 2. */
    671 #define TMS570_DMA_DMAMPCTRL_INT2ENA BSP_FLD32(19)
     653#define TMS570_DMA_DMAMPCTRL_INT2ENA BSP_BIT32(19)
    672654
    673655/* field: REG2AP - Region 2 access permission. These bits determine the access permission for region 2. */
     
    677659
    678660/* field: REG2ENA - Region 2 enable. */
    679 #define TMS570_DMA_DMAMPCTRL_REG2ENA BSP_FLD32(16)
     661#define TMS570_DMA_DMAMPCTRL_REG2ENA BSP_BIT32(16)
    680662
    681663/* field: INT1AB - Interrupt assignment of region 1 to Group A or Group B. */
    682 #define TMS570_DMA_DMAMPCTRL_INT1AB BSP_FLD32(12)
     664#define TMS570_DMA_DMAMPCTRL_INT1AB BSP_BIT32(12)
    683665
    684666/* field: INT1ENA - Interrupt enable of region 1. */
    685 #define TMS570_DMA_DMAMPCTRL_INT1ENA BSP_FLD32(11)
     667#define TMS570_DMA_DMAMPCTRL_INT1ENA BSP_BIT32(11)
    686668
    687669/* field: REG1AP - Region 1 access permission. */
     
    691673
    692674/* field: REG1ENA - Region 1 enable. */
    693 #define TMS570_DMA_DMAMPCTRL_REG1ENA BSP_FLD32(8)
     675#define TMS570_DMA_DMAMPCTRL_REG1ENA BSP_BIT32(8)
    694676
    695677/* field: INT0AB - Interrupt assignment of region 0 to Group A or Group B. */
    696 #define TMS570_DMA_DMAMPCTRL_INT0AB BSP_FLD32(4)
     678#define TMS570_DMA_DMAMPCTRL_INT0AB BSP_BIT32(4)
    697679
    698680/* field: INT0ENA - Interrupt enable of region 0. */
    699 #define TMS570_DMA_DMAMPCTRL_INT0ENA BSP_FLD32(3)
     681#define TMS570_DMA_DMAMPCTRL_INT0ENA BSP_BIT32(3)
    700682
    701683/* field: REG0AP - Region 0 access permission. These bits determine the access permission for region 0. */
     
    705687
    706688/* field: REG0ENA - Region 0 enable. */
    707 #define TMS570_DMA_DMAMPCTRL_REG0ENA BSP_FLD32(0)
    708 
    709 
    710 /*---------------------TMS570_DMADMAMPST---------------------*/
     689#define TMS570_DMA_DMAMPCTRL_REG0ENA BSP_BIT32(0)
     690
     691
     692/*---------------------TMS570_DMA_DMAMPST---------------------*/
    711693/* field: REG3FT - Region 3 fault. */
    712 #define TMS570_DMA_DMAMPST_REG3FT BSP_FLD32(24)
     694#define TMS570_DMA_DMAMPST_REG3FT BSP_BIT32(24)
    713695
    714696/* field: REG2FT - Region 2 fault. */
    715 #define TMS570_DMA_DMAMPST_REG2FT BSP_FLD32(16)
     697#define TMS570_DMA_DMAMPST_REG2FT BSP_BIT32(16)
    716698
    717699/* field: REG1FT - Region 1 fault. */
    718 #define TMS570_DMA_DMAMPST_REG1FT BSP_FLD32(8)
     700#define TMS570_DMA_DMAMPST_REG1FT BSP_BIT32(8)
    719701
    720702/* field: REG0FT - Region 0 fault. */
    721 #define TMS570_DMA_DMAMPST_REG0FT BSP_FLD32(0)
    722 
    723 
    724 /*---------------------TMS570_DMADMAMPROS---------------------*/
     703#define TMS570_DMA_DMAMPST_REG0FT BSP_BIT32(0)
     704
     705
     706/*--------------------TMS570_DMA_DMAMPROS--------------------*/
    725707/* field: STARTADDRESS - Start Address defines the address at which the region begins. */
    726 #define TMS570_DMA_DMAMPROS_STARTADDRESS(val) BSP_FLD32(val,0, 31)
    727 #define TMS570_DMA_DMAMPROS_STARTADDRESS_GET(reg) BSP_FLD32GET(reg,0, 31)
    728 #define TMS570_DMA_DMAMPROS_STARTADDRESS_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
    729 
    730 
    731 
    732 #endif /* LIBBSP_ARM_tms570_DMA */
     708/* Whole 32 bits */
     709
     710
     711#endif /* LIBBSP_ARM_TMS570_DMA */
  • c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_dmm.h

    r3f923fd2 r9a84f983  
    3737 * either expressed or implied, of the FreeBSD Project.
    3838*/
    39 #ifndef LIBBSP_ARM_tms570_DMM
    40 #define LIBBSP_ARM_tms570_DMM
     39#ifndef LIBBSP_ARM_TMS570_DMM
     40#define LIBBSP_ARM_TMS570_DMM
    4141
    4242#include <bsp/utility.h>
     
    8282
    8383
    84 /*---------------------TMS570_DMMGLBCTRL---------------------*/
     84/*---------------------TMS570_DMM_GLBCTRL---------------------*/
    8585/* field: BUSY - Busy indicator. */
    86 #define TMS570_DMM_GLBCTRL_BUSY BSP_FLD32(24)
     86#define TMS570_DMM_GLBCTRL_BUSY BSP_BIT32(24)
    8787
    8888/* field: CONTCLK - Continuous DMMCLK input. */
    89 #define TMS570_DMM_GLBCTRL_CONTCLK BSP_FLD32(18)
     89#define TMS570_DMM_GLBCTRL_CONTCLK BSP_BIT32(18)
    9090
    9191/* field: COS - Continue on suspend. Influences behavior of module while in debug mode. */
    92 #define TMS570_DMM_GLBCTRL_COS BSP_FLD32(17)
     92#define TMS570_DMM_GLBCTRL_COS BSP_BIT32(17)
    9393
    9494/* field: RESET - Reset. */
    95 #define TMS570_DMM_GLBCTRL_RESET BSP_FLD32(16)
     95#define TMS570_DMM_GLBCTRL_RESET BSP_BIT32(16)
    9696
    9797/* field: DDM_WIDTH - Packet Width in direct data mode. */
     
    101101
    102102/* field: TM_DMM - Packet Format. */
    103 #define TMS570_DMM_GLBCTRL_TM_DMM BSP_FLD32(8)
     103#define TMS570_DMM_GLBCTRL_TM_DMM BSP_BIT32(8)
    104104
    105105/* field: ON_OFF - Switch module on or off */
     
    109109
    110110
    111 /*----------------------TMS570_DMMINTSET----------------------*/
     111/*---------------------TMS570_DMM_INTSET---------------------*/
    112112/* field: PROG_BUFF - Programmable Buffer Interrupt Set. */
    113 #define TMS570_DMM_INTSET_PROG_BUFF BSP_FLD32(17)
     113#define TMS570_DMM_INTSET_PROG_BUFF BSP_BIT32(17)
    114114
    115115/* field: EO_BUFF - EO_BUFF */
    116 #define TMS570_DMM_INTSET_EO_BUFF BSP_FLD32(16)
     116#define TMS570_DMM_INTSET_EO_BUFF BSP_BIT32(16)
    117117
    118118/* field: DEST3REG2 - Destination 3 Region 2 Interrupt Set. */
    119 #define TMS570_DMM_INTSET_DEST3REG2 BSP_FLD32(15)
     119#define TMS570_DMM_INTSET_DEST3REG2 BSP_BIT32(15)
    120120
    121121/* field: DEST3REG1 - Destination 3 Region 1 Interrupt Set. */
    122 #define TMS570_DMM_INTSET_DEST3REG1 BSP_FLD32(14)
     122#define TMS570_DMM_INTSET_DEST3REG1 BSP_BIT32(14)
    123123
    124124/* field: DEST2REG2 - Destination 2 Region 2 Interrupt Set. */
    125 #define TMS570_DMM_INTSET_DEST2REG2 BSP_FLD32(13)
     125#define TMS570_DMM_INTSET_DEST2REG2 BSP_BIT32(13)
    126126
    127127/* field: DEST2REG1 - Destination 2 Region 1 Interrupt Set. */
    128 #define TMS570_DMM_INTSET_DEST2REG1 BSP_FLD32(12)
     128#define TMS570_DMM_INTSET_DEST2REG1 BSP_BIT32(12)
    129129
    130130/* field: DEST1REG2 - Destination 1 Region 2 Interrupt Set. */
    131 #define TMS570_DMM_INTSET_DEST1REG2 BSP_FLD32(11)
     131#define TMS570_DMM_INTSET_DEST1REG2 BSP_BIT32(11)
    132132
    133133/* field: DEST1REG1 - DEST1REG1 */
    134 #define TMS570_DMM_INTSET_DEST1REG1 BSP_FLD32(10)
     134#define TMS570_DMM_INTSET_DEST1REG1 BSP_BIT32(10)
    135135
    136136/* field: DEST0REG2 - Destination 0 Region 2 Interrupt Set. */
    137 #define TMS570_DMM_INTSET_DEST0REG2 BSP_FLD32(9)
     137#define TMS570_DMM_INTSET_DEST0REG2 BSP_BIT32(9)
    138138
    139139/* field: DEST0REG1 - Destination 0 Region 1 Interrupt Set. */
    140 #define TMS570_DMM_INTSET_DEST0REG1 BSP_FLD32(8)
     140#define TMS570_DMM_INTSET_DEST0REG1 BSP_BIT32(8)
    141141
    142142/* field: BUSERROR - Bus Error Response for errors generated when doing internal bus transfers. */
    143 #define TMS570_DMM_INTSET_BUSERROR BSP_FLD32(7)
     143#define TMS570_DMM_INTSET_BUSERROR BSP_BIT32(7)
    144144
    145145/* field: BUFF_OVF - Buffer Overflow. */
    146 #define TMS570_DMM_INTSET_BUFF_OVF BSP_FLD32(6)
     146#define TMS570_DMM_INTSET_BUFF_OVF BSP_BIT32(6)
    147147
    148148/* field: SRC_OVF - Source Overflow. */
    149 #define TMS570_DMM_INTSET_SRC_OVF BSP_FLD32(5)
     149#define TMS570_DMM_INTSET_SRC_OVF BSP_BIT32(5)
    150150
    151151/* field: DEST3_ERR - Destination 3 Error. */
    152 #define TMS570_DMM_INTSET_DEST3_ERR BSP_FLD32(4)
     152#define TMS570_DMM_INTSET_DEST3_ERR BSP_BIT32(4)
    153153
    154154/* field: DEST2_ERR - Destination 2 Error Interrupt Set. */
    155 #define TMS570_DMM_INTSET_DEST2_ERR BSP_FLD32(3)
     155#define TMS570_DMM_INTSET_DEST2_ERR BSP_BIT32(3)
    156156
    157157/* field: DEST1_ERR - Destination 1 Error Interrupt Set. */
    158 #define TMS570_DMM_INTSET_DEST1_ERR BSP_FLD32(2)
     158#define TMS570_DMM_INTSET_DEST1_ERR BSP_BIT32(2)
    159159
    160160/* field: DEST0_ERR - Destination 0 Error Interrupt Set. */
    161 #define TMS570_DMM_INTSET_DEST0_ERR BSP_FLD32(1)
     161#define TMS570_DMM_INTSET_DEST0_ERR BSP_BIT32(1)
    162162
    163163/* field: PACKET_ERR_INT - Packet Error. */
    164 #define TMS570_DMM_INTSET_PACKET_ERR_INT BSP_FLD32(0)
    165 
    166 
    167 /*----------------------TMS570_DMMINTCLR----------------------*/
     164#define TMS570_DMM_INTSET_PACKET_ERR_INT BSP_BIT32(0)
     165
     166
     167/*---------------------TMS570_DMM_INTCLR---------------------*/
    168168/* field: PROG_BUFF - Programmable Buffer Interrupt Set. */
    169 #define TMS570_DMM_INTCLR_PROG_BUFF BSP_FLD32(17)
     169#define TMS570_DMM_INTCLR_PROG_BUFF BSP_BIT32(17)
    170170
    171171/* field: EO_BUFF - End of Buffer Interrupt Set. */
    172 #define TMS570_DMM_INTCLR_EO_BUFF BSP_FLD32(16)
     172#define TMS570_DMM_INTCLR_EO_BUFF BSP_BIT32(16)
    173173
    174174/* field: DEST3REG2 - was accessed at the startaddress of Destination 3 Region 2. */
    175 #define TMS570_DMM_INTCLR_DEST3REG2 BSP_FLD32(15)
     175#define TMS570_DMM_INTCLR_DEST3REG2 BSP_BIT32(15)
    176176
    177177/* field: DEST3REG1 - Destination 3 Region 1 Interrupt Set. */
    178 #define TMS570_DMM_INTCLR_DEST3REG1 BSP_FLD32(14)
     178#define TMS570_DMM_INTCLR_DEST3REG1 BSP_BIT32(14)
    179179
    180180/* field: DEST2REG2 - Destination 2 Region 2 Interrupt Set. */
    181 #define TMS570_DMM_INTCLR_DEST2REG2 BSP_FLD32(13)
     181#define TMS570_DMM_INTCLR_DEST2REG2 BSP_BIT32(13)
    182182
    183183/* field: DEST2REG1 - Destination 2 Region 1 Interrupt Set. */
    184 #define TMS570_DMM_INTCLR_DEST2REG1 BSP_FLD32(12)
     184#define TMS570_DMM_INTCLR_DEST2REG1 BSP_BIT32(12)
    185185
    186186/* field: DEST1REG2 - Destination 1 Region 2 Interrupt Set. */
    187 #define TMS570_DMM_INTCLR_DEST1REG2 BSP_FLD32(11)
     187#define TMS570_DMM_INTCLR_DEST1REG2 BSP_BIT32(11)
    188188
    189189/* field: DEST1REG1 - Destination 1 Region 1 Interrupt Set. */
    190 #define TMS570_DMM_INTCLR_DEST1REG1 BSP_FLD32(10)
     190#define TMS570_DMM_INTCLR_DEST1REG1 BSP_BIT32(10)
    191191
    192192/* field: DEST0REG2 - Destination 0 Region 2 Interrupt Set. */
    193 #define TMS570_DMM_INTCLR_DEST0REG2 BSP_FLD32(9)
     193#define TMS570_DMM_INTCLR_DEST0REG2 BSP_BIT32(9)
    194194
    195195/* field: DEST0REG1 - Destination 0 Region 1 Interrupt Set. */
    196 #define TMS570_DMM_INTCLR_DEST0REG1 BSP_FLD32(8)
     196#define TMS570_DMM_INTCLR_DEST0REG1 BSP_BIT32(8)
    197197
    198198/* field: BUSERROR - Bus Error Response for errors generated when doing internal bus transfers. */
    199 #define TMS570_DMM_INTCLR_BUSERROR BSP_FLD32(7)
     199#define TMS570_DMM_INTCLR_BUSERROR BSP_BIT32(7)
    200200
    201201/* field: BUFF_OVF - Buffer Overflow. */
    202 #define TMS570_DMM_INTCLR_BUFF_OVF BSP_FLD32(6)
     202#define TMS570_DMM_INTCLR_BUFF_OVF BSP_BIT32(6)
    203203
    204204/* field: SRC_OVF - Source Overflow. */
    205 #define TMS570_DMM_INTCLR_SRC_OVF BSP_FLD32(5)
     205#define TMS570_DMM_INTCLR_SRC_OVF BSP_BIT32(5)
    206206
    207207/* field: DEST3_ERR - Destination 3 Error. */
    208 #define TMS570_DMM_INTCLR_DEST3_ERR BSP_FLD32(4)
     208#define TMS570_DMM_INTCLR_DEST3_ERR BSP_BIT32(4)
    209209
    210210/* field: DEST2_ERR - Destination 2 Error Interrupt Set. */
    211 #define TMS570_DMM_INTCLR_DEST2_ERR BSP_FLD32(3)
     211#define TMS570_DMM_INTCLR_DEST2_ERR BSP_BIT32(3)
    212212
    213213/* field: DEST1_ERR - Destination 1 Error Interrupt Set. */
    214 #define TMS570_DMM_INTCLR_DEST1_ERR BSP_FLD32(2)
     214#define TMS570_DMM_INTCLR_DEST1_ERR BSP_BIT32(2)
    215215
    216216/* field: DEST0_ERR - Destination 0 Error Interrupt Set. */
    217 #define TMS570_DMM_INTCLR_DEST0_ERR BSP_FLD32(1)
     217#define TMS570_DMM_INTCLR_DEST0_ERR BSP_BIT32(1)
    218218
    219219/* field: PACKET_ERR_INT - Packet Error. */
    220 #define TMS570_DMM_INTCLR_PACKET_ERR_INT BSP_FLD32(0)
    221 
    222 
    223 /*----------------------TMS570_DMMINTLVL----------------------*/
     220#define TMS570_DMM_INTCLR_PACKET_ERR_INT BSP_BIT32(0)
     221
     222
     223/*---------------------TMS570_DMM_INTLVL---------------------*/
    224224/* field: PROG_BUFF - Programmable Buffer Interrupt Level */
    225 #define TMS570_DMM_INTLVL_PROG_BUFF BSP_FLD32(17)
     225#define TMS570_DMM_INTLVL_PROG_BUFF BSP_BIT32(17)
    226226
    227227/* field: EO_BUFF - End of Buffer Interrupt Level */
    228 #define TMS570_DMM_INTLVL_EO_BUFF BSP_FLD32(16)
     228#define TMS570_DMM_INTLVL_EO_BUFF BSP_BIT32(16)
    229229
    230230/* field: DEST3REG2 - Destination 3 Region 2 Interrupt Level */
    231 #define TMS570_DMM_INTLVL_DEST3REG2 BSP_FLD32(15)
     231#define TMS570_DMM_INTLVL_DEST3REG2 BSP_BIT32(15)
    232232
    233233/* field: DEST3REG1 - Destination 3 Region 1 Interrupt Level */
    234 #define TMS570_DMM_INTLVL_DEST3REG1 BSP_FLD32(14)
     234#define TMS570_DMM_INTLVL_DEST3REG1 BSP_BIT32(14)
    235235
    236236/* field: DEST2REG2 - Destination 2 Region 2 Interrupt Level */
    237 #define TMS570_DMM_INTLVL_DEST2REG2 BSP_FLD32(13)
     237#define TMS570_DMM_INTLVL_DEST2REG2 BSP_BIT32(13)
    238238
    239239/* field: DEST2REG1 - Destination 2 Region 1 Interrupt Level */
    240 #define TMS570_DMM_INTLVL_DEST2REG1 BSP_FLD32(12)
     240#define TMS570_DMM_INTLVL_DEST2REG1 BSP_BIT32(12)
    241241
    242242/* field: DEST1REG2 - Destination 1 Region 2 Interrupt Level */
    243 #define TMS570_DMM_INTLVL_DEST1REG2 BSP_FLD32(11)
     243#define TMS570_DMM_INTLVL_DEST1REG2 BSP_BIT32(11)
    244244
    245245/* field: DEST1REG1 - Destination 1 Region 1 Interrupt Level */
    246 #define TMS570_DMM_INTLVL_DEST1REG1 BSP_FLD32(10)
     246#define TMS570_DMM_INTLVL_DEST1REG1 BSP_BIT32(10)
    247247
    248248/* field: DEST0REG2 - Destination 0 Region 2 Interrupt Level */
    249 #define TMS570_DMM_INTLVL_DEST0REG2 BSP_FLD32(9)
     249#define TMS570_DMM_INTLVL_DEST0REG2 BSP_BIT32(9)
    250250
    251251/* field: DEST0REG1 - Destination 0 Region 1 Interrupt Level */
    252 #define TMS570_DMM_INTLVL_DEST0REG1 BSP_FLD32(8)
     252#define TMS570_DMM_INTLVL_DEST0REG1 BSP_BIT32(8)
    253253
    254254/* field: BUSERROR - BMM Bus Error Response */
    255 #define TMS570_DMM_INTLVL_BUSERROR BSP_FLD32(7)
     255#define TMS570_DMM_INTLVL_BUSERROR BSP_BIT32(7)
    256256
    257257/* field: BUFF_OVF - Write Buffer Overflow Interrupt Level */
    258 #define TMS570_DMM_INTLVL_BUFF_OVF BSP_FLD32(6)
     258#define TMS570_DMM_INTLVL_BUFF_OVF BSP_BIT32(6)
    259259
    260260/* field: SRC_OVF - Source Overflow Interrupt Level */
    261 #define TMS570_DMM_INTLVL_SRC_OVF BSP_FLD32(5)
     261#define TMS570_DMM_INTLVL_SRC_OVF BSP_BIT32(5)
    262262
    263263/* field: DEST3_ERR - Destination 3 Error Interrupt Level */
    264 #define TMS570_DMM_INTLVL_DEST3_ERR BSP_FLD32(4)
     264#define TMS570_DMM_INTLVL_DEST3_ERR BSP_BIT32(4)
    265265
    266266/* field: DEST2_ERR - Destination 2 Error Interrupt Level */
    267 #define TMS570_DMM_INTLVL_DEST2_ERR BSP_FLD32(3)
     267#define TMS570_DMM_INTLVL_DEST2_ERR BSP_BIT32(3)
    268268
    269269/* field: DEST1_ERR - Destination 1 Error Interrupt Level */
    270 #define TMS570_DMM_INTLVL_DEST1_ERR BSP_FLD32(2)
     270#define TMS570_DMM_INTLVL_DEST1_ERR BSP_BIT32(2)
    271271
    272272/* field: DEST0_ERR - Destination 0 Error Interrupt Level */
    273 #define TMS570_DMM_INTLVL_DEST0_ERR BSP_FLD32(1)
     273#define TMS570_DMM_INTLVL_DEST0_ERR BSP_BIT32(1)
    274274
    275275/* field: PACKET_ERR_INT - Packet Error Interrupt Level */
    276 #define TMS570_DMM_INTLVL_PACKET_ERR_INT BSP_FLD32(0)
    277 
    278 
    279 /*----------------------TMS570_DMMINTFLG----------------------*/
     276#define TMS570_DMM_INTLVL_PACKET_ERR_INT BSP_BIT32(0)
     277
     278
     279/*---------------------TMS570_DMM_INTFLG---------------------*/
    280280/* field: PROG_BUFF - Programmable Buffer Interrupt Flag */
    281 #define TMS570_DMM_INTFLG_PROG_BUFF BSP_FLD32(17)
     281#define TMS570_DMM_INTFLG_PROG_BUFF BSP_BIT32(17)
    282282
    283283/* field: EO_BUFF - End of Buffer Interrupt Flag */
    284 #define TMS570_DMM_INTFLG_EO_BUFF BSP_FLD32(16)
     284#define TMS570_DMM_INTFLG_EO_BUFF BSP_BIT32(16)
    285285
    286286/* field: DEST3REG2 - Destination 3 Region 2 Interrupt Flag */
    287 #define TMS570_DMM_INTFLG_DEST3REG2 BSP_FLD32(15)
     287#define TMS570_DMM_INTFLG_DEST3REG2 BSP_BIT32(15)
    288288
    289289/* field: DEST3REG1 - Destination 3 Region 1 Interrupt Flag */
    290 #define TMS570_DMM_INTFLG_DEST3REG1 BSP_FLD32(14)
     290#define TMS570_DMM_INTFLG_DEST3REG1 BSP_BIT32(14)
    291291
    292292/* field: DEST2REG2 - Destination 2 Region 2 Interrupt Flag */
    293 #define TMS570_DMM_INTFLG_DEST2REG2 BSP_FLD32(13)
     293#define TMS570_DMM_INTFLG_DEST2REG2 BSP_BIT32(13)
    294294
    295295/* field: DEST2REG1 - Destination 2 Region 1 Interrupt Flag */
    296 #define TMS570_DMM_INTFLG_DEST2REG1 BSP_FLD32(12)
     296#define TMS570_DMM_INTFLG_DEST2REG1 BSP_BIT32(12)
    297297
    298298/* field: DEST1REG2 - Destination 1 Region 2 Interrupt Flag */
    299 #define TMS570_DMM_INTFLG_DEST1REG2 BSP_FLD32(11)
     299#define TMS570_DMM_INTFLG_DEST1REG2 BSP_BIT32(11)
    300300
    301301/* field: DEST1REG1 - Destination 1 Region 1 Interrupt Flag */
    302 #define TMS570_DMM_INTFLG_DEST1REG1 BSP_FLD32(10)
     302#define TMS570_DMM_INTFLG_DEST1REG1 BSP_BIT32(10)
    303303
    304304/* field: DEST0REG2 - Destination 0 Region 2 Interrupt Flag */
    305 #define TMS570_DMM_INTFLG_DEST0REG2 BSP_FLD32(9)
     305#define TMS570_DMM_INTFLG_DEST0REG2 BSP_BIT32(9)
    306306
    307307/* field: DEST0REG1 - Destination 0 Region 1 Interrupt Flag */
    308 #define TMS570_DMM_INTFLG_DEST0REG1 BSP_FLD32(8)
     308#define TMS570_DMM_INTFLG_DEST0REG1 BSP_BIT32(8)
    309309
    310310/* field: BUSERROR - BMM Bus Error Response. */
    311 #define TMS570_DMM_INTFLG_BUSERROR BSP_FLD32(7)
     311#define TMS570_DMM_INTFLG_BUSERROR BSP_BIT32(7)
    312312
    313313/* field: BUFF_OVF - Write Buffer Overflow Interrupt Flag */
    314 #define TMS570_DMM_INTFLG_BUFF_OVF BSP_FLD32(6)
     314#define TMS570_DMM_INTFLG_BUFF_OVF BSP_BIT32(6)
    315315
    316316/* field: SRC_OVF - Source Overflow Interrupt Flag */
    317 #define TMS570_DMM_INTFLG_SRC_OVF BSP_FLD32(5)
     317#define TMS570_DMM_INTFLG_SRC_OVF BSP_BIT32(5)
    318318
    319319/* field: DEST3_ERR - Destination 3 Error Interrupt Flag */
    320 #define TMS570_DMM_INTFLG_DEST3_ERR BSP_FLD32(4)
     320#define TMS570_DMM_INTFLG_DEST3_ERR BSP_BIT32(4)
    321321
    322322/* field: DEST2_ERR - Destination 2 Error Interrupt Flag */
    323 #define TMS570_DMM_INTFLG_DEST2_ERR BSP_FLD32(3)
     323#define TMS570_DMM_INTFLG_DEST2_ERR BSP_BIT32(3)
    324324
    325325/* field: DEST1_ERR - Destination 1 Error Interrupt Flag */
    326 #define TMS570_DMM_INTFLG_DEST1_ERR BSP_FLD32(2)
     326#define TMS570_DMM_INTFLG_DEST1_ERR BSP_BIT32(2)
    327327
    328328/* field: DEST0_ERR - Destination 0 Error Interrupt Flag */
    329 #define TMS570_DMM_INTFLG_DEST0_ERR BSP_FLD32(1)
     329#define TMS570_DMM_INTFLG_DEST0_ERR BSP_BIT32(1)
    330330
    331331/* field: PACKET_ERR_INT - Packet Error Interrupt Flag */
    332 #define TMS570_DMM_INTFLG_PACKET_ERR_INT BSP_FLD32(0)
    333 
    334 
    335 /*-----------------------TMS570_DMMOFF1-----------------------*/
     332#define TMS570_DMM_INTFLG_PACKET_ERR_INT BSP_BIT32(0)
     333
     334
     335/*----------------------TMS570_DMM_OFF1----------------------*/
    336336/* field: OFFSET - User and privilege mode (read): */
    337337#define TMS570_DMM_OFF1_OFFSET(val) BSP_FLD32(val,0, 4)
     
    340340
    341341
    342 /*-----------------------TMS570_DMMOFF2-----------------------*/
     342/*----------------------TMS570_DMM_OFF2----------------------*/
    343343/* field: OFFSET - User and privilege mode (read): */
    344344#define TMS570_DMM_OFF2_OFFSET(val) BSP_FLD32(val,0, 4)
     
    347347
    348348
    349 /*---------------------TMS570_DMMDDMDEST---------------------*/
     349/*---------------------TMS570_DMM_DDMDEST---------------------*/
    350350/* field: STARTADDR - These bits define the starting address of the buffer. */
    351 #define TMS570_DMM_DDMDEST_STARTADDR(val) BSP_FLD32(val,0, 31)
    352 #define TMS570_DMM_DDMDEST_STARTADDR_GET(reg) BSP_FLD32GET(reg,0, 31)
    353 #define TMS570_DMM_DDMDEST_STARTADDR_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
    354 
    355 
    356 /*----------------------TMS570_DMMDDMBL----------------------*/
     351/* Whole 32 bits */
     352
     353/*----------------------TMS570_DMM_DDMBL----------------------*/
    357354/* field: BLOCKSIZE - These bits define the size of the buffer region */
    358355#define TMS570_DMM_DDMBL_BLOCKSIZE(val) BSP_FLD32(val,0, 3)
     
    361358
    362359
    363 /*----------------------TMS570_DMMDDMPT----------------------*/
     360/*----------------------TMS570_DMM_DDMPT----------------------*/
    364361/* field: POINTER - These bits hold the pointer to the next entry to be written in the buffer. */
    365362#define TMS570_DMM_DDMPT_POINTER(val) BSP_FLD32(val,0, 14)
     
    368365
    369366
    370 /*----------------------TMS570_DMMINTPT----------------------*/
     367/*----------------------TMS570_DMM_INTPT----------------------*/
    371368/* field: INTPT - Interrupt Pointer. When the buffer pointer (Section 30.3. */
    372369#define TMS570_DMM_INTPT_INTPT(val) BSP_FLD32(val,0, 14)
     
    375372
    376373
    377 /*--------------------TMS570_DMMDEST0REG1--------------------*/
     374/*--------------------TMS570_DMM_DESTxREG1--------------------*/
    378375/* field: BASEADDR - These bits define the base address of the 256kB region where the buffer is located. */
    379 #define TMS570_DMM_DEST0REG1_BASEADDR(val) BSP_FLD32(val,18, 31)
    380 #define TMS570_DMM_DEST0REG1_BASEADDR_GET(reg) BSP_FLD32GET(reg,18, 31)
    381 #define TMS570_DMM_DEST0REG1_BASEADDR_SET(reg,val) BSP_FLD32SET(reg, val,18, 31)
     376#define TMS570_DMM_DESTxREG1_BASEADDR(val) BSP_FLD32(val,18, 31)
     377#define TMS570_DMM_DESTxREG1_BASEADDR_GET(reg) BSP_FLD32GET(reg,18, 31)
     378#define TMS570_DMM_DESTxREG1_BASEADDR_SET(reg,val) BSP_FLD32SET(reg, val,18, 31)
    382379
    383380/* field: BLOCKADDR - These bits define the starting address of the buffer in the 256kB page. */
    384 #define TMS570_DMM_DEST0REG1_BLOCKADDR(val) BSP_FLD32(val,0, 17)
    385 #define TMS570_DMM_DEST0REG1_BLOCKADDR_GET(reg) BSP_FLD32GET(reg,0, 17)
    386 #define TMS570_DMM_DEST0REG1_BLOCKADDR_SET(reg,val) BSP_FLD32SET(reg, val,0, 17)
    387 
    388 
    389 /*---------------------TMS570_DMMDEST0BL1---------------------*/
     381#define TMS570_DMM_DESTxREG1_BLOCKADDR(val) BSP_FLD32(val,0, 17)
     382#define TMS570_DMM_DESTxREG1_BLOCKADDR_GET(reg) BSP_FLD32GET(reg,0, 17)
     383#define TMS570_DMM_DESTxREG1_BLOCKADDR_SET(reg,val) BSP_FLD32SET(reg, val,0, 17)
     384
     385
     386/*--------------------TMS570_DMM_DESTxBL1--------------------*/
    390387/* field: BLOCKSIZE - These bits define the length of the buffer region. */
    391 #define TMS570_DMM_DEST0BL1_BLOCKSIZE(val) BSP_FLD32(val,0, 3)
    392 #define TMS570_DMM_DEST0BL1_BLOCKSIZE_GET(reg) BSP_FLD32GET(reg,0, 3)
    393 #define TMS570_DMM_DEST0BL1_BLOCKSIZE_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
    394 
    395 
    396 /*--------------------TMS570_DMMDEST0REG2--------------------*/
     388#define TMS570_DMM_DESTxBL1_BLOCKSIZE(val) BSP_FLD32(val,0, 3)
     389#define TMS570_DMM_DESTxBL1_BLOCKSIZE_GET(reg) BSP_FLD32GET(reg,0, 3)
     390#define TMS570_DMM_DESTxBL1_BLOCKSIZE_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
     391
     392
     393/*--------------------TMS570_DMM_DESTxREG2--------------------*/
    397394/* field: BASEADDR - These bits define the base address of the 256kB region where the buffer is located. */
    398 #define TMS570_DMM_DEST0REG2_BASEADDR(val) BSP_FLD32(val,18, 31)
    399 #define TMS570_DMM_DEST0REG2_BASEADDR_GET(reg) BSP_FLD32GET(reg,18, 31)
    400 #define TMS570_DMM_DEST0REG2_BASEADDR_SET(reg,val) BSP_FLD32SET(reg, val,18, 31)
     395#define TMS570_DMM_DESTxREG2_BASEADDR(val) BSP_FLD32(val,18, 31)
     396#define TMS570_DMM_DESTxREG2_BASEADDR_GET(reg) BSP_FLD32GET(reg,18, 31)
     397#define TMS570_DMM_DESTxREG2_BASEADDR_SET(reg,val) BSP_FLD32SET(reg, val,18, 31)
    401398
    402399/* field: BLOCKADDR - These bits define the starting address of the buffer in the 256kB page. */
    403 #define TMS570_DMM_DEST0REG2_BLOCKADDR(val) BSP_FLD32(val,0, 17)
    404 #define TMS570_DMM_DEST0REG2_BLOCKADDR_GET(reg) BSP_FLD32GET(reg,0, 17)
    405 #define TMS570_DMM_DEST0REG2_BLOCKADDR_SET(reg,val) BSP_FLD32SET(reg, val,0, 17)
    406 
    407 
    408 /*---------------------TMS570_DMMDEST0BL2---------------------*/
     400#define TMS570_DMM_DESTxREG2_BLOCKADDR(val) BSP_FLD32(val,0, 17)
     401#define TMS570_DMM_DESTxREG2_BLOCKADDR_GET(reg) BSP_FLD32GET(reg,0, 17)
     402#define TMS570_DMM_DESTxREG2_BLOCKADDR_SET(reg,val) BSP_FLD32SET(reg, val,0, 17)
     403
     404
     405/*--------------------TMS570_DMM_DESTxBL2--------------------*/
    409406/* field: BLOCKSIZE - These bits define the length of the buffer region. */
    410 #define TMS570_DMM_DEST0BL2_BLOCKSIZE(val) BSP_FLD32(val,0, 3)
    411 #define TMS570_DMM_DEST0BL2_BLOCKSIZE_GET(reg) BSP_FLD32GET(reg,0, 3)
    412 #define TMS570_DMM_DEST0BL2_BLOCKSIZE_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
    413 
    414 
    415 /*-----------------------TMS570_DMMPC0-----------------------*/
     407#define TMS570_DMM_DESTxBL2_BLOCKSIZE(val) BSP_FLD32(val,0, 3)
     408#define TMS570_DMM_DESTxBL2_BLOCKSIZE_GET(reg) BSP_FLD32GET(reg,0, 3)
     409#define TMS570_DMM_DESTxBL2_BLOCKSIZE_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
     410
     411
     412/*-----------------------TMS570_DMM_PC0-----------------------*/
    416413/* field: ENAFUNC - Functional mode of DMMENA pin. */
    417 #define TMS570_DMM_PC0_ENAFUNC BSP_FLD32(18)
     414#define TMS570_DMM_PC0_ENAFUNC BSP_BIT32(18)
    418415
    419416/* field: DATAxFUNC - Functional mode of DMMDATA[x] pin. */
     
    423420
    424421/* field: CLKFUNC - Functional mode of DMMCLK pin. */
    425 #define TMS570_DMM_PC0_CLKFUNC BSP_FLD32(1)
     422#define TMS570_DMM_PC0_CLKFUNC BSP_BIT32(1)
    426423
    427424/* field: SYNCFUNC - Functional mode of DMMSYNC pin. */
    428 #define TMS570_DMM_PC0_SYNCFUNC BSP_FLD32(0)
    429 
    430 
    431 /*-----------------------TMS570_DMMPC1-----------------------*/
     425#define TMS570_DMM_PC0_SYNCFUNC BSP_BIT32(0)
     426
     427
     428/*-----------------------TMS570_DMM_PC1-----------------------*/
    432429/* field: ENADIR - Direction of DMMENA pin. */
    433 #define TMS570_DMM_PC1_ENADIR BSP_FLD32(18)
     430#define TMS570_DMM_PC1_ENADIR BSP_BIT32(18)
    434431
    435432/* field: DATAxDIR - Direction of DMMDATA[x] pin. */
     
    439436
    440437/* field: CLKDIR - Direction of DMMCLK pin. */
    441 #define TMS570_DMM_PC1_CLKDIR BSP_FLD32(1)
     438#define TMS570_DMM_PC1_CLKDIR BSP_BIT32(1)
    442439
    443440/* field: SYNCDIR - Direction of DMMSYNC pin. */
    444 #define TMS570_DMM_PC1_SYNCDIR BSP_FLD32(0)
    445 
    446 
    447 /*-----------------------TMS570_DMMPC2-----------------------*/
     441#define TMS570_DMM_PC1_SYNCDIR BSP_BIT32(0)
     442
     443
     444/*-----------------------TMS570_DMM_PC2-----------------------*/
    448445/* field: ENAIN - DMMENA input. This bit reflects the state of the pin in all modes. */
    449 #define TMS570_DMM_PC2_ENAIN BSP_FLD32(18)
     446#define TMS570_DMM_PC2_ENAIN BSP_BIT32(18)
    450447
    451448/* field: DATAxIN - DMMDATA[x] input. This bit reflects the state of the pin in all modes. */
     
    455452
    456453/* field: CLKIN - DMMCLK input. This bit reflects the state of the pin in all modes. */
    457 #define TMS570_DMM_PC2_CLKIN BSP_FLD32(1)
     454#define TMS570_DMM_PC2_CLKIN BSP_BIT32(1)
    458455
    459456/* field: SYNCIN - DMMSYNC input. */
    460 #define TMS570_DMM_PC2_SYNCIN BSP_FLD32(0)
    461 
    462 
    463 /*-----------------------TMS570_DMMPC3-----------------------*/
     457#define TMS570_DMM_PC2_SYNCIN BSP_BIT32(0)
     458
     459
     460/*-----------------------TMS570_DMM_PC3-----------------------*/
    464461/* field: ENAOUT - Output state of DMMENA pin. */
    465 #define TMS570_DMM_PC3_ENAOUT BSP_FLD32(18)
     462#define TMS570_DMM_PC3_ENAOUT BSP_BIT32(18)
    466463
    467464/* field: DATAxOUT - Output state of DMMDATA[x] pin. This bit sets the pin to logic low or high level. */
     
    471468
    472469/* field: CLKOUT - Output state of DMMCLK pin. */
    473 #define TMS570_DMM_PC3_CLKOUT BSP_FLD32(1)
     470#define TMS570_DMM_PC3_CLKOUT BSP_BIT32(1)
    474471
    475472/* field: SYNCOUT - Output state of DMMSYNC pin. This bit sets the pin to logic low or high level. */
    476 #define TMS570_DMM_PC3_SYNCOUT BSP_FLD32(0)
    477 
    478 
    479 /*-----------------------TMS570_DMMPC4-----------------------*/
     473#define TMS570_DMM_PC3_SYNCOUT BSP_BIT32(0)
     474
     475
     476/*-----------------------TMS570_DMM_PC4-----------------------*/
    480477/* field: ENASET - control register bit to 1 regardless of the current value in the ENAOUT bit. */
    481 #define TMS570_DMM_PC4_ENASET BSP_FLD32(18)
     478#define TMS570_DMM_PC4_ENASET BSP_BIT32(18)
    482479
    483480/* field: DATAxSET - Sets output state of DMMDATA[x] pin to logic high. */
     
    487484
    488485/* field: CLKSET - Sets output state of DMMCLK pin to logic high. */
    489 #define TMS570_DMM_PC4_CLKSET BSP_FLD32(1)
     486#define TMS570_DMM_PC4_CLKSET BSP_BIT32(1)
    490487
    491488/* field: SYNCSET - Sets output state of DMMSYNC pin logic high. */
    492 #define TMS570_DMM_PC4_SYNCSET BSP_FLD32(0)
    493 
    494 
    495 /*-----------------------TMS570_DMMPC5-----------------------*/
     489#define TMS570_DMM_PC4_SYNCSET BSP_BIT32(0)
     490
     491
     492/*-----------------------TMS570_DMM_PC5-----------------------*/
    496493/* field: ENACLR - Sets output state of DMMENA pin to logic low. */
    497 #define TMS570_DMM_PC5_ENACLR BSP_FLD32(18)
     494#define TMS570_DMM_PC5_ENACLR BSP_BIT32(18)
    498495
    499496/* field: DATAxCLR - Sets output state of DMMDATA[x] pin to logic low. */
     
    503500
    504501/* field: CLKCLR - Sets output state of DMMCLK pin to logic low. */
    505 #define TMS570_DMM_PC5_CLKCLR BSP_FLD32(1)
     502#define TMS570_DMM_PC5_CLKCLR BSP_BIT32(1)
    506503
    507504/* field: SYNCCLR - Sets output state of DMMSYNC pin to logic low. */
    508 #define TMS570_DMM_PC5_SYNCCLR BSP_FLD32(0)
    509 
    510 
    511 /*-----------------------TMS570_DMMPC6-----------------------*/
     505#define TMS570_DMM_PC5_SYNCCLR BSP_BIT32(0)
     506
     507
     508/*-----------------------TMS570_DMM_PC6-----------------------*/
    512509/* field: ENAPDR - Open Drain enable. */
    513 #define TMS570_DMM_PC6_ENAPDR BSP_FLD32(18)
     510#define TMS570_DMM_PC6_ENAPDR BSP_BIT32(18)
    514511
    515512/* field: DATAxPDR - Open Drain enable. */
     
    519516
    520517/* field: CLKPDR - Open Drain enable. */
    521 #define TMS570_DMM_PC6_CLKPDR BSP_FLD32(1)
     518#define TMS570_DMM_PC6_CLKPDR BSP_BIT32(1)
    522519
    523520/* field: SYNCPDR - Open Drain enable. */
    524 #define TMS570_DMM_PC6_SYNCPDR BSP_FLD32(0)
    525 
    526 
    527 /*-----------------------TMS570_DMMPC7-----------------------*/
     521#define TMS570_DMM_PC6_SYNCPDR BSP_BIT32(0)
     522
     523
     524/*-----------------------TMS570_DMM_PC7-----------------------*/
    528525/* field: ENAPDIS - Pull disable. */
    529 #define TMS570_DMM_PC7_ENAPDIS BSP_FLD32(18)
     526#define TMS570_DMM_PC7_ENAPDIS BSP_BIT32(18)
    530527
    531528/* field: DATAxPDIS - Pull disable. */
     
    535532
    536533/* field: CLKPDIS - Pull disable. */
    537 #define TMS570_DMM_PC7_CLKPDIS BSP_FLD32(1)
     534#define TMS570_DMM_PC7_CLKPDIS BSP_BIT32(1)
    538535
    539536/* field: SYNCPDIS - Pull disable. */
    540 #define TMS570_DMM_PC7_SYNCPDIS BSP_FLD32(0)
    541 
    542 
    543 /*-----------------------TMS570_DMMPC8-----------------------*/
     537#define TMS570_DMM_PC7_SYNCPDIS BSP_BIT32(0)
     538
     539
     540/*-----------------------TMS570_DMM_PC8-----------------------*/
    544541/* field: ENAPSEL - Pull disable. */
    545 #define TMS570_DMM_PC8_ENAPSEL BSP_FLD32(18)
     542#define TMS570_DMM_PC8_ENAPSEL BSP_BIT32(18)
    546543
    547544/* field: DATAxPSEL - Pull disable. */
     
    551548
    552549/* field: CLKPSEL - Pull disable. */
    553 #define TMS570_DMM_PC8_CLKPSEL BSP_FLD32(1)
     550#define TMS570_DMM_PC8_CLKPSEL BSP_BIT32(1)
    554551
    555552/* field: SYNCPSEL - Pull disable. */
    556 #define TMS570_DMM_PC8_SYNCPSEL BSP_FLD32(0)
    557 
    558 
    559 
    560 #endif /* LIBBSP_ARM_tms570_DMM */
     553#define TMS570_DMM_PC8_SYNCPSEL BSP_BIT32(0)
     554
     555
     556
     557#endif /* LIBBSP_ARM_TMS570_DMM */
  • c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_efuse.h

    r3f923fd2 r9a84f983  
    3737 * either expressed or implied, of the FreeBSD Project.
    3838*/
    39 #ifndef LIBBSP_ARM_tms570_EFUSE
    40 #define LIBBSP_ARM_tms570_EFUSE
     39#ifndef LIBBSP_ARM_TMS570_EFUSE
     40#define LIBBSP_ARM_TMS570_EFUSE
    4141
    4242#include <bsp/utility.h>
     
    5454
    5555
    56 /*--------------------TMS570_EFUSEEFCBOUND--------------------*/
     56/*-------------------TMS570_EFUSE_EFCBOUND-------------------*/
    5757/* field: EFC_Self_Test_Error - This bit drives the self test error signal when bit 17 (Self Test Error OE) is high. */
    58 #define TMS570_EFUSE_EFCBOUND_EFC_Self_Test_Error BSP_FLD32(21)
     58#define TMS570_EFUSE_EFCBOUND_EFC_Self_Test_Error BSP_BIT32(21)
    5959
    6060/* field: EFC_Single_Bit_Error - This bit drives the single bit error signal when bit 16 (Single bit Error OE) is high. */
    61 #define TMS570_EFUSE_EFCBOUND_EFC_Single_Bit_Error BSP_FLD32(20)
     61#define TMS570_EFUSE_EFCBOUND_EFC_Single_Bit_Error BSP_BIT32(20)
    6262
    6363/* field: EFC_Instruction_Error - This bit drives the instruction error signal when bit 15 (Instruction Error OE) is high. */
    64 #define TMS570_EFUSE_EFCBOUND_EFC_Instruction_Error BSP_FLD32(19)
     64#define TMS570_EFUSE_EFCBOUND_EFC_Instruction_Error BSP_BIT32(19)
    6565
    6666/* field: EFC_Autoload_Error - This bit drives the Autoload Error signal when bit 14 (Autoload Error OE) is high. */
    67 #define TMS570_EFUSE_EFCBOUND_EFC_Autoload_Error BSP_FLD32(18)
     67#define TMS570_EFUSE_EFCBOUND_EFC_Autoload_Error BSP_BIT32(18)
    6868
    6969/* field: Self_Test_Error_OE - The Self Test Error Output Enable bit determines if the EFC Self Test signal comes from the */
    70 #define TMS570_EFUSE_EFCBOUND_Self_Test_Error_OE BSP_FLD32(17)
     70#define TMS570_EFUSE_EFCBOUND_Self_Test_Error_OE BSP_BIT32(17)
    7171
    7272/* field: Single_Bit_Error_OE - The single bit error output enable signal determines if the EFC Single Bit Error signal comes */
    73 #define TMS570_EFUSE_EFCBOUND_Single_Bit_Error_OE BSP_FLD32(16)
     73#define TMS570_EFUSE_EFCBOUND_Single_Bit_Error_OE BSP_BIT32(16)
    7474
    7575/* field: Instruction_Error_OE - comes from the eFuse controller or from bit 19 of the boundary register. */
    76 #define TMS570_EFUSE_EFCBOUND_Instruction_Error_OE BSP_FLD32(15)
     76#define TMS570_EFUSE_EFCBOUND_Instruction_Error_OE BSP_BIT32(15)
    7777
    7878/* field: Autoload_Error_OE - The autoload error output enable signal determines if the EFC Autoload Error signal comes */
    79 #define TMS570_EFUSE_EFCBOUND_Autoload_Error_OE BSP_FLD32(14)
     79#define TMS570_EFUSE_EFCBOUND_Autoload_Error_OE BSP_BIT32(14)
    8080
    8181/* field: EFC_ECC_Selftest - The eFuse Controller ECC Selftest Enable bit starts the selftest of the ECC logic if the four */
    82 #define TMS570_EFUSE_EFCBOUND_EFC_ECC_Selftest BSP_FLD32(13)
     82#define TMS570_EFUSE_EFCBOUND_EFC_ECC_Selftest BSP_BIT32(13)
    8383
    8484/* field: Input_Enable - The eFuse Controller ECC Selftest Enable bit starts the selftest of the ECC logic if the four */
     
    8888
    8989
    90 /*--------------------TMS570_EFUSEEFCPINS--------------------*/
     90/*--------------------TMS570_EFUSE_EFCPINS--------------------*/
    9191/* field: EFC_Selftest_Done - This bit can be polled to determine when the EFC ECC selftest is complete */
    92 #define TMS570_EFUSE_EFCPINS_EFC_Selftest_Done BSP_FLD32(15)
     92#define TMS570_EFUSE_EFCPINS_EFC_Selftest_Done BSP_BIT32(15)
    9393
    9494/* field: EFC_Selftest_Error - This bit indicates the pass/fail status of the EFC ECC Selftest once the EFC Selftest Done */
    95 #define TMS570_EFUSE_EFCPINS_EFC_Selftest_Error BSP_FLD32(14)
     95#define TMS570_EFUSE_EFCPINS_EFC_Selftest_Error BSP_BIT32(14)
    9696
    9797/* field: EFC_Single_Bit_Error - This bit indicates if a single bit error was corrected by the ECC logic during the autoload */
    98 #define TMS570_EFUSE_EFCPINS_EFC_Single_Bit_Error BSP_FLD32(12)
     98#define TMS570_EFUSE_EFCPINS_EFC_Single_Bit_Error BSP_BIT32(12)
    9999
    100100/* field: EFC_Instruction_Error - This bit indicates an error occured during a factory test or program operation. */
    101 #define TMS570_EFUSE_EFCPINS_EFC_Instruction_Error BSP_FLD32(11)
     101#define TMS570_EFUSE_EFCPINS_EFC_Instruction_Error BSP_BIT32(11)
    102102
    103103/* field: EFC_Autoload_Error - This bit indicates that some non-correctable error occurred during the autoload sequence */
    104 #define TMS570_EFUSE_EFCPINS_EFC_Autoload_Error BSP_FLD32(10)
     104#define TMS570_EFUSE_EFCPINS_EFC_Autoload_Error BSP_BIT32(10)
    105105
    106106
    107 /*------------------TMS570_EFUSEEFC_ERR_STAT------------------*/
     107/*-----------------TMS570_EFUSE_EFC_ERR_STAT-----------------*/
    108108/* field: Instruc_Done - Instruction done. */
    109 #define TMS570_EFUSE_EFC_ERR_STAT_Instruc_Done BSP_FLD32(5)
     109#define TMS570_EFUSE_EFC_ERR_STAT_Instruc_Done BSP_BIT32(5)
    110110
    111111/* field: Error_Code - The error status of the last instruction executed by the eFuse Controller */
     
    115115
    116116
    117 /*-------------------TMS570_EFUSEEFC_ST_CY-------------------*/
     117/*-------------------TMS570_EFUSE_EFC_ST_CY-------------------*/
    118118/* field: Cycles - This register is used to determine the number of cycles to run the eFuse controller ECC logic self test. */
    119 #define TMS570_EFUSE_EFC_ST_CY_Cycles(val) BSP_FLD32(val,0, 31)
    120 #define TMS570_EFUSE_EFC_ST_CY_Cycles_GET(reg) BSP_FLD32GET(reg,0, 31)
    121 #define TMS570_EFUSE_EFC_ST_CY_Cycles_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
     119/* Whole 32 bits */
     120
     121/*------------------TMS570_EFUSE_EFC_ST_SIG------------------*/
     122/* field: Signature - This register is used to hold the expected signature for the eFuse ECC logic self test. */
     123/* Whole 32 bits */
    122124
    123125
    124 /*-------------------TMS570_EFUSEEFC_ST_SIG-------------------*/
    125 /* field: Signature - This register is used to hold the expected signature for the eFuse ECC logic self test. */
    126 #define TMS570_EFUSE_EFC_ST_SIG_Signature(val) BSP_FLD32(val,0, 31)
    127 #define TMS570_EFUSE_EFC_ST_SIG_Signature_GET(reg) BSP_FLD32GET(reg,0, 31)
    128 #define TMS570_EFUSE_EFC_ST_SIG_Signature_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
    129 
    130 
    131 
    132 #endif /* LIBBSP_ARM_tms570_EFUSE */
     126#endif /* LIBBSP_ARM_TMS570_EFUSE */
  • c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_emac.h

    r3f923fd2 r9a84f983  
    3737 * either expressed or implied, of the FreeBSD Project.
    3838*/
    39 #ifndef LIBBSP_ARM_tms570_EMAC
    40 #define LIBBSP_ARM_tms570_EMAC
     39#ifndef LIBBSP_ARM_TMS570_EMAC
     40#define LIBBSP_ARM_TMS570_EMAC
    4141
    4242#include <bsp/utility.h>
     
    6262
    6363
    64 /*----------------------TMS570_EMACREVID----------------------*/
     64/*---------------------TMS570_EMAC_REVID---------------------*/
    6565/* field: REV - Identifies the MDIO Module revision. */
    66 #define TMS570_EMAC_REVID_REV(val) BSP_FLD32(val,0, 31)
    67 #define TMS570_EMAC_REVID_REV_GET(reg) BSP_FLD32GET(reg,0, 31)
    68 #define TMS570_EMAC_REVID_REV_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
    69 
    70 
    71 /*---------------------TMS570_EMACCONTROL---------------------*/
     66/* Whole 32 bits */
     67
     68/*--------------------TMS570_EMAC_CONTROL--------------------*/
    7269/* field: IDLE - State machine IDLE status bit. */
    73 #define TMS570_EMAC_CONTROL_IDLE BSP_FLD32(31)
     70#define TMS570_EMAC_CONTROL_IDLE BSP_BIT32(31)
    7471
    7572/* field: ENABLE - State machine enable control bit. */
    76 #define TMS570_EMAC_CONTROL_ENABLE BSP_FLD32(30)
     73#define TMS570_EMAC_CONTROL_ENABLE BSP_BIT32(30)
    7774
    7875/* field: HIGHEST_USER_CHANNEL - Highest user channel that is available in the module. It is currently set to 1. */
     
    8279
    8380/* field: PREAMBLE - Preamble disable */
    84 #define TMS570_EMAC_CONTROL_PREAMBLE BSP_FLD32(20)
     81#define TMS570_EMAC_CONTROL_PREAMBLE BSP_BIT32(20)
    8582
    8683/* field: FAULT - Fault indicator. */
    87 #define TMS570_EMAC_CONTROL_FAULT BSP_FLD32(19)
     84#define TMS570_EMAC_CONTROL_FAULT BSP_BIT32(19)
    8885
    8986/* field: FAULTENB - Fault detect enable. */
    90 #define TMS570_EMAC_CONTROL_FAULTENB BSP_FLD32(18)
     87#define TMS570_EMAC_CONTROL_FAULTENB BSP_BIT32(18)
    9188
    9289/* field: CLKDIV - Clock Divider bits. */
     
    9693
    9794
    98 /*----------------------TMS570_EMACALIVE----------------------*/
     95/*---------------------TMS570_EMAC_ALIVE---------------------*/
    9996/* field: ALIVE - MDIO Alive bits. */
    100 #define TMS570_EMAC_ALIVE_ALIVE(val) BSP_FLD32(val,0, 31)
    101 #define TMS570_EMAC_ALIVE_ALIVE_GET(reg) BSP_FLD32GET(reg,0, 31)
    102 #define TMS570_EMAC_ALIVE_ALIVE_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
    103 
    104 
    105 /*----------------------TMS570_EMACLINK----------------------*/
     97/* Whole 32 bits */
     98
     99/*----------------------TMS570_EMAC_LINK----------------------*/
    106100/* field: LINK - MDIO Link state bits. This register is updated after a read of the generic status register of a PHY. */
    107 #define TMS570_EMAC_LINK_LINK(val) BSP_FLD32(val,0, 31)
    108 #define TMS570_EMAC_LINK_LINK_GET(reg) BSP_FLD32GET(reg,0, 31)
    109 #define TMS570_EMAC_LINK_LINK_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
    110 
    111 
    112 /*-------------------TMS570_EMACLINKINTRAW-------------------*/
     101/* Whole 32 bits */
     102
     103/*-------------------TMS570_EMAC_LINKINTRAW-------------------*/
    113104/* field: USERPHY1 - MDIO Link change event, raw value. */
    114 #define TMS570_EMAC_LINKINTRAW_USERPHY1 BSP_FLD32(1)
     105#define TMS570_EMAC_LINKINTRAW_USERPHY1 BSP_BIT32(1)
    115106
    116107/* field: USERPHY0 - MDIO Link change event, raw value. */
    117 #define TMS570_EMAC_LINKINTRAW_USERPHY0 BSP_FLD32(0)
    118 
    119 
    120 /*------------------TMS570_EMACLINKINTMASKED------------------*/
     108#define TMS570_EMAC_LINKINTRAW_USERPHY0 BSP_BIT32(0)
     109
     110
     111/*-----------------TMS570_EMAC_LINKINTMASKED-----------------*/
    121112/* field: USERPHY1 - MDIO Link change interrupt, masked value. */
    122 #define TMS570_EMAC_LINKINTMASKED_USERPHY1 BSP_FLD32(1)
     113#define TMS570_EMAC_LINKINTMASKED_USERPHY1 BSP_BIT32(1)
    123114
    124115/* field: USERPHY0 - MDIO Link change interrupt, masked value. */
    125 #define TMS570_EMAC_LINKINTMASKED_USERPHY0 BSP_FLD32(0)
    126 
    127 
    128 /*-------------------TMS570_EMACUSERINTRAW-------------------*/
     116#define TMS570_EMAC_LINKINTMASKED_USERPHY0 BSP_BIT32(0)
     117
     118
     119/*-------------------TMS570_EMAC_USERINTRAW-------------------*/
    129120/* field: USERACCESS1 - MDIO User command complete event bit. */
    130 #define TMS570_EMAC_USERINTRAW_USERACCESS1 BSP_FLD32(1)
     121#define TMS570_EMAC_USERINTRAW_USERACCESS1 BSP_BIT32(1)
    131122
    132123/* field: USERACCESS0 - MDIO User command complete event bit. */
    133 #define TMS570_EMAC_USERINTRAW_USERACCESS0 BSP_FLD32(0)
    134 
    135 
    136 /*------------------TMS570_EMACUSERINTMASKED------------------*/
     124#define TMS570_EMAC_USERINTRAW_USERACCESS0 BSP_BIT32(0)
     125
     126
     127/*-----------------TMS570_EMAC_USERINTMASKED-----------------*/
    137128/* field: USERACCESS1 - Masked value of MDIO User command complete interrupt. */
    138 #define TMS570_EMAC_USERINTMASKED_USERACCESS1 BSP_FLD32(1)
     129#define TMS570_EMAC_USERINTMASKED_USERACCESS1 BSP_BIT32(1)
    139130
    140131/* field: USERACCESS0 - Masked value of MDIO User command complete interrupt. */
    141 #define TMS570_EMAC_USERINTMASKED_USERACCESS0 BSP_FLD32(0)
    142 
    143 
    144 /*-----------------TMS570_EMACUSERINTMASKSET-----------------*/
     132#define TMS570_EMAC_USERINTMASKED_USERACCESS0 BSP_BIT32(0)
     133
     134
     135/*-----------------TMS570_EMAC_USERINTMASKSET-----------------*/
    145136/* field: USERACCESS1 - MDIO user interrupt mask set for USERINTMASKED[1]. */
    146 #define TMS570_EMAC_USERINTMASKSET_USERACCESS1 BSP_FLD32(1)
     137#define TMS570_EMAC_USERINTMASKSET_USERACCESS1 BSP_BIT32(1)
    147138
    148139/* field: USERACCESS0 - MDIO user interrupt mask set for USERINTMASKED[0]. */
    149 #define TMS570_EMAC_USERINTMASKSET_USERACCESS0 BSP_FLD32(0)
    150 
    151 
    152 /*----------------TMS570_EMACUSERINTMASKCLEAR----------------*/
     140#define TMS570_EMAC_USERINTMASKSET_USERACCESS0 BSP_BIT32(0)
     141
     142
     143/*----------------TMS570_EMAC_USERINTMASKCLEAR----------------*/
    153144/* field: USERACCESS1 - MDIO user command complete interrupt mask clear for USERINTMASKED[1]. */
    154 #define TMS570_EMAC_USERINTMASKCLEAR_USERACCESS1 BSP_FLD32(1)
     145#define TMS570_EMAC_USERINTMASKCLEAR_USERACCESS1 BSP_BIT32(1)
    155146
    156147/* field: USERACCESS0 - MDIO user command complete interrupt mask clear for USERINTMASKED[0]. */
    157 #define TMS570_EMAC_USERINTMASKCLEAR_USERACCESS0 BSP_FLD32(0)
    158 
    159 
    160 /*-------------------TMS570_EMACUSERACCESS0-------------------*/
     148#define TMS570_EMAC_USERINTMASKCLEAR_USERACCESS0 BSP_BIT32(0)
     149
     150
     151/*------------------TMS570_EMAC_USERACCESS0------------------*/
    161152/* field: GO - Go bit. */
    162 #define TMS570_EMAC_USERACCESS0_GO BSP_FLD32(31)
     153#define TMS570_EMAC_USERACCESS0_GO BSP_BIT32(31)
    163154
    164155/* field: WRITE - Write enable bit. */
    165 #define TMS570_EMAC_USERACCESS0_WRITE BSP_FLD32(30)
     156#define TMS570_EMAC_USERACCESS0_WRITE BSP_BIT32(30)
    166157
    167158/* field: ACK - Acknowledge bit. This bit is set if the PHY acknowledged the read transaction. */
    168 #define TMS570_EMAC_USERACCESS0_ACK BSP_FLD32(29)
     159#define TMS570_EMAC_USERACCESS0_ACK BSP_BIT32(29)
    169160
    170161/* field: REGADR - Register address bits. */
     
    184175
    185176
    186 /*-------------------TMS570_EMACUSERPHYSEL0-------------------*/
     177/*------------------TMS570_EMAC_USERPHYSEL0------------------*/
    187178/* field: LINKSEL - Link status determination select bit. */
    188 #define TMS570_EMAC_USERPHYSEL0_LINKSEL BSP_FLD32(7)
     179#define TMS570_EMAC_USERPHYSEL0_LINKSEL BSP_BIT32(7)
    189180
    190181/* field: LINKINTENB - Link change interrupt enable. */
    191 #define TMS570_EMAC_USERPHYSEL0_LINKINTENB BSP_FLD32(6)
     182#define TMS570_EMAC_USERPHYSEL0_LINKINTENB BSP_BIT32(6)
    192183
    193184/* field: PHYADRMON - PHY address whose link status is to be monitored. */
     
    197188
    198189
    199 /*-------------------TMS570_EMACUSERACCESS1-------------------*/
     190/*------------------TMS570_EMAC_USERACCESS1------------------*/
    200191/* field: GO - Go bit. */
    201 #define TMS570_EMAC_USERACCESS1_GO BSP_FLD32(31)
     192#define TMS570_EMAC_USERACCESS1_GO BSP_BIT32(31)
    202193
    203194/* field: WRITE - Write enable bit. */
    204 #define TMS570_EMAC_USERACCESS1_WRITE BSP_FLD32(30)
     195#define TMS570_EMAC_USERACCESS1_WRITE BSP_BIT32(30)
    205196
    206197/* field: ACK - Acknowledge bit. This bit is set if the PHY acknowledged the read transaction. */
    207 #define TMS570_EMAC_USERACCESS1_ACK BSP_FLD32(29)
     198#define TMS570_EMAC_USERACCESS1_ACK BSP_BIT32(29)
    208199
    209200/* field: REGADR - Register address bits. */
     
    223214
    224215
    225 /*-------------------TMS570_EMACUSERPHYSEL1-------------------*/
     216/*------------------TMS570_EMAC_USERPHYSEL1------------------*/
    226217/* field: LINKSEL - Link status determination select bit. */
    227 #define TMS570_EMAC_USERPHYSEL1_LINKSEL BSP_FLD32(7)
     218#define TMS570_EMAC_USERPHYSEL1_LINKSEL BSP_BIT32(7)
    228219
    229220/* field: LINKINTENB - Link change interrupt enable. */
    230 #define TMS570_EMAC_USERPHYSEL1_LINKINTENB BSP_FLD32(6)
     221#define TMS570_EMAC_USERPHYSEL1_LINKINTENB BSP_BIT32(6)
    231222
    232223/* field: PHYADRMON - PHY address whose link status is to be monitored. */
     
    237228
    238229
    239 #endif /* LIBBSP_ARM_tms570_EMAC */
     230#endif /* LIBBSP_ARM_TMS570_EMAC */
  • c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_emacm.h

    r3f923fd2 r9a84f983  
    3737 * either expressed or implied, of the FreeBSD Project.
    3838*/
    39 #ifndef LIBBSP_ARM_tms570_EMACM
    40 #define LIBBSP_ARM_tms570_EMACM
     39#ifndef LIBBSP_ARM_TMS570_EMACM
     40#define LIBBSP_ARM_TMS570_EMACM
    4141
    4242#include <bsp/utility.h>
     
    103103
    104104
    105 /*--------------------TMS570_EMACMTXREVID--------------------*/
     105/*--------------------TMS570_EMACM_TXREVID--------------------*/
    106106/* field: TXREV - Transmit module revision */
    107 #define TMS570_EMACM_TXREVID_TXREV(val) BSP_FLD32(val,0, 31)
    108 #define TMS570_EMACM_TXREVID_TXREV_GET(reg) BSP_FLD32GET(reg,0, 31)
    109 #define TMS570_EMACM_TXREVID_TXREV_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
    110 
    111 
    112 /*-------------------TMS570_EMACMTXCONTROL-------------------*/
     107/* Whole 32 bits */
     108
     109/*-------------------TMS570_EMACM_TXCONTROL-------------------*/
    113110/* field: TXEN - Transmit enable */
    114 #define TMS570_EMACM_TXCONTROL_TXEN BSP_FLD32(0)
    115 
    116 
    117 /*-------------------TMS570_EMACMTXTEARDOWN-------------------*/
     111#define TMS570_EMACM_TXCONTROL_TXEN BSP_BIT32(0)
     112
     113
     114/*------------------TMS570_EMACM_TXTEARDOWN------------------*/
    118115/* field: TXTDNCH - Transmit teardown channel. */
    119116#define TMS570_EMACM_TXTEARDOWN_TXTDNCH(val) BSP_FLD32(val,0, 2)
     
    122119
    123120
    124 /*--------------------TMS570_EMACMRXREVID--------------------*/
     121/*--------------------TMS570_EMACM_RXREVID--------------------*/
    125122/* field: RXREV - Receive module revision */
    126 #define TMS570_EMACM_RXREVID_RXREV(val) BSP_FLD32(val,0, 31)
    127 #define TMS570_EMACM_RXREVID_RXREV_GET(reg) BSP_FLD32GET(reg,0, 31)
    128 #define TMS570_EMACM_RXREVID_RXREV_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
    129 
    130 
    131 /*-------------------TMS570_EMACMRXCONTROL-------------------*/
     123/* Whole 32 bits */
     124
     125/*-------------------TMS570_EMACM_RXCONTROL-------------------*/
    132126/* field: RXEN - Receive enable */
    133 #define TMS570_EMACM_RXCONTROL_RXEN BSP_FLD32(0)
    134 
    135 
    136 /*-------------------TMS570_EMACMRXTEARDOWN-------------------*/
     127#define TMS570_EMACM_RXCONTROL_RXEN BSP_BIT32(0)
     128
     129
     130/*------------------TMS570_EMACM_RXTEARDOWN------------------*/
    137131/* field: RXTDNCH - Receive teardown channel. */
    138132#define TMS570_EMACM_RXTEARDOWN_RXTDNCH(val) BSP_FLD32(val,0, 2)
     
    141135
    142136
    143 /*------------------TMS570_EMACMTXINTSTATRAW------------------*/
     137/*-----------------TMS570_EMACM_TXINTSTATRAW-----------------*/
    144138/* field: TX7PEND - TX7PEND raw interrupt read (before mask) */
    145 #define TMS570_EMACM_TXINTSTATRAW_TX7PEND BSP_FLD32(7)
     139#define TMS570_EMACM_TXINTSTATRAW_TX7PEND BSP_BIT32(7)
    146140
    147141/* field: TX6PEND - TX6PEND raw interrupt read (before mask) */
    148 #define TMS570_EMACM_TXINTSTATRAW_TX6PEND BSP_FLD32(6)
     142#define TMS570_EMACM_TXINTSTATRAW_TX6PEND BSP_BIT32(6)
    149143
    150144/* field: TX5PEND - TX5PEND raw interrupt read (before mask) */
    151 #define TMS570_EMACM_TXINTSTATRAW_TX5PEND BSP_FLD32(5)
     145#define TMS570_EMACM_TXINTSTATRAW_TX5PEND BSP_BIT32(5)
    152146
    153147/* field: TX4PEND - X4PEND raw interrupt read (before mask) */
    154 #define TMS570_EMACM_TXINTSTATRAW_TX4PEND BSP_FLD32(4)
     148#define TMS570_EMACM_TXINTSTATRAW_TX4PEND BSP_BIT32(4)
    155149
    156150/* field: TX3PEND - TX3PEND raw interrupt read (before mask) */
    157 #define TMS570_EMACM_TXINTSTATRAW_TX3PEND BSP_FLD32(3)
     151#define TMS570_EMACM_TXINTSTATRAW_TX3PEND BSP_BIT32(3)
    158152
    159153/* field: TX2PEND - TX2PEND raw interrupt read (before mask) */
    160 #define TMS570_EMACM_TXINTSTATRAW_TX2PEND BSP_FLD32(2)
     154#define TMS570_EMACM_TXINTSTATRAW_TX2PEND BSP_BIT32(2)
    161155
    162156/* field: TX1PEND - TX1PEND raw interrupt read (before mask) */
    163 #define TMS570_EMACM_TXINTSTATRAW_TX1PEND BSP_FLD32(1)
     157#define TMS570_EMACM_TXINTSTATRAW_TX1PEND BSP_BIT32(1)
    164158
    165159/* field: TX0PEND - TX0PEND raw interrupt read (before mask) */
    166 #define TMS570_EMACM_TXINTSTATRAW_TX0PEND BSP_FLD32(0)
    167 
    168 
    169 /*----------------TMS570_EMACMTXINTSTATMASKED----------------*/
     160#define TMS570_EMACM_TXINTSTATRAW_TX0PEND BSP_BIT32(0)
     161
     162
     163/*----------------TMS570_EMACM_TXINTSTATMASKED----------------*/
    170164/* field: TX7PEND - TX7PEND masked interrupt read */
    171 #define TMS570_EMACM_TXINTSTATMASKED_TX7PEND BSP_FLD32(7)
     165#define TMS570_EMACM_TXINTSTATMASKED_TX7PEND BSP_BIT32(7)
    172166
    173167/* field: TX6PEND - TX6PEND masked interrupt read */
    174 #define TMS570_EMACM_TXINTSTATMASKED_TX6PEND BSP_FLD32(6)
     168#define TMS570_EMACM_TXINTSTATMASKED_TX6PEND BSP_BIT32(6)
    175169
    176170/* field: TX5PEND - TX5PEND masked interrupt read */
    177 #define TMS570_EMACM_TXINTSTATMASKED_TX5PEND BSP_FLD32(5)
     171#define TMS570_EMACM_TXINTSTATMASKED_TX5PEND BSP_BIT32(5)
    178172
    179173/* field: TX4PEND - TX4PEND masked interrupt read */
    180 #define TMS570_EMACM_TXINTSTATMASKED_TX4PEND BSP_FLD32(4)
     174#define TMS570_EMACM_TXINTSTATMASKED_TX4PEND BSP_BIT32(4)
    181175
    182176/* field: TX3PEND - TX3PEND masked interrupt read */
    183 #define TMS570_EMACM_TXINTSTATMASKED_TX3PEND BSP_FLD32(3)
     177#define TMS570_EMACM_TXINTSTATMASKED_TX3PEND BSP_BIT32(3)
    184178
    185179/* field: TX2PEND - TX2PEND masked interrupt read */
    186 #define TMS570_EMACM_TXINTSTATMASKED_TX2PEND BSP_FLD32(2)
     180#define TMS570_EMACM_TXINTSTATMASKED_TX2PEND BSP_BIT32(2)
    187181
    188182/* field: TX1PEND - TX1PEND masked interrupt read */
    189 #define TMS570_EMACM_TXINTSTATMASKED_TX1PEND BSP_FLD32(1)
     183#define TMS570_EMACM_TXINTSTATMASKED_TX1PEND BSP_BIT32(1)
    190184
    191185/* field: TX0PEND - TX0PEND masked interrupt read */
    192 #define TMS570_EMACM_TXINTSTATMASKED_TX0PEND BSP_FLD32(0)
    193 
    194 
    195 /*------------------TMS570_EMACMTXINTMASKSET------------------*/
     186#define TMS570_EMACM_TXINTSTATMASKED_TX0PEND BSP_BIT32(0)
     187
     188
     189/*-----------------TMS570_EMACM_TXINTMASKSET-----------------*/
    196190/* field: TX7MASK - Transmit channel 7 interrupt mask set bit. Write 1 to enable interrupt, a write of 0 has no effect. */
    197 #define TMS570_EMACM_TXINTMASKSET_TX7MASK BSP_FLD32(7)
     191#define TMS570_EMACM_TXINTMASKSET_TX7MASK BSP_BIT32(7)
    198192
    199193/* field: TX6MASK - Transmit channel 6 interrupt mask set bit. Write 1 to enable interrupt, a write of 0 has no effect. */
    200 #define TMS570_EMACM_TXINTMASKSET_TX6MASK BSP_FLD32(6)
     194#define TMS570_EMACM_TXINTMASKSET_TX6MASK BSP_BIT32(6)
    201195
    202196/* field: TX5MASK - Transmit channel 5 interrupt mask set bit. Write 1 to enable interrupt, a write of 0 has no effect. */
    203 #define TMS570_EMACM_TXINTMASKSET_TX5MASK BSP_FLD32(5)
     197#define TMS570_EMACM_TXINTMASKSET_TX5MASK BSP_BIT32(5)
    204198
    205199/* field: TX4MASK - Transmit channel 4 interrupt mask set bit. Write 1 to enable interrupt, a write of 0 has no effect. */
    206 #define TMS570_EMACM_TXINTMASKSET_TX4MASK BSP_FLD32(4)
     200#define TMS570_EMACM_TXINTMASKSET_TX4MASK BSP_BIT32(4)
    207201
    208202/* field: TX3MASK - Transmit channel 3 interrupt mask set bit. Write 1 to enable interrupt, a write of 0 has no effect. */
    209 #define TMS570_EMACM_TXINTMASKSET_TX3MASK BSP_FLD32(3)
     203#define TMS570_EMACM_TXINTMASKSET_TX3MASK BSP_BIT32(3)
    210204
    211205/* field: TX2MASK - Transmit channel 2 interrupt mask set bit. Write 1 to enable interrupt, a write of 0 has no effect. */
    212 #define TMS570_EMACM_TXINTMASKSET_TX2MASK BSP_FLD32(2)
     206#define TMS570_EMACM_TXINTMASKSET_TX2MASK BSP_BIT32(2)
    213207
    214208/* field: TX1MASK - Transmit channel 1 interrupt mask set bit. Write 1 to enable interrupt, a write of 0 has no effect. */
    215 #define TMS570_EMACM_TXINTMASKSET_TX1MASK BSP_FLD32(1)
     209#define TMS570_EMACM_TXINTMASKSET_TX1MASK BSP_BIT32(1)
    216210
    217211/* field: TX0MASK - Transmit channel 0 interrupt mask set bit. Write 1 to enable interrupt, a write of 0 has no effect. */
    218 #define TMS570_EMACM_TXINTMASKSET_TX0MASK BSP_FLD32(0)
    219 
    220 
    221 /*-----------------TMS570_EMACMTXINTMASKCLEAR-----------------*/
     212#define TMS570_EMACM_TXINTMASKSET_TX0MASK BSP_BIT32(0)
     213
     214
     215/*----------------TMS570_EMACM_TXINTMASKCLEAR----------------*/
    222216/* field: TX7MASK - Transmit channel 7 interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect. */
    223 #define TMS570_EMACM_TXINTMASKCLEAR_TX7MASK BSP_FLD32(7)
     217#define TMS570_EMACM_TXINTMASKCLEAR_TX7MASK BSP_BIT32(7)
    224218
    225219/* field: TX6MASK - Transmit channel 6 interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect. */
    226 #define TMS570_EMACM_TXINTMASKCLEAR_TX6MASK BSP_FLD32(6)
     220#define TMS570_EMACM_TXINTMASKCLEAR_TX6MASK BSP_BIT32(6)
    227221
    228222/* field: TX5MASK - Transmit channel 5 interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect. */
    229 #define TMS570_EMACM_TXINTMASKCLEAR_TX5MASK BSP_FLD32(5)
     223#define TMS570_EMACM_TXINTMASKCLEAR_TX5MASK BSP_BIT32(5)
    230224
    231225/* field: TX4MASK - Transmit channel 4 interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect. */
    232 #define TMS570_EMACM_TXINTMASKCLEAR_TX4MASK BSP_FLD32(4)
     226#define TMS570_EMACM_TXINTMASKCLEAR_TX4MASK BSP_BIT32(4)
    233227
    234228/* field: TX3MASK - Transmit channel 3 interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect. */
    235 #define TMS570_EMACM_TXINTMASKCLEAR_TX3MASK BSP_FLD32(3)
     229#define TMS570_EMACM_TXINTMASKCLEAR_TX3MASK BSP_BIT32(3)
    236230
    237231/* field: TX2MASK - Transmit channel 2 interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect. */
    238 #define TMS570_EMACM_TXINTMASKCLEAR_TX2MASK BSP_FLD32(2)
     232#define TMS570_EMACM_TXINTMASKCLEAR_TX2MASK BSP_BIT32(2)
    239233
    240234/* field: TX1MASK - Transmit channel 1 interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect. */
    241 #define TMS570_EMACM_TXINTMASKCLEAR_TX1MASK BSP_FLD32(1)
     235#define TMS570_EMACM_TXINTMASKCLEAR_TX1MASK BSP_BIT32(1)
    242236
    243237/* field: TX0MASK - Transmit channel 0 interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect. */
    244 #define TMS570_EMACM_TXINTMASKCLEAR_TX0MASK BSP_FLD32(0)
    245 
    246 
    247 /*------------------TMS570_EMACMMACINVECTOR------------------*/
     238#define TMS570_EMACM_TXINTMASKCLEAR_TX0MASK BSP_BIT32(0)
     239
     240
     241/*------------------TMS570_EMACM_MACINVECTOR------------------*/
    248242/* field: STATPEND - EMAC module statistics interrupt (STATPEND) pending status bit */
    249 #define TMS570_EMACM_MACINVECTOR_STATPEND BSP_FLD32(27)
     243#define TMS570_EMACM_MACINVECTOR_STATPEND BSP_BIT32(27)
    250244
    251245/* field: HOSTPEND - EMAC module host error interrupt (HOSTPEND) pending status bit */
    252 #define TMS570_EMACM_MACINVECTOR_HOSTPEND BSP_FLD32(26)
     246#define TMS570_EMACM_MACINVECTOR_HOSTPEND BSP_BIT32(26)
    253247
    254248/* field: LINKINT0 - MDIO module USERPHYSEL0 (LINKINT0) status bit */
    255 #define TMS570_EMACM_MACINVECTOR_LINKINT0 BSP_FLD32(25)
     249#define TMS570_EMACM_MACINVECTOR_LINKINT0 BSP_BIT32(25)
    256250
    257251/* field: USERINT0 - MDIO module USERACCESS0 (USERINT0) status bit */
    258 #define TMS570_EMACM_MACINVECTOR_USERINT0 BSP_FLD32(24)
     252#define TMS570_EMACM_MACINVECTOR_USERINT0 BSP_BIT32(24)
    259253
    260254/* field: TXPEND - Transmit channels 0-7 interrupt (TXnPEND) pending status. Bit 16 is TX0PEND. */
     
    274268
    275269
    276 /*------------------TMS570_EMACMMACEOIVECTOR------------------*/
     270/*-----------------TMS570_EMACM_MACEOIVECTOR-----------------*/
    277271/* field: INTVECT - Acknowledge EMAC Control Module Interrupts */
    278272#define TMS570_EMACM_MACEOIVECTOR_INTVECT(val) BSP_FLD32(val,0, 4)
     
    281275
    282276
    283 /*------------------TMS570_EMACMRXINTSTATRAW------------------*/
     277/*-----------------TMS570_EMACM_RXINTSTATRAW-----------------*/
    284278/* field: RX7THRESHPEND - RX7THRESHPEND raw interrupt read (before mask) */
    285 #define TMS570_EMACM_RXINTSTATRAW_RX7THRESHPEND BSP_FLD32(15)
     279#define TMS570_EMACM_RXINTSTATRAW_RX7THRESHPEND BSP_BIT32(15)
    286280
    287281/* field: RX6THRESHPEND - RX6THRESHPEND raw interrupt read (before mask) */
    288 #define TMS570_EMACM_RXINTSTATRAW_RX6THRESHPEND BSP_FLD32(14)
     282#define TMS570_EMACM_RXINTSTATRAW_RX6THRESHPEND BSP_BIT32(14)
    289283
    290284/* field: RX5THRESHPEND - RX5THRESHPEND raw interrupt read (before mask) */
    291 #define TMS570_EMACM_RXINTSTATRAW_RX5THRESHPEND BSP_FLD32(13)
     285#define TMS570_EMACM_RXINTSTATRAW_RX5THRESHPEND BSP_BIT32(13)
    292286
    293287/* field: RX4THRESHPEND - RX4THRESHPEND raw interrupt read (before mask) */
    294 #define TMS570_EMACM_RXINTSTATRAW_RX4THRESHPEND BSP_FLD32(12)
     288#define TMS570_EMACM_RXINTSTATRAW_RX4THRESHPEND BSP_BIT32(12)
    295289
    296290/* field: RX3THRESHPEND - RX3THRESHPEND raw interrupt read (before mask) */
    297 #define TMS570_EMACM_RXINTSTATRAW_RX3THRESHPEND BSP_FLD32(11)
     291#define TMS570_EMACM_RXINTSTATRAW_RX3THRESHPEND BSP_BIT32(11)
    298292
    299293/* field: RX2THRESHPEND - RX2THRESHPEND raw interrupt read (before mask) */
    300 #define TMS570_EMACM_RXINTSTATRAW_RX2THRESHPEND BSP_FLD32(10)
     294#define TMS570_EMACM_RXINTSTATRAW_RX2THRESHPEND BSP_BIT32(10)
    301295
    302296/* field: RX1THRESHPEND - RX1THRESHPEND raw interrupt read (before mask) */
    303 #define TMS570_EMACM_RXINTSTATRAW_RX1THRESHPEND BSP_FLD32(9)
     297#define TMS570_EMACM_RXINTSTATRAW_RX1THRESHPEND BSP_BIT32(9)
    304298
    305299/* field: RX0THRESHPEND - RX0THRESHPEND raw interrupt read (before mask) */
    306 #define TMS570_EMACM_RXINTSTATRAW_RX0THRESHPEND BSP_FLD32(8)
     300#define TMS570_EMACM_RXINTSTATRAW_RX0THRESHPEND BSP_BIT32(8)
    307301
    308302/* field: RX7PEND - RX7PEND raw interrupt read (before mask) */
    309 #define TMS570_EMACM_RXINTSTATRAW_RX7PEND BSP_FLD32(7)
     303#define TMS570_EMACM_RXINTSTATRAW_RX7PEND BSP_BIT32(7)
    310304
    311305/* field: RX6PEND - RX6PEND raw interrupt read (before mask) */
    312 #define TMS570_EMACM_RXINTSTATRAW_RX6PEND BSP_FLD32(6)
     306#define TMS570_EMACM_RXINTSTATRAW_RX6PEND BSP_BIT32(6)
    313307
    314308/* field: RX5PEND - RX5PEND raw interrupt read (before mask) */
    315 #define TMS570_EMACM_RXINTSTATRAW_RX5PEND BSP_FLD32(5)
     309#define TMS570_EMACM_RXINTSTATRAW_RX5PEND BSP_BIT32(5)
    316310
    317311/* field: RX4PEND - RX4PEND raw interrupt read (before mask) */
    318 #define TMS570_EMACM_RXINTSTATRAW_RX4PEND BSP_FLD32(4)
     312#define TMS570_EMACM_RXINTSTATRAW_RX4PEND BSP_BIT32(4)
    319313
    320314/* field: RX3PEND - RX3PEND raw interrupt read (before mask) */
    321 #define TMS570_EMACM_RXINTSTATRAW_RX3PEND BSP_FLD32(3)
     315#define TMS570_EMACM_RXINTSTATRAW_RX3PEND BSP_BIT32(3)
    322316
    323317/* field: RX2PEND - RX2PEND raw interrupt read (before mask) */
    324 #define TMS570_EMACM_RXINTSTATRAW_RX2PEND BSP_FLD32(2)
     318#define TMS570_EMACM_RXINTSTATRAW_RX2PEND BSP_BIT32(2)
    325319
    326320/* field: RX1PEND - RX1PEND raw interrupt read (before mask) */
    327 #define TMS570_EMACM_RXINTSTATRAW_RX1PEND BSP_FLD32(1)
     321#define TMS570_EMACM_RXINTSTATRAW_RX1PEND BSP_BIT32(1)
    328322
    329323/* field: RX0PEND - RX0PEND raw interrupt read (before mask) */
    330 #define TMS570_EMACM_RXINTSTATRAW_RX0PEND BSP_FLD32(0)
    331 
    332 
    333 /*----------------TMS570_EMACMRXINTSTATMASKED----------------*/
     324#define TMS570_EMACM_RXINTSTATRAW_RX0PEND BSP_BIT32(0)
     325
     326
     327/*----------------TMS570_EMACM_RXINTSTATMASKED----------------*/
    334328/* field: RX7THRESHPEND - RX7THRESHPEND masked interrupt read */
    335 #define TMS570_EMACM_RXINTSTATMASKED_RX7THRESHPEND BSP_FLD32(15)
     329#define TMS570_EMACM_RXINTSTATMASKED_RX7THRESHPEND BSP_BIT32(15)
    336330
    337331/* field: RX6THRESHPEND - RX6THRESHPEND masked interrupt read */
    338 #define TMS570_EMACM_RXINTSTATMASKED_RX6THRESHPEND BSP_FLD32(14)
     332#define TMS570_EMACM_RXINTSTATMASKED_RX6THRESHPEND BSP_BIT32(14)
    339333
    340334/* field: RX5THRESHPEND - RX5THRESHPEND masked interrupt read */
    341 #define TMS570_EMACM_RXINTSTATMASKED_RX5THRESHPEND BSP_FLD32(13)
     335#define TMS570_EMACM_RXINTSTATMASKED_RX5THRESHPEND BSP_BIT32(13)
    342336
    343337/* field: RX4THRESHPEND - RX4THRESHPEND masked interrupt read */
    344 #define TMS570_EMACM_RXINTSTATMASKED_RX4THRESHPEND BSP_FLD32(12)
     338#define TMS570_EMACM_RXINTSTATMASKED_RX4THRESHPEND BSP_BIT32(12)
    345339
    346340/* field: RX3THRESHPEND - RX3THRESHPEND masked interrupt read */
    347 #define TMS570_EMACM_RXINTSTATMASKED_RX3THRESHPEND BSP_FLD32(11)
     341#define TMS570_EMACM_RXINTSTATMASKED_RX3THRESHPEND BSP_BIT32(11)
    348342
    349343/* field: RX2THRESHPEND - RX2THRESHPEND masked interrupt read */
    350 #define TMS570_EMACM_RXINTSTATMASKED_RX2THRESHPEND BSP_FLD32(10)
     344#define TMS570_EMACM_RXINTSTATMASKED_RX2THRESHPEND BSP_BIT32(10)
    351345
    352346/* field: RX1THRESHPEND - RX1THRESHPEND masked interrupt read */
    353 #define TMS570_EMACM_RXINTSTATMASKED_RX1THRESHPEND BSP_FLD32(9)
     347#define TMS570_EMACM_RXINTSTATMASKED_RX1THRESHPEND BSP_BIT32(9)
    354348
    355349/* field: RX0THRESHPEND - RX0THRESHPEND masked interrupt read */
    356 #define TMS570_EMACM_RXINTSTATMASKED_RX0THRESHPEND BSP_FLD32(8)
     350#define TMS570_EMACM_RXINTSTATMASKED_RX0THRESHPEND BSP_BIT32(8)
    357351
    358352/* field: RX7PEND - RX7PEND masked interrupt read */
    359 #define TMS570_EMACM_RXINTSTATMASKED_RX7PEND BSP_FLD32(7)
     353#define TMS570_EMACM_RXINTSTATMASKED_RX7PEND BSP_BIT32(7)
    360354
    361355/* field: RX6PEND - RX6PEND masked interrupt read */
    362 #define TMS570_EMACM_RXINTSTATMASKED_RX6PEND BSP_FLD32(6)
     356#define TMS570_EMACM_RXINTSTATMASKED_RX6PEND BSP_BIT32(6)
    363357
    364358/* field: RX5PEND - RX5PEND masked interrupt read */
    365 #define TMS570_EMACM_RXINTSTATMASKED_RX5PEND BSP_FLD32(5)
     359#define TMS570_EMACM_RXINTSTATMASKED_RX5PEND BSP_BIT32(5)
    366360
    367361/* field: RX4PEND - RX4PEND masked interrupt read */
    368 #define TMS570_EMACM_RXINTSTATMASKED_RX4PEND BSP_FLD32(4)
     362#define TMS570_EMACM_RXINTSTATMASKED_RX4PEND BSP_BIT32(4)
    369363
    370364/* field: RX3PEND - RX3PEND masked interrupt read */
    371 #define TMS570_EMACM_RXINTSTATMASKED_RX3PEND BSP_FLD32(3)
     365#define TMS570_EMACM_RXINTSTATMASKED_RX3PEND BSP_BIT32(3)
    372366
    373367/* field: RX2PEND - RX2PEND masked interrupt read */
    374 #define TMS570_EMACM_RXINTSTATMASKED_RX2PEND BSP_FLD32(2)
     368#define TMS570_EMACM_RXINTSTATMASKED_RX2PEND BSP_BIT32(2)
    375369
    376370/* field: RX1PEND - RX1PEND masked interrupt read */
    377 #define TMS570_EMACM_RXINTSTATMASKED_RX1PEND BSP_FLD32(1)
     371#define TMS570_EMACM_RXINTSTATMASKED_RX1PEND BSP_BIT32(1)
    378372
    379373/* field: RX0PEND - RX0PEND masked interrupt read */
    380 #define TMS570_EMACM_RXINTSTATMASKED_RX0PEND BSP_FLD32(0)
    381 
    382 
    383 /*------------------TMS570_EMACMRXINTMASKSET------------------*/
     374#define TMS570_EMACM_RXINTSTATMASKED_RX0PEND BSP_BIT32(0)
     375
     376
     377/*-----------------TMS570_EMACM_RXINTMASKSET-----------------*/
    384378/* field: RX7THRESHMASK - Receive channel 7 threshold mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. */
    385 #define TMS570_EMACM_RXINTMASKSET_RX7THRESHMASK BSP_FLD32(15)
     379#define TMS570_EMACM_RXINTMASKSET_RX7THRESHMASK BSP_BIT32(15)
    386380
    387381/* field: RX6THRESHMASK - Receive channel 6 threshold mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. */
    388 #define TMS570_EMACM_RXINTMASKSET_RX6THRESHMASK BSP_FLD32(14)
     382#define TMS570_EMACM_RXINTMASKSET_RX6THRESHMASK BSP_BIT32(14)
    389383
    390384/* field: RX5THRESHMASK - Receive channel 5 threshold mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. */
    391 #define TMS570_EMACM_RXINTMASKSET_RX5THRESHMASK BSP_FLD32(13)
     385#define TMS570_EMACM_RXINTMASKSET_RX5THRESHMASK BSP_BIT32(13)
    392386
    393387/* field: RX4THRESHMASK - Receive channel 4 threshold mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. */
    394 #define TMS570_EMACM_RXINTMASKSET_RX4THRESHMASK BSP_FLD32(12)
     388#define TMS570_EMACM_RXINTMASKSET_RX4THRESHMASK BSP_BIT32(12)
    395389
    396390/* field: RX3THRESHMASK - Receive channel 3 threshold mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. */
    397 #define TMS570_EMACM_RXINTMASKSET_RX3THRESHMASK BSP_FLD32(11)
     391#define TMS570_EMACM_RXINTMASKSET_RX3THRESHMASK BSP_BIT32(11)
    398392
    399393/* field: RX2THRESHMASK - Receive channel 2 threshold mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. */
    400 #define TMS570_EMACM_RXINTMASKSET_RX2THRESHMASK BSP_FLD32(10)
     394#define TMS570_EMACM_RXINTMASKSET_RX2THRESHMASK BSP_BIT32(10)
    401395
    402396/* field: RX1THRESHMASK - Receive channel 1 threshold mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. */
    403 #define TMS570_EMACM_RXINTMASKSET_RX1THRESHMASK BSP_FLD32(9)
     397#define TMS570_EMACM_RXINTMASKSET_RX1THRESHMASK BSP_BIT32(9)
    404398
    405399/* field: RX0THRESHMASK - Receive channel 0 threshold mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. */
    406 #define TMS570_EMACM_RXINTMASKSET_RX0THRESHMASK BSP_FLD32(8)
     400#define TMS570_EMACM_RXINTMASKSET_RX0THRESHMASK BSP_BIT32(8)
    407401
    408402/* field: RX7MASK - Receive channel 7 mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. */
    409 #define TMS570_EMACM_RXINTMASKSET_RX7MASK BSP_FLD32(7)
     403#define TMS570_EMACM_RXINTMASKSET_RX7MASK BSP_BIT32(7)
    410404
    411405/* field: RX6MASK - Receive channel 6 mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. */
    412 #define TMS570_EMACM_RXINTMASKSET_RX6MASK BSP_FLD32(6)
     406#define TMS570_EMACM_RXINTMASKSET_RX6MASK BSP_BIT32(6)
    413407
    414408/* field: RX5MASK - Receive channel 5 mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. */
    415 #define TMS570_EMACM_RXINTMASKSET_RX5MASK BSP_FLD32(5)
     409#define TMS570_EMACM_RXINTMASKSET_RX5MASK BSP_BIT32(5)
    416410
    417411/* field: RX4MASK - Receive channel 4 mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. */
    418 #define TMS570_EMACM_RXINTMASKSET_RX4MASK BSP_FLD32(4)
     412#define TMS570_EMACM_RXINTMASKSET_RX4MASK BSP_BIT32(4)
    419413
    420414/* field: RX3MASK - Receive channel 3 mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. */
    421 #define TMS570_EMACM_RXINTMASKSET_RX3MASK BSP_FLD32(3)
     415#define TMS570_EMACM_RXINTMASKSET_RX3MASK BSP_BIT32(3)
    422416
    423417/* field: RX2MASK - Receive channel 2 mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. */
    424 #define TMS570_EMACM_RXINTMASKSET_RX2MASK BSP_FLD32(2)
     418#define TMS570_EMACM_RXINTMASKSET_RX2MASK BSP_BIT32(2)
    425419
    426420/* field: RX1MASK - Receive channel 1 mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. */
    427 #define TMS570_EMACM_RXINTMASKSET_RX1MASK BSP_FLD32(1)
     421#define TMS570_EMACM_RXINTMASKSET_RX1MASK BSP_BIT32(1)
    428422
    429423/* field: RX0MASK - Receive channel 0 mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. */
    430 #define TMS570_EMACM_RXINTMASKSET_RX0MASK BSP_FLD32(0)
    431 
    432 
    433 /*-----------------TMS570_EMACMRXINTMASKCLEAR-----------------*/
     424#define TMS570_EMACM_RXINTMASKSET_RX0MASK BSP_BIT32(0)
     425
     426
     427/*----------------TMS570_EMACM_RXINTMASKCLEAR----------------*/
    434428/* field: RX7THRESHMASK - Receive channel 7 threshold mask clear bit. */
    435 #define TMS570_EMACM_RXINTMASKCLEAR_RX7THRESHMASK BSP_FLD32(15)
     429#define TMS570_EMACM_RXINTMASKCLEAR_RX7THRESHMASK BSP_BIT32(15)
    436430
    437431/* field: RX6THRESHMASK - Receive channel 6 threshold mask clear bit. */
    438 #define TMS570_EMACM_RXINTMASKCLEAR_RX6THRESHMASK BSP_FLD32(14)
     432#define TMS570_EMACM_RXINTMASKCLEAR_RX6THRESHMASK BSP_BIT32(14)
    439433
    440434/* field: RX5THRESHMASK - Receive channel 5 threshold mask clear bit. */
    441 #define TMS570_EMACM_RXINTMASKCLEAR_RX5THRESHMASK BSP_FLD32(13)
     435#define TMS570_EMACM_RXINTMASKCLEAR_RX5THRESHMASK BSP_BIT32(13)
    442436
    443437/* field: RX4THRESHMASK - Receive channel 4 threshold mask clear bit. */
    444 #define TMS570_EMACM_RXINTMASKCLEAR_RX4THRESHMASK BSP_FLD32(12)
     438#define TMS570_EMACM_RXINTMASKCLEAR_RX4THRESHMASK BSP_BIT32(12)
    445439
    446440/* field: RX3THRESHMASK - Receive channel 3 threshold mask clear bit. */
    447 #define TMS570_EMACM_RXINTMASKCLEAR_RX3THRESHMASK BSP_FLD32(11)
     441#define TMS570_EMACM_RXINTMASKCLEAR_RX3THRESHMASK BSP_BIT32(11)
    448442
    449443/* field: RX2THRESHMASK - Receive channel 2 threshold mask clear bit. */
    450 #define TMS570_EMACM_RXINTMASKCLEAR_RX2THRESHMASK BSP_FLD32(10)
     444#define TMS570_EMACM_RXINTMASKCLEAR_RX2THRESHMASK BSP_BIT32(10)
    451445
    452446/* field: RX1THRESHMASK - Receive channel 1 threshold mask clear bit. */
    453 #define TMS570_EMACM_RXINTMASKCLEAR_RX1THRESHMASK BSP_FLD32(9)
     447#define TMS570_EMACM_RXINTMASKCLEAR_RX1THRESHMASK BSP_BIT32(9)
    454448
    455449/* field: RX0THRESHMASK - Receive channel 0 threshold mask clear bit. */
    456 #define TMS570_EMACM_RXINTMASKCLEAR_RX0THRESHMASK BSP_FLD32(8)
     450#define TMS570_EMACM_RXINTMASKCLEAR_RX0THRESHMASK BSP_BIT32(8)
    457451
    458452/* field: RX7MASK - Receive channel 7 mask clear bit. Write 1 to disable interrupt; a write of 0 has no effect. */
    459 #define TMS570_EMACM_RXINTMASKCLEAR_RX7MASK BSP_FLD32(7)
     453#define TMS570_EMACM_RXINTMASKCLEAR_RX7MASK BSP_BIT32(7)
    460454
    461455/* field: RX6MASK - Receive channel 6 mask clear bit. Write 1 to disable interrupt; a write of 0 has no effect. */
    462 #define TMS570_EMACM_RXINTMASKCLEAR_RX6MASK BSP_FLD32(6)
     456#define TMS570_EMACM_RXINTMASKCLEAR_RX6MASK BSP_BIT32(6)
    463457
    464458/* field: RX5MASK - Receive channel 5 mask clear bit. Write 1 to disable interrupt; a write of 0 has no effect. */
    465 #define TMS570_EMACM_RXINTMASKCLEAR_RX5MASK BSP_FLD32(5)
     459#define TMS570_EMACM_RXINTMASKCLEAR_RX5MASK BSP_BIT32(5)
    466460
    467461/* field: RX4MASK - Receive channel 4 mask clear bit. Write 1 to disable interrupt; a write of 0 has no effect. */
    468 #define TMS570_EMACM_RXINTMASKCLEAR_RX4MASK BSP_FLD32(4)
     462#define TMS570_EMACM_RXINTMASKCLEAR_RX4MASK BSP_BIT32(4)
    469463
    470464/* field: RX3MASK - Receive channel 3 mask clear bit. Write 1 to disable interrupt; a write of 0 has no effect. */
    471 #define TMS570_EMACM_RXINTMASKCLEAR_RX3MASK BSP_FLD32(3)
     465#define TMS570_EMACM_RXINTMASKCLEAR_RX3MASK BSP_BIT32(3)
    472466
    473467/* field: RX2MASK - Receive channel 2 mask clear bit. Write 1 to disable interrupt; a write of 0 has no effect. */
    474 #define TMS570_EMACM_RXINTMASKCLEAR_RX2MASK BSP_FLD32(2)
     468#define TMS570_EMACM_RXINTMASKCLEAR_RX2MASK BSP_BIT32(2)
    475469
    476470/* field: RX1MASK - Receive channel 1 mask clear bit. Write 1 to disable interrupt; a write of 0 has no effect. */
    477 #define TMS570_EMACM_RXINTMASKCLEAR_RX1MASK BSP_FLD32(1)
     471#define TMS570_EMACM_RXINTMASKCLEAR_RX1MASK BSP_BIT32(1)
    478472
    479473/* field: RX0MASK - Receive channel 0 mask clear bit. Write 1 to disable interrupt; a write of 0 has no effect. */
    480 #define TMS570_EMACM_RXINTMASKCLEAR_RX0MASK BSP_FLD32(0)
    481 
    482 
    483 /*-----------------TMS570_EMACMMACINTSTATRAW-----------------*/
     474#define TMS570_EMACM_RXINTMASKCLEAR_RX0MASK BSP_BIT32(0)
     475
     476
     477/*-----------------TMS570_EMACM_MACINTSTATRAW-----------------*/
    484478/* field: HOSTPEND - Host pending interrupt (HOSTPEND); raw interrupt read (before mask). */
    485 #define TMS570_EMACM_MACINTSTATRAW_HOSTPEND BSP_FLD32(1)
     479#define TMS570_EMACM_MACINTSTATRAW_HOSTPEND BSP_BIT32(1)
    486480
    487481/* field: STATPEND - Statistics pending interrupt (STATPEND); raw interrupt read (before mask). */
    488 #define TMS570_EMACM_MACINTSTATRAW_STATPEND BSP_FLD32(0)
    489 
    490 
    491 /*----------------TMS570_EMACMMACINTSTATMASKED----------------*/
     482#define TMS570_EMACM_MACINTSTATRAW_STATPEND BSP_BIT32(0)
     483
     484
     485/*---------------TMS570_EMACM_MACINTSTATMASKED---------------*/
    492486/* field: HOSTPEND - Host pending interrupt (HOSTPEND); masked interrupt read. */
    493 #define TMS570_EMACM_MACINTSTATMASKED_HOSTPEND BSP_FLD32(1)
     487#define TMS570_EMACM_MACINTSTATMASKED_HOSTPEND BSP_BIT32(1)
    494488
    495489/* field: STATPEND - Statistics pending interrupt (STATPEND); masked interrupt read. */
    496 #define TMS570_EMACM_MACINTSTATMASKED_STATPEND BSP_FLD32(0)
    497 
    498 
    499 /*-----------------TMS570_EMACMMACINTMASKSET-----------------*/
     490#define TMS570_EMACM_MACINTSTATMASKED_STATPEND BSP_BIT32(0)
     491
     492
     493/*-----------------TMS570_EMACM_MACINTMASKSET-----------------*/
    500494/* field: HOSTMASK - Host error interrupt mask set bit. Write 1 to enable interrupt, a write of 0 has no effect. */
    501 #define TMS570_EMACM_MACINTMASKSET_HOSTMASK BSP_FLD32(1)
     495#define TMS570_EMACM_MACINTMASKSET_HOSTMASK BSP_BIT32(1)
    502496
    503497/* field: STATMASK - Statistics interrupt mask set bit. Write 1 to enable interrupt, a write of 0 has no effect. */
    504 #define TMS570_EMACM_MACINTMASKSET_STATMASK BSP_FLD32(0)
    505 
    506 
    507 /*----------------TMS570_EMACMMACINTMASKCLEAR----------------*/
     498#define TMS570_EMACM_MACINTMASKSET_STATMASK BSP_BIT32(0)
     499
     500
     501/*----------------TMS570_EMACM_MACINTMASKCLEAR----------------*/
    508502/* field: HOSTMASK - Host error interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect. */
    509 #define TMS570_EMACM_MACINTMASKCLEAR_HOSTMASK BSP_FLD32(1)
     503#define TMS570_EMACM_MACINTMASKCLEAR_HOSTMASK BSP_BIT32(1)
    510504
    511505/* field: STATMASK - Statistics interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect. */
    512 #define TMS570_EMACM_MACINTMASKCLEAR_STATMASK BSP_FLD32(0)
    513 
    514 
    515 /*------------------TMS570_EMACMRXMBPENABLE------------------*/
     506#define TMS570_EMACM_MACINTMASKCLEAR_STATMASK BSP_BIT32(0)
     507
     508
     509/*------------------TMS570_EMACM_RXMBPENABLE------------------*/
    516510/* field: RXPASSCRC - Pass receive CRC enable bit */
    517 #define TMS570_EMACM_RXMBPENABLE_RXPASSCRC BSP_FLD32(30)
     511#define TMS570_EMACM_RXMBPENABLE_RXPASSCRC BSP_BIT32(30)
    518512
    519513/* field: RXQOSEN - Receive quality of service enable bit */
    520 #define TMS570_EMACM_RXMBPENABLE_RXQOSEN BSP_FLD32(29)
     514#define TMS570_EMACM_RXMBPENABLE_RXQOSEN BSP_BIT32(29)
    521515
    522516/* field: RXNOCHAIN - Receive no buffer chaining bit */
    523 #define TMS570_EMACM_RXMBPENABLE_RXNOCHAIN BSP_FLD32(28)
     517#define TMS570_EMACM_RXMBPENABLE_RXNOCHAIN BSP_BIT32(28)
    524518
    525519/* field: RXCMFEN - Receive copy MAC control frames enable bit. */
    526 #define TMS570_EMACM_RXMBPENABLE_RXCMFEN BSP_FLD32(24)
     520#define TMS570_EMACM_RXMBPENABLE_RXCMFEN BSP_BIT32(24)
    527521
    528522/* field: RXCSFEN - Receive copy short frames enable bit. */
    529 #define TMS570_EMACM_RXMBPENABLE_RXCSFEN BSP_FLD32(23)
     523#define TMS570_EMACM_RXMBPENABLE_RXCSFEN BSP_BIT32(23)
    530524
    531525/* field: RXCEFEN - Receive copy error frames enable bit. */
    532 #define TMS570_EMACM_RXMBPENABLE_RXCEFEN BSP_FLD32(22)
     526#define TMS570_EMACM_RXMBPENABLE_RXCEFEN BSP_BIT32(22)
    533527
    534528/* field: RXCAFEN - Receive copy all frames enable bit. */
    535 #define TMS570_EMACM_RXMBPENABLE_RXCAFEN BSP_FLD32(21)
     529#define TMS570_EMACM_RXMBPENABLE_RXCAFEN BSP_BIT32(21)
    536530
    537531/* field: RXPROMCH - Receive promiscuous channel select */
     
    541535
    542536/* field: RXBROADEN - Receive broadcast enable. */
    543 #define TMS570_EMACM_RXMBPENABLE_RXBROADEN BSP_FLD32(13)
     537#define TMS570_EMACM_RXMBPENABLE_RXBROADEN BSP_BIT32(13)
    544538
    545539/* field: RXBROADCH - Receive broadcast channel select */
     
    549543
    550544/* field: RXMULTEN - RX multicast enable. */
    551 #define TMS570_EMACM_RXMBPENABLE_RXMULTEN BSP_FLD32(5)
    552 
    553 
    554 /*------------------TMS570_EMACMRXUNICASTSET------------------*/
     545#define TMS570_EMACM_RXMBPENABLE_RXMULTEN BSP_BIT32(5)
     546
     547
     548/*-----------------TMS570_EMACM_RXUNICASTSET-----------------*/
    555549/* field: RXCH7EN - Receive channel 7 unicast enable set bit. Write 1 to set the enable, a write of 0 has no effect. */
    556 #define TMS570_EMACM_RXUNICASTSET_RXCH7EN BSP_FLD32(7)
     550#define TMS570_EMACM_RXUNICASTSET_RXCH7EN BSP_BIT32(7)
    557551
    558552/* field: RXCH6EN - Receive channel 6 unicast enable set bit. Write 1 to set the enable, a write of 0 has no effect. */
    559 #define TMS570_EMACM_RXUNICASTSET_RXCH6EN BSP_FLD32(6)
     553#define TMS570_EMACM_RXUNICASTSET_RXCH6EN BSP_BIT32(6)
    560554
    561555/* field: RXCH5EN - Receive channel 5 unicast enable set bit. Write 1 to set the enable, a write of 0 has no effect. */
    562 #define TMS570_EMACM_RXUNICASTSET_RXCH5EN BSP_FLD32(5)
     556#define TMS570_EMACM_RXUNICASTSET_RXCH5EN BSP_BIT32(5)
    563557
    564558/* field: RXCH4EN - Receive channel 4 unicast enable set bit. Write 1 to set the enable, a write of 0 has no effect. */
    565 #define TMS570_EMACM_RXUNICASTSET_RXCH4EN BSP_FLD32(4)
     559#define TMS570_EMACM_RXUNICASTSET_RXCH4EN BSP_BIT32(4)
    566560
    567561/* field: RXCH3EN - Receive channel 3 unicast enable set bit. Write 1 to set the enable, a write of 0 has no effect. */
    568 #define TMS570_EMACM_RXUNICASTSET_RXCH3EN BSP_FLD32(3)
     562#define TMS570_EMACM_RXUNICASTSET_RXCH3EN BSP_BIT32(3)
    569563
    570564/* field: RXCH2EN - Receive channel 2 unicast enable set bit. Write 1 to set the enable, a write of 0 has no effect. */
    571 #define TMS570_EMACM_RXUNICASTSET_RXCH2EN BSP_FLD32(2)
     565#define TMS570_EMACM_RXUNICASTSET_RXCH2EN BSP_BIT32(2)
    572566
    573567/* field: RXCH1EN - Receive channel 1 unicast enable set bit. Write 1 to set the enable, a write of 0 has no effect. */
    574 #define TMS570_EMACM_RXUNICASTSET_RXCH1EN BSP_FLD32(1)
     568#define TMS570_EMACM_RXUNICASTSET_RXCH1EN BSP_BIT32(1)
    575569
    576570/* field: RXCH0EN - Receive channel 0 unicast enable set bit. Write 1 to set the enable, a write of 0 has no effect. */
    577 #define TMS570_EMACM_RXUNICASTSET_RXCH0EN BSP_FLD32(0)
    578 
    579 
    580 /*-----------------TMS570_EMACMRXUNICASTCLEAR-----------------*/
     571#define TMS570_EMACM_RXUNICASTSET_RXCH0EN BSP_BIT32(0)
     572
     573
     574/*----------------TMS570_EMACM_RXUNICASTCLEAR----------------*/
    581575/* field: RXCH7EN - Receive channel 7 unicast enable clear bit. Write 1 to clear the enable, a write of 0 has no effect. */
    582 #define TMS570_EMACM_RXUNICASTCLEAR_RXCH7EN BSP_FLD32(7)
     576#define TMS570_EMACM_RXUNICASTCLEAR_RXCH7EN BSP_BIT32(7)
    583577
    584578/* field: RXCH6EN - Receive channel 6 unicast enable clear bit. Write 1 to clear the enable, a write of 0 has no effect. */
    585 #define TMS570_EMACM_RXUNICASTCLEAR_RXCH6EN BSP_FLD32(6)
     579#define TMS570_EMACM_RXUNICASTCLEAR_RXCH6EN BSP_BIT32(6)
    586580
    587581/* field: RXCH5EN - Receive channel 5 unicast enable clear bit. Write 1 to clear the enable, a write of 0 has no effect. */
    588 #define TMS570_EMACM_RXUNICASTCLEAR_RXCH5EN BSP_FLD32(5)
     582#define TMS570_EMACM_RXUNICASTCLEAR_RXCH5EN BSP_BIT32(5)
    589583
    590584/* field: RXCH4EN - Receive channel 4 unicast enable clear bit. Write 1 to clear the enable, a write of 0 has no effect. */
    591 #define TMS570_EMACM_RXUNICASTCLEAR_RXCH4EN BSP_FLD32(4)
     585#define TMS570_EMACM_RXUNICASTCLEAR_RXCH4EN BSP_BIT32(4)
    592586
    593587/* field: RXCH3EN - Receive channel 3 unicast enable clear bit. Write 1 to clear the enable, a write of 0 has no effect. */
    594 #define TMS570_EMACM_RXUNICASTCLEAR_RXCH3EN BSP_FLD32(3)
     588#define TMS570_EMACM_RXUNICASTCLEAR_RXCH3EN BSP_BIT32(3)
    595589
    596590/* field: RXCH2EN - Receive channel 2 unicast enable clear bit. Write 1 to clear the enable, a write of 0 has no effect. */
    597 #define TMS570_EMACM_RXUNICASTCLEAR_RXCH2EN BSP_FLD32(2)
     591#define TMS570_EMACM_RXUNICASTCLEAR_RXCH2EN BSP_BIT32(2)
    598592
    599593/* field: RXCH1EN - Receive channel 1 unicast enable clear bit. Write 1 to clear the enable, a write of 0 has no effect. */
    600 #define TMS570_EMACM_RXUNICASTCLEAR_RXCH1EN BSP_FLD32(1)
     594#define TMS570_EMACM_RXUNICASTCLEAR_RXCH1EN BSP_BIT32(1)
    601595
    602596/* field: RXCH0EN - Receive channel 0 unicast enable clear bit. Write 1 to clear the enable, a write of 0 has no effect. */
    603 #define TMS570_EMACM_RXUNICASTCLEAR_RXCH0EN BSP_FLD32(0)
    604 
    605 
    606 /*--------------------TMS570_EMACMRXMAXLEN--------------------*/
     597#define TMS570_EMACM_RXUNICASTCLEAR_RXCH0EN BSP_BIT32(0)
     598
     599
     600/*-------------------TMS570_EMACM_RXMAXLEN-------------------*/
    607601/* field: RXMAXLEN - Receive maximum frame length. These bits determine the maximum length of a received frame. */
    608602#define TMS570_EMACM_RXMAXLEN_RXMAXLEN(val) BSP_FLD32(val,0, 15)
     
    611605
    612606
    613 /*-----------------TMS570_EMACMRXBUFFEROFFSET-----------------*/
     607/*----------------TMS570_EMACM_RXBUFFEROFFSET----------------*/
    614608/* field: RXBUFFEROFFSET - Receive buffer offset value. */
    615609#define TMS570_EMACM_RXBUFFEROFFSET_RXBUFFEROFFSET(val) BSP_FLD32(val,0, 15)
     
    618612
    619613
    620 /*---------------TMS570_EMACMRXFILTERLOWTHRESH---------------*/
     614/*---------------TMS570_EMACM_RXFILTERLOWTHRESH---------------*/
    621615/* field: RXFILTERTHRESH - Receive filter low threshold. */
    622616#define TMS570_EMACM_RXFILTERLOWTHRESH_RXFILTERTHRESH(val) BSP_FLD32(val,0, 7)
     
    625619
    626620
    627 /*------------------TMS570_EMACMRXFLOWTHRESH------------------*/
     621/*-----------------TMS570_EMACM_RXFLOWTHRESH-----------------*/
    628622/* field: RXnFLOWTHRESH - Receive flow threshold. */
    629623#define TMS570_EMACM_RXFLOWTHRESH_RXnFLOWTHRESH(val) BSP_FLD32(val,0, 7)
     
    632626
    633627
    634 /*------------------TMS570_EMACMRXFREEBUFFER------------------*/
     628/*-----------------TMS570_EMACM_RXFREEBUFFER-----------------*/
    635629/* field: RXnFREEBUF - Receive free buffer count. These bits contain the count of free buffers available. */
    636630#define TMS570_EMACM_RXFREEBUFFER_RXnFREEBUF(val) BSP_FLD32(val,0, 15)
     
    639633
    640634
    641 /*-------------------TMS570_EMACMMACCONTROL-------------------*/
     635/*------------------TMS570_EMACM_MACCONTROL------------------*/
    642636/* field: RMIISPEED - RMII interface transmit and receive speed select. */
    643 #define TMS570_EMACM_MACCONTROL_RMIISPEED BSP_FLD32(15)
     637#define TMS570_EMACM_MACCONTROL_RMIISPEED BSP_BIT32(15)
    644638
    645639/* field: RXOFFLENBLOCK - Receive offset / length word write block. */
    646 #define TMS570_EMACM_MACCONTROL_RXOFFLENBLOCK BSP_FLD32(14)
     640#define TMS570_EMACM_MACCONTROL_RXOFFLENBLOCK BSP_BIT32(14)
    647641
    648642/* field: RXOWNERSHIP - Receive ownership write bit value. */
    649 #define TMS570_EMACM_MACCONTROL_RXOWNERSHIP BSP_FLD32(13)
     643#define TMS570_EMACM_MACCONTROL_RXOWNERSHIP BSP_BIT32(13)
    650644
    651645/* field: CMDIDLE - Command Idle bit */
    652 #define TMS570_EMACM_MACCONTROL_CMDIDLE BSP_FLD32(11)
     646#define TMS570_EMACM_MACCONTROL_CMDIDLE BSP_BIT32(11)
    653647
    654648/* field: TXSHORTGAPEN - Transmit Short Gap Enable */
    655 #define TMS570_EMACM_MACCONTROL_TXSHORTGAPEN BSP_FLD32(10)
     649#define TMS570_EMACM_MACCONTROL_TXSHORTGAPEN BSP_BIT32(10)
    656650
    657651/* field: TXPTYPE - Transmit queue priority type */
    658 #define TMS570_EMACM_MACCONTROL_TXPTYPE BSP_FLD32(9)
     652#define TMS570_EMACM_MACCONTROL_TXPTYPE BSP_BIT32(9)
    659653
    660654/* field: TXPACE - Transmit pacing enable bit */
    661 #define TMS570_EMACM_MACCONTROL_TXPACE BSP_FLD32(6)
     655#define TMS570_EMACM_MACCONTROL_TXPACE BSP_BIT32(6)
    662656
    663657/* field: GMIIEN - GMII enable bit */
    664 #define TMS570_EMACM_MACCONTROL_GMIIEN BSP_FLD32(5)
     658#define TMS570_EMACM_MACCONTROL_GMIIEN BSP_BIT32(5)
    665659
    666660/* field: TXFLOWEN - Transmit flow control enable bit. */
    667 #define TMS570_EMACM_MACCONTROL_TXFLOWEN BSP_FLD32(4)
     661#define TMS570_EMACM_MACCONTROL_TXFLOWEN BSP_BIT32(4)
    668662
    669663/* field: RXBUFFERFLOWEN - Receive buffer flow control enable bit */
    670 #define TMS570_EMACM_MACCONTROL_RXBUFFERFLOWEN BSP_FLD32(3)
     664#define TMS570_EMACM_MACCONTROL_RXBUFFERFLOWEN BSP_BIT32(3)
    671665
    672666/* field: LOOPBACK - Loopback mode. The loopback mode forces internal full-duplex mode regardless of the FULLDUPLEX bit. */
    673 #define TMS570_EMACM_MACCONTROL_LOOPBACK BSP_FLD32(1)
     667#define TMS570_EMACM_MACCONTROL_LOOPBACK BSP_BIT32(1)
    674668
    675669/* field: FULLDUPLEX - Full duplex mode. */
    676 #define TMS570_EMACM_MACCONTROL_FULLDUPLEX BSP_FLD32(0)
    677 
    678 
    679 /*-------------------TMS570_EMACMMACSTATUS-------------------*/
     670#define TMS570_EMACM_MACCONTROL_FULLDUPLEX BSP_BIT32(0)
     671
     672
     673/*-------------------TMS570_EMACM_MACSTATUS-------------------*/
    680674/* field: IDLE - EMAC idle bit. This bit is cleared to 0 at reset; one clock after reset, it goes to 1. */
    681 #define TMS570_EMACM_MACSTATUS_IDLE BSP_FLD32(31)
     675#define TMS570_EMACM_MACSTATUS_IDLE BSP_BIT32(31)
    682676
    683677/* field: TXERRCODE - Transmit host error code. These bits indicate that EMAC detected transmit DMA related host errors. */
     
    702696
    703697/* field: RXQOSACT - Receive Quality of Service (QOS) active bit. */
    704 #define TMS570_EMACM_MACSTATUS_RXQOSACT BSP_FLD32(2)
     698#define TMS570_EMACM_MACSTATUS_RXQOSACT BSP_BIT32(2)
    705699
    706700/* field: RXFLOWACT - Receive flow control active bit. */
    707 #define TMS570_EMACM_MACSTATUS_RXFLOWACT BSP_FLD32(1)
     701#define TMS570_EMACM_MACSTATUS_RXFLOWACT BSP_BIT32(1)
    708702
    709703/* field: TXFLOWACT - Transmit flow control active bit. */
    710 #define TMS570_EMACM_MACSTATUS_TXFLOWACT BSP_FLD32(0)
    711 
    712 
    713 /*-------------------TMS570_EMACMEMCONTROL-------------------*/
     704#define TMS570_EMACM_MACSTATUS_TXFLOWACT BSP_BIT32(0)
     705
     706
     707/*-------------------TMS570_EMACM_EMCONTROL-------------------*/
    714708/* field: SOFT - Emulation soft bit. */
    715 #define TMS570_EMACM_EMCONTROL_SOFT BSP_FLD32(1)
     709#define TMS570_EMACM_EMCONTROL_SOFT BSP_BIT32(1)
    716710
    717711/* field: FREE - Emulation free bit. */
    718 #define TMS570_EMACM_EMCONTROL_FREE BSP_FLD32(0)
    719 
    720 
    721 /*------------------TMS570_EMACMFIFOCONTROL------------------*/
     712#define TMS570_EMACM_EMCONTROL_FREE BSP_BIT32(0)
     713
     714
     715/*------------------TMS570_EMACM_FIFOCONTROL------------------*/
    722716/* field: TXCELLTHRESH - Transmit FIFO cell threshold. */
    723717#define TMS570_EMACM_FIFOCONTROL_TXCELLTHRESH(val) BSP_FLD32(val,0, 1)
     
    726720
    727721
    728 /*-------------------TMS570_EMACMMACCONFIG-------------------*/
     722/*-------------------TMS570_EMACM_MACCONFIG-------------------*/
    729723/* field: TXCELLDEPTH - Transmit cell depth. These bits indicate the number of cells in the transmit FIFO. */
    730724#define TMS570_EMACM_MACCONFIG_TXCELLDEPTH(val) BSP_FLD32(val,24, 31)
     
    748742
    749743
    750 /*-------------------TMS570_EMACMSOFTRESET-------------------*/
     744/*-------------------TMS570_EMACM_SOFTRESET-------------------*/
    751745/* field: SOFTRESET - Software reset. Writing a 1 to this bit causes the EMAC logic to be reset. */
    752 #define TMS570_EMACM_SOFTRESET_SOFTRESET BSP_FLD32(0)
    753 
    754 
    755 /*------------------TMS570_EMACMMACSRCADDRLO------------------*/
     746#define TMS570_EMACM_SOFTRESET_SOFTRESET BSP_BIT32(0)
     747
     748
     749/*-----------------TMS570_EMACM_MACSRCADDRLO-----------------*/
    756750/* field: MACSRCADDR0 - MAC source address lower 8-0 bits (byte 0) */
    757751#define TMS570_EMACM_MACSRCADDRLO_MACSRCADDR0(val) BSP_FLD32(val,8, 15)
     
    765759
    766760
    767 /*------------------TMS570_EMACMMACSRCADDRHI------------------*/
     761/*-----------------TMS570_EMACM_MACSRCADDRHI-----------------*/
    768762/* field: MACSRCADDR2 - MAC source address bits 23-16 (byte 2) */
    769763#define TMS570_EMACM_MACSRCADDRHI_MACSRCADDR2(val) BSP_FLD32(val,24, 31)
     
    787781
    788782
    789 /*--------------------TMS570_EMACMMACHASH1--------------------*/
     783/*-------------------TMS570_EMACM_MACHASH1-------------------*/
    790784/* field: MACHASH1 - Least-significant 32 bits of the hash table corresponding to hash values 0 to 31. */
    791 #define TMS570_EMACM_MACHASH1_MACHASH1(val) BSP_FLD32(val,0, 31)
    792 #define TMS570_EMACM_MACHASH1_MACHASH1_GET(reg) BSP_FLD32GET(reg,0, 31)
    793 #define TMS570_EMACM_MACHASH1_MACHASH1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
    794 
    795 
    796 /*--------------------TMS570_EMACMMACHASH2--------------------*/
     785/* Whole 32 bits */
     786
     787/*-------------------TMS570_EMACM_MACHASH2-------------------*/
    797788/* field: MACHASH2 - Most-significant 32 bits of the hash table corresponding to hash values 32 to 63. */
    798 #define TMS570_EMACM_MACHASH2_MACHASH2(val) BSP_FLD32(val,0, 31)
    799 #define TMS570_EMACM_MACHASH2_MACHASH2_GET(reg) BSP_FLD32GET(reg,0, 31)
    800 #define TMS570_EMACM_MACHASH2_MACHASH2_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
    801 
    802 
    803 /*--------------------TMS570_EMACMBOFFTEST--------------------*/
     789/* Whole 32 bits */
     790
     791/*-------------------TMS570_EMACM_BOFFTEST-------------------*/
    804792/* field: RNDNUM - Backoff random number generator. */
    805793#define TMS570_EMACM_BOFFTEST_RNDNUM(val) BSP_FLD32(val,16, 25)
     
    818806
    819807
    820 /*-------------------TMS570_EMACMTPACETEST-------------------*/
     808/*-------------------TMS570_EMACM_TPACETEST-------------------*/
    821809/* field: PACEVAL - Pacing register current value. A nonzero value in this field indicates that transmit pacing is active. */
    822810#define TMS570_EMACM_TPACETEST_PACEVAL(val) BSP_FLD32(val,0, 4)
     
    825813
    826814
    827 /*--------------------TMS570_EMACMRXPAUSE--------------------*/
     815/*--------------------TMS570_EMACM_RXPAUSE--------------------*/
    828816/* field: PAUSETIMER - Receive pause timer value. */
    829817#define TMS570_EMACM_RXPAUSE_PAUSETIMER(val) BSP_FLD32(val,0, 15)
     
    832820
    833821
    834 /*--------------------TMS570_EMACMTXPAUSE--------------------*/
     822/*--------------------TMS570_EMACM_TXPAUSE--------------------*/
    835823/* field: PAUSETIMER - Transmit pause timer value. */
    836824#define TMS570_EMACM_TXPAUSE_PAUSETIMER(val) BSP_FLD32(val,0, 15)
     
    839827
    840828
    841 /*-------------------TMS570_EMACMMACADDRLO-------------------*/
     829/*-------------------TMS570_EMACM_MACADDRLO-------------------*/
    842830/* field: VALID - Address valid bit. */
    843 #define TMS570_EMACM_MACADDRLO_VALID BSP_FLD32(20)
     831#define TMS570_EMACM_MACADDRLO_VALID BSP_BIT32(20)
    844832
    845833/* field: MATCHFILT - Match or filter bit */
    846 #define TMS570_EMACM_MACADDRLO_MATCHFILT BSP_FLD32(19)
     834#define TMS570_EMACM_MACADDRLO_MATCHFILT BSP_BIT32(19)
    847835
    848836/* field: CHANNEL - Channel select. Determines which receive channel a valid address match will be transferred to. */
     
    862850
    863851
    864 /*-------------------TMS570_EMACMMACADDRHI-------------------*/
     852/*-------------------TMS570_EMACM_MACADDRHI-------------------*/
    865853/* field: MACADDR2 - MAC source address bits 23-16 (byte 2) */
    866854#define TMS570_EMACM_MACADDRHI_MACADDR2(val) BSP_FLD32(val,24, 31)
     
    884872
    885873
    886 /*--------------------TMS570_EMACMMACINDEX--------------------*/
     874/*-------------------TMS570_EMACM_MACINDEX-------------------*/
    887875/* field: MACINDEX - MAC address index. All eight addresses share the upper 40 bits. */
    888876#define TMS570_EMACM_MACINDEX_MACINDEX(val) BSP_FLD32(val,0, 2)
     
    891879
    892880
    893 /*---------------------TMS570_EMACMTXHDP---------------------*/
     881/*---------------------TMS570_EMACM_TXHDP---------------------*/
    894882/* field: TXnHDP - Transmit channel n DMA Head Descriptor pointer. */
    895 #define TMS570_EMACM_TXHDP_TXnHDP(val) BSP_FLD32(val,0, 31)
    896 #define TMS570_EMACM_TXHDP_TXnHDP_GET(reg) BSP_FLD32GET(reg,0, 31)
    897 #define TMS570_EMACM_TXHDP_TXnHDP_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
    898 
    899 
    900 /*---------------------TMS570_EMACMRXHDP---------------------*/
     883/* Whole 32 bits */
     884
     885/*---------------------TMS570_EMACM_RXHDP---------------------*/
    901886/* field: RXnHDP - Receive channel n DMA Head Descriptor pointer. */
    902 #define TMS570_EMACM_RXHDP_RXnHDP(val) BSP_FLD32(val,0, 31)
    903 #define TMS570_EMACM_RXHDP_RXnHDP_GET(reg) BSP_FLD32GET(reg,0, 31)
    904 #define TMS570_EMACM_RXHDP_RXnHDP_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
    905 
    906 
    907 /*----------------------TMS570_EMACMTXCP----------------------*/
     887/* Whole 32 bits */
     888
     889/*---------------------TMS570_EMACM_TXCP---------------------*/
    908890/* field: TXnCP - Transmit channel n completion pointer register is written by the host with the buffer descriptor */
    909 #define TMS570_EMACM_TXCP_TXnCP(val) BSP_FLD32(val,0, 31)
    910 #define TMS570_EMACM_TXCP_TXnCP_GET(reg) BSP_FLD32GET(reg,0, 31)
    911 #define TMS570_EMACM_TXCP_TXnCP_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
    912 
    913 
    914 /*----------------------TMS570_EMACMRXCP----------------------*/
     891/* Whole 32 bits */
     892
     893/*---------------------TMS570_EMACM_RXCP---------------------*/
    915894/* field: RXnCP - Receive channel n completion pointer register is written by the host with the buffer descriptor */
    916 #define TMS570_EMACM_RXCP_RXnCP(val) BSP_FLD32(val,0, 31)
    917 #define TMS570_EMACM_RXCP_RXnCP_GET(reg) BSP_FLD32GET(reg,0, 31)
    918 #define TMS570_EMACM_RXCP_RXnCP_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
    919 
    920 
    921 
    922 #endif /* LIBBSP_ARM_tms570_EMACM */
     895/* Whole 32 bits */
     896
     897
     898#endif /* LIBBSP_ARM_TMS570_EMACM */
  • c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_emif.h

    r3f923fd2 r9a84f983  
    3737 * either expressed or implied, of the FreeBSD Project.
    3838*/
    39 #ifndef LIBBSP_ARM_tms570_EMIF
    40 #define LIBBSP_ARM_tms570_EMIF
     39#ifndef LIBBSP_ARM_TMS570_EMIF
     40#define LIBBSP_ARM_TMS570_EMIF
    4141
    4242#include <bsp/utility.h>
     
    6363
    6464
    65 /*----------------------TMS570_EMIFMIDR----------------------*/
     65/*----------------------TMS570_EMIF_MIDR----------------------*/
    6666/* field: REV - Module ID of EMIF. See the device-specific data manual. */
    67 #define TMS570_EMIF_MIDR_REV(val) BSP_FLD32(val,0, 31)
    68 #define TMS570_EMIF_MIDR_REV_GET(reg) BSP_FLD32GET(reg,0, 31)
    69 #define TMS570_EMIF_MIDR_REV_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
    70 
    71 
    72 /*----------------------TMS570_EMIFAWCC----------------------*/
     67/* Whole 32 bits */
     68
     69/*----------------------TMS570_EMIF_AWCC----------------------*/
    7370/* field: WP1 - EMIF_nWAIT[1] polarity bit. This bit defines the polarity of the EMIF_nWAIT[1] pin. */
    74 #define TMS570_EMIF_AWCC_WP1 BSP_FLD32(29)
     71#define TMS570_EMIF_AWCC_WP1 BSP_BIT32(29)
    7572
    7673/* field: WP0 - EMIF_nWAIT[0] polarity bit. This bit defines the polarity of the EMIF_nWAIT[0] pin. */
    77 #define TMS570_EMIF_AWCC_WP0 BSP_FLD32(28)
     74#define TMS570_EMIF_AWCC_WP0 BSP_BIT32(28)
    7875
    7976/* field: CS5_WAIT - Chip Select 5 WAIT signal selection. */
     
    103100
    104101
    105 /*----------------------TMS570_EMIFSDCR----------------------*/
     102/*----------------------TMS570_EMIF_SDCR----------------------*/
    106103/* field: SR - Self-Refresh mode bit. */
    107 #define TMS570_EMIF_SDCR_SR BSP_FLD32(31)
     104#define TMS570_EMIF_SDCR_SR BSP_BIT32(31)
    108105
    109106/* field: PD - Power Down bit. This bit controls entering and exiting of the power-down mode. */
    110 #define TMS570_EMIF_SDCR_PD BSP_FLD32(30)
     107#define TMS570_EMIF_SDCR_PD BSP_BIT32(30)
    111108
    112109/* field: PDWR - Perform refreshes during power down. */
    113 #define TMS570_EMIF_SDCR_PDWR BSP_FLD32(29)
     110#define TMS570_EMIF_SDCR_PDWR BSP_BIT32(29)
    114111
    115112/* field: NM - Narrow mode bit. This bit defines whether a 16- or 32-bit-wide SDRAM is connected to the EMIF. */
    116 #define TMS570_EMIF_SDCR_NM BSP_FLD32(14)
     113#define TMS570_EMIF_SDCR_NM BSP_BIT32(14)
    117114
    118115/* field: CL - CAS Latency. */
     
    122119
    123120/* field: BIT11_9LOCK - Bits 11 to 9 lock. CL can only be written if BIT11_9LOCK is simultaneously written with a 1. */
    124 #define TMS570_EMIF_SDCR_BIT11_9LOCK BSP_FLD32(8)
     121#define TMS570_EMIF_SDCR_BIT11_9LOCK BSP_BIT32(8)
    125122
    126123/* field: IBANK - Internal SDRAM Bank size. */
     
    135132
    136133
    137 /*----------------------TMS570_EMIFSDRCR----------------------*/
     134/*---------------------TMS570_EMIF_SDRCR---------------------*/
    138135/* field: RR - Refresh Rate. This field is used to define the SDRAM refresh period in terms of EMIF_CLK cycles. */
    139136#define TMS570_EMIF_SDRCR_RR(val) BSP_FLD32(val,0, 12)
     
    142139
    143140
    144 /*---------------------TMS570_EMIFCE2CFG---------------------*/
     141/*---------------------TMS570_EMIF_CE2CFG---------------------*/
    145142/* field: SS - Select Strobe bit. */
    146 #define TMS570_EMIF_CE2CFG_SS BSP_FLD32(31)
     143#define TMS570_EMIF_CE2CFG_SS BSP_BIT32(31)
    147144
    148145/* field: EW - Extend Wait bit. This bit defines whether extended wait cycles will be enabled. See Section 17.2.6. */
    149 #define TMS570_EMIF_CE2CFG_EW BSP_FLD32(30)
     146#define TMS570_EMIF_CE2CFG_EW BSP_BIT32(30)
    150147
    151148/* field: W_SETUP - Write setup width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */
     
    190187
    191188
    192 /*---------------------TMS570_EMIFCE3CFG---------------------*/
     189/*---------------------TMS570_EMIF_CE3CFG---------------------*/
    193190/* field: SS - Select Strobe bit. */
    194 #define TMS570_EMIF_CE3CFG_SS BSP_FLD32(31)
     191#define TMS570_EMIF_CE3CFG_SS BSP_BIT32(31)
    195192
    196193/* field: EW - Extend Wait bit. This bit defines whether extended wait cycles will be enabled. See Section 17.2.6. */
    197 #define TMS570_EMIF_CE3CFG_EW BSP_FLD32(30)
     194#define TMS570_EMIF_CE3CFG_EW BSP_BIT32(30)
    198195
    199196/* field: W_SETUP - Write setup width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */
     
    238235
    239236
    240 /*---------------------TMS570_EMIFCE4CFG---------------------*/
     237/*---------------------TMS570_EMIF_CE4CFG---------------------*/
    241238/* field: SS - Select Strobe bit. */
    242 #define TMS570_EMIF_CE4CFG_SS BSP_FLD32(31)
     239#define TMS570_EMIF_CE4CFG_SS BSP_BIT32(31)
    243240
    244241/* field: EW - Extend Wait bit. This bit defines whether extended wait cycles will be enabled. See Section 17.2.6. */
    245 #define TMS570_EMIF_CE4CFG_EW BSP_FLD32(30)
     242#define TMS570_EMIF_CE4CFG_EW BSP_BIT32(30)
    246243
    247244/* field: W_SETUP - Write setup width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */
     
    286283
    287284
    288 /*---------------------TMS570_EMIFCE5CFG---------------------*/
     285/*---------------------TMS570_EMIF_CE5CFG---------------------*/
    289286/* field: SS - Select Strobe bit. */
    290 #define TMS570_EMIF_CE5CFG_SS BSP_FLD32(31)
     287#define TMS570_EMIF_CE5CFG_SS BSP_BIT32(31)
    291288
    292289/* field: EW - Extend Wait bit. This bit defines whether extended wait cycles will be enabled. See Section 17.2.6. */
    293 #define TMS570_EMIF_CE5CFG_EW BSP_FLD32(30)
     290#define TMS570_EMIF_CE5CFG_EW BSP_BIT32(30)
    294291
    295292/* field: W_SETUP - Write setup width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */
     
    334331
    335332
    336 /*---------------------TMS570_EMIFSDTIMR---------------------*/
     333/*---------------------TMS570_EMIF_SDTIMR---------------------*/
    337334/* field: T_RFC - Specifies the Trfc value of the SDRAM. */
    338335#define TMS570_EMIF_SDTIMR_T_RFC(val) BSP_FLD32(val,27, 31)
     
    371368
    372369
    373 /*---------------------TMS570_EMIFSDSRETR---------------------*/
     370/*--------------------TMS570_EMIF_SDSRETR--------------------*/
    374371/* field: T_XS - This field specifies the minimum number of ECLKOUT cycles from Self-Refresh exit to any command, */
    375372#define TMS570_EMIF_SDSRETR_T_XS(val) BSP_FLD32(val,0, 4)
     
    378375
    379376
    380 /*---------------------TMS570_EMIFINTRAW---------------------*/
     377/*---------------------TMS570_EMIF_INTRAW---------------------*/
    381378/* field: WR - Wait Rise. */
    382 #define TMS570_EMIF_INTRAW_WR BSP_FLD32(2)
     379#define TMS570_EMIF_INTRAW_WR BSP_BIT32(2)
    383380
    384381/* field: LT - Line Trap. Set to 1 by hardware to indicate illegal memory access type or invalid cache line size. */
    385 #define TMS570_EMIF_INTRAW_LT BSP_FLD32(1)
     382#define TMS570_EMIF_INTRAW_LT BSP_BIT32(1)
    386383
    387384/* field: AT - Asynchronous Timeout. */
    388 #define TMS570_EMIF_INTRAW_AT BSP_FLD32(0)
    389 
    390 
    391 /*---------------------TMS570_EMIFINTMSK---------------------*/
     385#define TMS570_EMIF_INTRAW_AT BSP_BIT32(0)
     386
     387
     388/*---------------------TMS570_EMIF_INTMSK---------------------*/
    392389/* field: WR_MASKED - Wait Rise Masked. */
    393 #define TMS570_EMIF_INTMSK_WR_MASKED BSP_FLD32(2)
     390#define TMS570_EMIF_INTMSK_WR_MASKED BSP_BIT32(2)
    394391
    395392/* field: LT_MASKED - Masked Line Trap. */
    396 #define TMS570_EMIF_INTMSK_LT_MASKED BSP_FLD32(1)
     393#define TMS570_EMIF_INTMSK_LT_MASKED BSP_BIT32(1)
    397394
    398395/* field: AT_MASKED - Asynchronous Timeout Masked. */
    399 #define TMS570_EMIF_INTMSK_AT_MASKED BSP_FLD32(0)
    400 
    401 
    402 /*--------------------TMS570_EMIFINTMSKSET--------------------*/
     396#define TMS570_EMIF_INTMSK_AT_MASKED BSP_BIT32(0)
     397
     398
     399/*-------------------TMS570_EMIF_INTMSKSET-------------------*/
    403400/* field: WR_MASK_SET - Wait Rise Mask Set. This bit determines whether or not the wait rise Interrupt is enabled. */
    404 #define TMS570_EMIF_INTMSKSET_WR_MASK_SET BSP_FLD32(2)
     401#define TMS570_EMIF_INTMSKSET_WR_MASK_SET BSP_BIT32(2)
    405402
    406403/* field: LT_MASK_SET - LT_MASK_SET Mask set for LT_MASKED bit in the EMIF interrupt mask register (INTMSK). */
    407 #define TMS570_EMIF_INTMSKSET_LT_MASK_SET BSP_FLD32(1)
     404#define TMS570_EMIF_INTMSKSET_LT_MASK_SET BSP_BIT32(1)
    408405
    409406/* field: AT_MASK_SET - Asynchronous Timeout Mask Set. */
    410 #define TMS570_EMIF_INTMSKSET_AT_MASK_SET BSP_FLD32(0)
    411 
    412 
    413 /*--------------------TMS570_EMIFINTMSKCLR--------------------*/
     407#define TMS570_EMIF_INTMSKSET_AT_MASK_SET BSP_BIT32(0)
     408
     409
     410/*-------------------TMS570_EMIF_INTMSKCLR-------------------*/
    414411/* field: WR_MASK_CLR - Wait Rise Mask Clear. This bit determines whether or not the wait rise interrupt is enabled. */
    415 #define TMS570_EMIF_INTMSKCLR_WR_MASK_CLR BSP_FLD32(2)
     412#define TMS570_EMIF_INTMSKCLR_WR_MASK_CLR BSP_BIT32(2)
    416413
    417414/* field: LT_MASK_CLR - 1 to this bit clears this bit, clears the LT_MASK_SET bit in the EMIF interrupt mask set register */
    418 #define TMS570_EMIF_INTMSKCLR_LT_MASK_CLR BSP_FLD32(1)
     415#define TMS570_EMIF_INTMSKCLR_LT_MASK_CLR BSP_BIT32(1)
    419416
    420417/* field: AT_MASK_CLR - Asynchronous Timeout Mask Clear. */
    421 #define TMS570_EMIF_INTMSKCLR_AT_MASK_CLR BSP_FLD32(0)
    422 
    423 
    424 /*----------------------TMS570_EMIFPMCR----------------------*/
     418#define TMS570_EMIF_INTMSKCLR_AT_MASK_CLR BSP_BIT32(0)
     419
     420
     421/*----------------------TMS570_EMIF_PMCR----------------------*/
    425422/* field: CS5_PG_DEL - Page access delay for NOR Flash connected on CS5. CS5 is not available on this device. */
    426423#define TMS570_EMIF_PMCR_CS5_PG_DEL(val) BSP_FLD32(val,26, 31)
     
    429426
    430427/* field: CS5_PG_SIZE - Page Size for NOR Flash connected on CS5. CS5 is not available on this device. */
    431 #define TMS570_EMIF_PMCR_CS5_PG_SIZE BSP_FLD32(25)
     428#define TMS570_EMIF_PMCR_CS5_PG_SIZE BSP_BIT32(25)
    432429
    433430/* field: CS5_PG_MD_EN - Page Mode enable for NOR Flash connected on CS5. CS5 is not available on this device. */
    434 #define TMS570_EMIF_PMCR_CS5_PG_MD_EN BSP_FLD32(24)
     431#define TMS570_EMIF_PMCR_CS5_PG_MD_EN BSP_BIT32(24)
    435432
    436433/* field: CS4_PG_DEL - Page access delay for NOR Flash connected on CS4. */
     
    440437
    441438/* field: CS4_PG_SIZE - Page Size for NOR Flash connected on CS4. */
    442 #define TMS570_EMIF_PMCR_CS4_PG_SIZE BSP_FLD32(17)
     439#define TMS570_EMIF_PMCR_CS4_PG_SIZE BSP_BIT32(17)
    443440
    444441/* field: CS4_PG_MD_EN - Page Mode enable for NOR Flash connected on CS4. */
    445 #define TMS570_EMIF_PMCR_CS4_PG_MD_EN BSP_FLD32(16)
     442#define TMS570_EMIF_PMCR_CS4_PG_MD_EN BSP_BIT32(16)
    446443
    447444/* field: CS3_PG_DEL - the page read data to be valid, minus one cycle. This value must not be cleared to 0. */
     
    451448
    452449/* field: CS3_PG_SIZE - Page Size for NOR Flash connected on CS3. */
    453 #define TMS570_EMIF_PMCR_CS3_PG_SIZE BSP_FLD32(9)
     450#define TMS570_EMIF_PMCR_CS3_PG_SIZE BSP_BIT32(9)
    454451
    455452/* field: CS3_PG_MD_EN - Page Mode enable for NOR Flash connected on CS3. */
    456 #define TMS570_EMIF_PMCR_CS3_PG_MD_EN BSP_FLD32(8)
     453#define TMS570_EMIF_PMCR_CS3_PG_MD_EN BSP_BIT32(8)
    457454
    458455/* field: CS2_PG_DEL - Page access delay for NOR Flash connected on CS2. */
     
    462459
    463460/* field: CS2_PG_SIZE - Page Size for NOR Flash connected on CS2. */
    464 #define TMS570_EMIF_PMCR_CS2_PG_SIZE BSP_FLD32(1)
     461#define TMS570_EMIF_PMCR_CS2_PG_SIZE BSP_BIT32(1)
    465462
    466463/* field: CS2_PG_MD_EN - Page Mode enable for NOR Flash connected on CS2. */
    467 #define TMS570_EMIF_PMCR_CS2_PG_MD_EN BSP_FLD32(0)
    468 
    469 
    470 
    471 #endif /* LIBBSP_ARM_tms570_EMIF */
     464#define TMS570_EMIF_PMCR_CS2_PG_MD_EN BSP_BIT32(0)
     465
     466
     467
     468#endif /* LIBBSP_ARM_TMS570_EMIF */
  • c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_esm.h

    r3f923fd2 r9a84f983  
    3737 * either expressed or implied, of the FreeBSD Project.
    3838*/
    39 #ifndef LIBBSP_ARM_tms570_ESM
    40 #define LIBBSP_ARM_tms570_ESM
     39#ifndef LIBBSP_ARM_TMS570_ESM
     40#define LIBBSP_ARM_TMS570_ESM
    4141
    4242#include <bsp/utility.h>
     
    6767
    6868
    69 /*---------------------TMS570_ESMEEPAPR1---------------------*/
     69/*---------------------TMS570_ESM_EEPAPR1---------------------*/
    7070/* field: IEPSET - Enable ERROR Pin Action/Response on Group 1. */
    71 #define TMS570_ESM_EEPAPR1_IEPSET(val) BSP_FLD32(val,0, 31)
    72 #define TMS570_ESM_EEPAPR1_IEPSET_GET(reg) BSP_FLD32GET(reg,0, 31)
    73 #define TMS570_ESM_EEPAPR1_IEPSET_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
     71/* Whole 32 bits */
     72
     73/*---------------------TMS570_ESM_DEPAPR1---------------------*/
     74/* field: IEPCLR - Disable ERROR Pin Action/Response on Group 1. */
     75/* Whole 32 bits */
     76
     77/*----------------------TMS570_ESM_IESR1----------------------*/
     78/* field: INTENSET - Set interrupt Enable */
     79/* Whole 32 bits */
     80
     81/*----------------------TMS570_ESM_IECR1----------------------*/
     82/* field: INTENCLR - Clear Interrupt Enable */
     83/* Whole 32 bits */
     84
     85/*----------------------TMS570_ESM_ILSR1----------------------*/
     86/* field: INTLVLSET - Set Interrupt Priority */
     87/* Whole 32 bits */
     88
     89/*----------------------TMS570_ESM_ILCR1----------------------*/
     90/* field: INTLVLCLR - Clear Interrupt Priority. */
     91/* Whole 32 bits */
     92
     93/*-----------------------TMS570_ESM_SR-----------------------*/
     94/* field: ESF - Error Status Flag. Provides status information on a pending error. */
     95/* Whole 32 bits */
     96
     97/*----------------------TMS570_ESM_EPSR----------------------*/
     98/* field: EPSF - ERROR Pin Status Flag. Provides status information for the ERROR Pin. */
     99#define TMS570_ESM_EPSR_EPSF BSP_BIT32(0)
    74100
    75101
    76 /*---------------------TMS570_ESMDEPAPR1---------------------*/
    77 /* field: IEPCLR - Disable ERROR Pin Action/Response on Group 1. */
    78 #define TMS570_ESM_DEPAPR1_IEPCLR(val) BSP_FLD32(val,0, 31)
    79 #define TMS570_ESM_DEPAPR1_IEPCLR_GET(reg) BSP_FLD32GET(reg,0, 31)
    80 #define TMS570_ESM_DEPAPR1_IEPCLR_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
    81 
    82 
    83 /*----------------------TMS570_ESMIESR1----------------------*/
    84 /* field: INTENSET - Set interrupt Enable */
    85 #define TMS570_ESM_IESR1_INTENSET(val) BSP_FLD32(val,0, 31)
    86 #define TMS570_ESM_IESR1_INTENSET_GET(reg) BSP_FLD32GET(reg,0, 31)
    87 #define TMS570_ESM_IESR1_INTENSET_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
    88 
    89 
    90 /*----------------------TMS570_ESMIECR1----------------------*/
    91 /* field: INTENCLR - Clear Interrupt Enable */
    92 #define TMS570_ESM_IECR1_INTENCLR(val) BSP_FLD32(val,0, 31)
    93 #define TMS570_ESM_IECR1_INTENCLR_GET(reg) BSP_FLD32GET(reg,0, 31)
    94 #define TMS570_ESM_IECR1_INTENCLR_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
    95 
    96 
    97 /*----------------------TMS570_ESMILSR1----------------------*/
    98 /* field: INTLVLSET - Set Interrupt Priority */
    99 #define TMS570_ESM_ILSR1_INTLVLSET(val) BSP_FLD32(val,0, 31)
    100 #define TMS570_ESM_ILSR1_INTLVLSET_GET(reg) BSP_FLD32GET(reg,0, 31)
    101 #define TMS570_ESM_ILSR1_INTLVLSET_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
    102 
    103 
    104 /*----------------------TMS570_ESMILCR1----------------------*/
    105 /* field: INTLVLCLR - Clear Interrupt Priority. */
    106 #define TMS570_ESM_ILCR1_INTLVLCLR(val) BSP_FLD32(val,0, 31)
    107 #define TMS570_ESM_ILCR1_INTLVLCLR_GET(reg) BSP_FLD32GET(reg,0, 31)
    108 #define TMS570_ESM_ILCR1_INTLVLCLR_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
    109 
    110 
    111 /*------------------------TMS570_ESMSR------------------------*/
    112 /* field: ESF - Error Status Flag. Provides status information on a pending error. */
    113 #define TMS570_ESM_SR_ESF(val) BSP_FLD32(val,0, 31)
    114 #define TMS570_ESM_SR_ESF_GET(reg) BSP_FLD32GET(reg,0, 31)
    115 #define TMS570_ESM_SR_ESF_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
    116 
    117 
    118 /*-----------------------TMS570_ESMEPSR-----------------------*/
    119 /* field: EPSF - ERROR Pin Status Flag. Provides status information for the ERROR Pin. */
    120 #define TMS570_ESM_EPSR_EPSF BSP_FLD32(0)
    121 
    122 
    123 /*----------------------TMS570_ESMIOFFHR----------------------*/
     102/*---------------------TMS570_ESM_IOFFHR---------------------*/
    124103/* field: INTOFFH - Offset High Level Interrupt. */
    125104#define TMS570_ESM_IOFFHR_INTOFFH(val) BSP_FLD32(val,0, 6)
     
    128107
    129108
    130 /*----------------------TMS570_ESMIOFFLR----------------------*/
     109/*---------------------TMS570_ESM_IOFFLR---------------------*/
    131110/* field: INTOFFL - Offset Low Level Interrupt. */
    132111#define TMS570_ESM_IOFFLR_INTOFFL(val) BSP_FLD32(val,0, 6)
     
    135114
    136115
    137 /*-----------------------TMS570_ESMLTCR-----------------------*/
     116/*----------------------TMS570_ESM_LTCR----------------------*/
    138117/* field: LTC - ERROR Pin Low-Time Counter */
    139118#define TMS570_ESM_LTCR_LTC(val) BSP_FLD32(val,0, 15)
     
    142121
    143122
    144 /*----------------------TMS570_ESMLTCPR----------------------*/
     123/*----------------------TMS570_ESM_LTCPR----------------------*/
    145124/* field: LTCP - ERROR Pin Low-Time Counter Pre-load Value */
    146125#define TMS570_ESM_LTCPR_LTCP(val) BSP_FLD32(val,0, 15)
     
    149128
    150129
    151 /*-----------------------TMS570_ESMEKR-----------------------*/
     130/*-----------------------TMS570_ESM_EKR-----------------------*/
    152131/* field: EKEY - Error Key. The key to reset the ERROR pin or to force an error on the ERROR pin. */
    153132#define TMS570_ESM_EKR_EKEY(val) BSP_FLD32(val,0, 3)
     
    156135
    157136
    158 /*-----------------------TMS570_ESMSSR2-----------------------*/
     137/*----------------------TMS570_ESM_SSR2----------------------*/
    159138/* field: ESF - Error Status Flag. Shadow register for status information on pending error. */
    160 #define TMS570_ESM_SSR2_ESF(val) BSP_FLD32(val,0, 31)
    161 #define TMS570_ESM_SSR2_ESF_GET(reg) BSP_FLD32GET(reg,0, 31)
    162 #define TMS570_ESM_SSR2_ESF_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
     139/* Whole 32 bits */
     140
     141/*---------------------TMS570_ESM_IEPSR4---------------------*/
     142/* field: IEPSET - Set Influence on ERROR Pin */
     143/* Whole 32 bits */
     144
     145/*---------------------TMS570_ESM_IEPCR4---------------------*/
     146/* field: IEPCLR - Clear Influence on ERROR Pin */
     147/* Whole 32 bits */
     148
     149/*----------------------TMS570_ESM_IESR4----------------------*/
     150/* field: INTENSET - Set Interrupt Enable */
     151/* Whole 32 bits */
     152
     153/*----------------------TMS570_ESM_IECR4----------------------*/
     154/* field: INTENCLR - Clear Interrupt Enable */
     155/* Whole 32 bits */
     156
     157/*----------------------TMS570_ESM_ILSR4----------------------*/
     158/* field: INTLVLSET - Set Interrupt Level */
     159/* Whole 32 bits */
     160
     161/*----------------------TMS570_ESM_ILCR4----------------------*/
     162/* field: INTLVLCLR - Clear Interrupt Level */
     163/* Whole 32 bits */
     164
     165/*-----------------------TMS570_ESM_SR4-----------------------*/
     166/* field: ESF - Error Status Flag. Provides status information on a pending error. */
     167/* Whole 32 bits */
    163168
    164169
    165 /*----------------------TMS570_ESMIEPSR4----------------------*/
    166 /* field: IEPSET - Set Influence on ERROR Pin */
    167 #define TMS570_ESM_IEPSR4_IEPSET(val) BSP_FLD32(val,32, 63)
    168 #define TMS570_ESM_IEPSR4_IEPSET_GET(reg) BSP_FLD32GET(reg,32, 63)
    169 #define TMS570_ESM_IEPSR4_IEPSET_SET(reg,val) BSP_FLD32SET(reg, val,32, 63)
    170 
    171 
    172 /*----------------------TMS570_ESMIEPCR4----------------------*/
    173 /* field: IEPCLR - Clear Influence on ERROR Pin */
    174 #define TMS570_ESM_IEPCR4_IEPCLR(val) BSP_FLD32(val,32, 63)
    175 #define TMS570_ESM_IEPCR4_IEPCLR_GET(reg) BSP_FLD32GET(reg,32, 63)
    176 #define TMS570_ESM_IEPCR4_IEPCLR_SET(reg,val) BSP_FLD32SET(reg, val,32, 63)
    177 
    178 
    179 /*----------------------TMS570_ESMIESR4----------------------*/
    180 /* field: INTENSET - Set Interrupt Enable */
    181 #define TMS570_ESM_IESR4_INTENSET(val) BSP_FLD32(val,32, 63)
    182 #define TMS570_ESM_IESR4_INTENSET_GET(reg) BSP_FLD32GET(reg,32, 63)
    183 #define TMS570_ESM_IESR4_INTENSET_SET(reg,val) BSP_FLD32SET(reg, val,32, 63)
    184 
    185 
    186 /*----------------------TMS570_ESMIECR4----------------------*/
    187 /* field: INTENCLR - Clear Interrupt Enable */
    188 #define TMS570_ESM_IECR4_INTENCLR(val) BSP_FLD32(val,32, 63)
    189 #define TMS570_ESM_IECR4_INTENCLR_GET(reg) BSP_FLD32GET(reg,32, 63)
    190 #define TMS570_ESM_IECR4_INTENCLR_SET(reg,val) BSP_FLD32SET(reg, val,32, 63)
    191 
    192 
    193 /*----------------------TMS570_ESMILSR4----------------------*/
    194 /* field: INTLVLSET - Set Interrupt Level */
    195 #define TMS570_ESM_ILSR4_INTLVLSET(val) BSP_FLD32(val,32, 63)
    196 #define TMS570_ESM_ILSR4_INTLVLSET_GET(reg) BSP_FLD32GET(reg,32, 63)
    197 #define TMS570_ESM_ILSR4_INTLVLSET_SET(reg,val) BSP_FLD32SET(reg, val,32, 63)
    198 
    199 
    200 /*----------------------TMS570_ESMILCR4----------------------*/
    201 /* field: INTLVLCLR - Clear Interrupt Level */
    202 #define TMS570_ESM_ILCR4_INTLVLCLR(val) BSP_FLD32(val,32, 63)
    203 #define TMS570_ESM_ILCR4_INTLVLCLR_GET(reg) BSP_FLD32GET(reg,32, 63)
    204 #define TMS570_ESM_ILCR4_INTLVLCLR_SET(reg,val) BSP_FLD32SET(reg, val,32, 63)
    205 
    206 
    207 /*-----------------------TMS570_ESMSR4-----------------------*/
    208 /* field: ESF - Error Status Flag. Provides status information on a pending error. */
    209 #define TMS570_ESM_SR4_ESF(val) BSP_FLD32(val,32, 63)
    210 #define TMS570_ESM_SR4_ESF_GET(reg) BSP_FLD32GET(reg,32, 63)
    211 #define TMS570_ESM_SR4_ESF_SET(reg,val) BSP_FLD32SET(reg, val,32, 63)