Changeset 9a26317 in rtems
- Timestamp:
- 03/30/04 11:46:37 (20 years ago)
- Branches:
- 4.10, 4.11, 4.8, 4.9, 5, master
- Children:
- d86bae8
- Parents:
- 42540ecd
- Location:
- cpukit/score/cpu/sh
- Files:
-
- 5 edited
Legend:
- Unmodified
- Added
- Removed
-
cpukit/score/cpu/sh/ChangeLog
r42540ecd r9a26317 1 2004-03-30 Ralf Corsepius <ralf_corsepius@rtems.org> 2 3 * cpu.c, rtems/score/cpu.h, rtems/score/sh.h, rtems/score/sh_io.h: 4 Convert to using c99 fixed size types. 5 1 6 2004-03-29 Ralf Corsepius <ralf_corsepius@rtems.org> 2 7 -
cpukit/score/cpu/sh/cpu.c
r42540ecd r9a26317 51 51 ) 52 52 { 53 register u nsigned32level = 0;53 register uint32_t level = 0; 54 54 55 55 /* … … 94 94 */ 95 95 96 u nsigned32_CPU_ISR_Get_level( void )96 uint32_t _CPU_ISR_Get_level( void ) 97 97 { 98 98 /* … … 100 100 */ 101 101 102 register u nsigned32_mask ;102 register uint32_t _mask ; 103 103 104 104 sh_get_interrupt_level( _mask ); … … 113 113 114 114 void _CPU_ISR_install_raw_handler( 115 u nsigned32vector,115 uint32_t vector, 116 116 proc_ptr new_handler, 117 117 proc_ptr *old_handler … … 125 125 126 126 #if SH_PARANOID_ISR 127 u nsigned32level ;127 uint32_t level ; 128 128 129 129 sh_disable_interrupts( level ); … … 160 160 #if defined(__sh1__) || defined(__sh2__) 161 161 void _CPU_ISR_install_vector( 162 u nsigned32vector,162 uint32_t vector, 163 163 proc_ptr new_handler, 164 164 proc_ptr *old_handler … … 224 224 #if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) 225 225 226 u nsigned8_bit_set_table[16] =226 uint8_t _bit_set_table[16] = 227 227 { 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 2, 2, 1,0}; 228 228 … … 233 233 Context_Control *_the_context, 234 234 void *_stack_base, 235 u nsigned32_size,236 u nsigned32_isr,235 uint32_t _size, 236 uint32_t _isr, 237 237 void (*_entry_point)(void), 238 238 int _is_fp ) 239 239 { 240 _the_context->r15 = (u nsigned32*) ((unsigned32) (_stack_base) + (_size) );240 _the_context->r15 = (uint32_t *) ((uint32_t ) (_stack_base) + (_size) ); 241 241 #if defined(__sh1__) || defined(__sh2__) 242 242 _the_context->sr = (_isr << 4) & 0x00f0 ; … … 244 244 _the_context->sr = SH4_SR_MD | ((_isr << 4) & 0x00f0); 245 245 #endif 246 _the_context->pr = (u nsigned32*) _entry_point ;246 _the_context->pr = (uint32_t *) _entry_point ; 247 247 248 248 -
cpukit/score/cpu/sh/rtems/score/cpu.h
r42540ecd r9a26317 333 333 334 334 typedef struct { 335 u nsigned32*r15; /* stack pointer */336 337 u nsigned32macl;338 u nsigned32mach;339 u nsigned32*pr;340 341 u nsigned32*r14; /* frame pointer/call saved */342 343 u nsigned32r13; /* call saved */344 u nsigned32r12; /* call saved */345 u nsigned32r11; /* call saved */346 u nsigned32r10; /* call saved */347 u nsigned32r9; /* call saved */348 u nsigned32r8; /* call saved */349 350 u nsigned32*r7; /* arg in */351 u nsigned32*r6; /* arg in */335 uint32_t *r15; /* stack pointer */ 336 337 uint32_t macl; 338 uint32_t mach; 339 uint32_t *pr; 340 341 uint32_t *r14; /* frame pointer/call saved */ 342 343 uint32_t r13; /* call saved */ 344 uint32_t r12; /* call saved */ 345 uint32_t r11; /* call saved */ 346 uint32_t r10; /* call saved */ 347 uint32_t r9; /* call saved */ 348 uint32_t r8; /* call saved */ 349 350 uint32_t *r7; /* arg in */ 351 uint32_t *r6; /* arg in */ 352 352 353 353 #if 0 354 u nsigned32*r5; /* arg in */355 u nsigned32*r4; /* arg in */356 #endif 357 358 u nsigned32*r3; /* scratch */359 u nsigned32*r2; /* scratch */360 u nsigned32*r1; /* scratch */361 362 u nsigned32*r0; /* arg return */363 364 u nsigned32gbr;365 u nsigned32sr;354 uint32_t *r5; /* arg in */ 355 uint32_t *r4; /* arg in */ 356 #endif 357 358 uint32_t *r3; /* scratch */ 359 uint32_t *r2; /* scratch */ 360 uint32_t *r1; /* scratch */ 361 362 uint32_t *r0; /* arg return */ 363 364 uint32_t gbr; 365 uint32_t sr; 366 366 367 367 } Context_Control; … … 380 380 } r; 381 381 float fpul; /* fp communication register */ 382 u nsigned32fpscr; /* fp control register */382 uint32_t fpscr; /* fp control register */ 383 383 #endif /* SH_HAS_FPU */ 384 384 } Context_Control_fp; … … 399 399 void (*idle_task)( void ); 400 400 boolean do_zero_of_workspace; 401 u nsigned32idle_task_stack_size;402 u nsigned32interrupt_stack_size;403 u nsigned32extra_mpci_receive_server_stack;404 void * (*stack_allocate_hook)( u nsigned32);401 uint32_t idle_task_stack_size; 402 uint32_t interrupt_stack_size; 403 uint32_t extra_mpci_receive_server_stack; 404 void * (*stack_allocate_hook)( uint32_t ); 405 405 void (*stack_free_hook)( void* ); 406 406 /* end of fields required on all CPUs */ 407 u nsigned32clicks_per_second ; /* cpu frequency in Hz */407 uint32_t clicks_per_second ; /* cpu frequency in Hz */ 408 408 } rtems_cpu_table; 409 409 … … 464 464 465 465 /* XXX: if needed, put more variables here */ 466 SCORE_EXTERN void CPU_delay( u nsigned32microseconds );466 SCORE_EXTERN void CPU_delay( uint32_t microseconds ); 467 467 468 468 /* … … 611 611 sh_set_interrupt_level(_newlevel) 612 612 613 u nsigned32_CPU_ISR_Get_level( void );613 uint32_t _CPU_ISR_Get_level( void ); 614 614 615 615 /* end of ISR handler macros */ … … 644 644 Context_Control *_the_context, 645 645 void *_stack_base, 646 u nsigned32_size,647 u nsigned32_isr,646 uint32_t _size, 647 uint32_t _isr, 648 648 void (*_entry_point)(void), 649 649 int _is_fp ); … … 717 717 #ifdef BSP_FATAL_HALT 718 718 /* we manage the fatal error in the board support package */ 719 void bsp_fatal_halt( u nsigned32_error);719 void bsp_fatal_halt( uint32_t _error); 720 720 #define _CPU_Fatal_halt( _error ) bsp_fatal_halt( _error) 721 721 #else … … 792 792 #if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) 793 793 794 extern u nsigned8_bit_set_table[];794 extern uint8_t _bit_set_table[]; 795 795 796 796 #define _CPU_Bitfield_Find_first_bit( _value, _output ) \ … … 857 857 858 858 void _CPU_ISR_install_raw_handler( 859 u nsigned32vector,859 uint32_t vector, 860 860 proc_ptr new_handler, 861 861 proc_ptr *old_handler … … 869 869 870 870 void _CPU_ISR_install_vector( 871 u nsigned32vector,871 uint32_t vector, 872 872 proc_ptr new_handler, 873 873 proc_ptr *old_handler -
cpukit/score/cpu/sh/rtems/score/sh.h
r42540ecd r9a26317 163 163 #define sh_get_interrupt_level( _level ) \ 164 164 { \ 165 register u nsigned32_tmpsr ; \165 register uint32_t _tmpsr ; \ 166 166 \ 167 167 asm volatile( "stc sr, %0" : "=r" (_tmpsr) ); \ … … 171 171 #define sh_set_interrupt_level( _newlevel ) \ 172 172 { \ 173 register u nsigned32_tmpsr; \173 register uint32_t _tmpsr; \ 174 174 \ 175 175 asm volatile ( "stc sr, %0" : "=r" (_tmpsr) ); \ -
cpukit/score/cpu/sh/rtems/score/sh_io.h
r42540ecd r9a26317 31 31 #define readw(addr) (*(volatile unsigned short *) (addr)) 32 32 #define readl(addr) (*(volatile unsigned int *) (addr)) 33 #define read8(addr) (*(volatile u nsigned8*) (addr))34 #define read16(addr) (*(volatile u nsigned16*) (addr))35 #define read32(addr) (*(volatile u nsigned32*) (addr))33 #define read8(addr) (*(volatile uint8_t *) (addr)) 34 #define read16(addr) (*(volatile uint16_t *) (addr)) 35 #define read32(addr) (*(volatile uint32_t *) (addr)) 36 36 37 37 #define writeb(b,addr) ((*(volatile unsigned char *) (addr)) = (b)) 38 38 #define writew(b,addr) ((*(volatile unsigned short *) (addr)) = (b)) 39 39 #define writel(b,addr) ((*(volatile unsigned int *) (addr)) = (b)) 40 #define write8(b,addr) ((*(volatile u nsigned8*) (addr)) = (b))41 #define write16(b,addr) ((*(volatile u nsigned16*) (addr)) = (b))42 #define write32(b,addr) ((*(volatile u nsigned32*) (addr)) = (b))40 #define write8(b,addr) ((*(volatile uint8_t *) (addr)) = (b)) 41 #define write16(b,addr) ((*(volatile uint16_t *) (addr)) = (b)) 42 #define write32(b,addr) ((*(volatile uint32_t *) (addr)) = (b)) 43 43 44 44 #define inb(addr) readb(addr)
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