Changeset 993e1b5 in rtems


Ignore:
Timestamp:
Apr 14, 1998, 7:54:24 PM (22 years ago)
Author:
Joel Sherrill <joel.sherrill@…>
Branches:
4.10, 4.11, 4.8, 4.9, master
Children:
b0562e74
Parents:
a34ab1b2
Message:

Refreshing effort from Avenger.

Location:
c/src/exec/score/cpu/powerpc
Files:
8 edited

Legend:

Unmodified
Added
Removed
  • c/src/exec/score/cpu/powerpc/README

    ra34ab1b2 r993e1b5  
    1212is copyright 1995 i-cubed ltd.
    1313
    14 
     14This port was later updated by Joel Sherrill <joel@OARcorp.com>
     15to test the support for the PPC603, PPC603e, and PPC604.  This
     16was tested on the PowerPC simulator PSIM and a VMEbus single board
     17computer.
    1518
    16192) CPU support.
    1720
    18 This release fully supports the IBM PPC403GA and PPC403GB processors.
     21This release fully supports the PPC403GA, PPC403GB, PPC603, PPC603e,
     22and PPC604 processors.  A good faith attempt has been made to include
     23support other models based upon available documentation.
    1924
    20 It has only been tested on the PPC403GA (using software floating
    21 point).
     25This port was originally written and tested on the PPC403GA (using
     26software floating point).  Current ports are tested on 60x CPUs
     27using the PowerPC simulator PSIM.
    2228
    23 With the gratefully acknowledged assistance of IBM and Blue Micro,
    24 this release contains code to support the following processors
    25   PPC601, PPC603, PPC603e, PPC604, and PPC602.
     29Andrew Bray received assistance during the initial porting effort
     30from IBM and Blue Micro and we would like to gratefully acknowledge
     31that help.
    2632
    27 The support for these processors is incomplete, especially that for
    28 the PPC602 for which only sketchy data is currently available.
     33The support for the PPC602 processor is incomplete as only sketchy
     34data is currently available.  Perhaps this model has been dropped.
    2935
    3036
     
    5965
    6066This port was built and tested using the PowerOpen ABI, with the following
    61 caveat:  we used an ELF assembler and linker.  So some attention may be required
    62 on the assembler files to get them through a traditional (XCOFF) PowerOpen
    63 assembler.
     67caveat:  we used an ELF assembler and linker.  So some attention may be
     68required on the assembler files to get them through a traditional (XCOFF)
     69PowerOpen assembler.
    6470
    65 This port contains support for the other ABIs, but this may prove to be incomplete
    66 as it is untested.
     71This port contains support for the other ABIs, but this may prove to be
     72incomplete as it is untested.
    6773
    68 In the long term, the RTEMS PowerPC port should move to the EABI as its primary
    69 or only port.  This should wait on a true EABI version of GCC.
     74The RTEMS PowerPC port supports EABI as the primary ABI.  The powerpc-rtems
     75GNU toolset configuration is EABI and .
    7076
    71 Andrew Bray 4/December/1995
     77Andrew Bray,   4 December 1995
     78Joel Sherrill, 16 July 1997
  • c/src/exec/score/cpu/powerpc/cpu.c

    ra34ab1b2 r993e1b5  
    1919 *  Derived from c/src/exec/cpu/no_cpu/cpu.c:
    2020 *
    21  *  COPYRIGHT (c) 1989-1998.
     21 *  COPYRIGHT (c) 1989-1997.
    2222 *  On-Line Applications Research Corporation (OAR).
    2323 *  Copyright assigned to U.S. Government, 1994.
    2424 *
    25  *  The license and distribution terms for this file may be
    26  *  found in the file LICENSE in this distribution or at
     25 *  The license and distribution terms for this file may be found in
     26 *  the file LICENSE in this distribution or at
    2727 *  http://www.OARcorp.com/rtems/license.html.
    2828 *
     
    3838 *  These are for testing purposes.
    3939 */
    40 #undef Testing
    41 
    42 #ifdef Testing
    43 static unsigned32 msr;
    44 #ifdef ppc403
    45 static unsigned32 evpr;
    46 static unsigned32 exier;
    47 #endif
    48 #endif
    49 
    50 /*
    51  *  ppc_interrupt_level_to_msr
    52  *
    53  *  This routine converts a two bit interrupt level to an MSR bit map.
    54  */
    55 
    56 const unsigned32 _CPU_msrs[4] =
    57   { PPC_MSR_0, PPC_MSR_1, PPC_MSR_2, PPC_MSR_3 };
    5840
    5941/*  _CPU_Initialize
     
    7658  int i;
    7759#if (PPC_ABI != PPC_ABI_POWEROPEN)
    78   register unsigned32 r2;
     60  register unsigned32 r2 = 0;
    7961#if (PPC_ABI != PPC_ABI_GCC27)
    80   register unsigned32 r13;
     62  register unsigned32 r13 = 0;
    8163
    8264  asm ("mr %0,13" : "=r" ((r13)) : "0" ((r13)));
     
    9779  _CPU_IRQ_info.Signal = &_ISR_Signals_to_thread_executing;
    9880
     81#if (PPC_USE_SPRG)
    9982  i = (int)&_CPU_IRQ_info;
    10083  asm volatile("mtspr 0x113, %0" : "=r" (i) : "0" (i)); /* SPRG 3 */
    101 
    102   i = PPC_MSR_INITIAL & ~PPC_MSR_DISABLE_MASK;
     84#endif
     85
     86  /*
     87   * Store Msr Value in the IRQ info structure.
     88   */
     89   _CPU_MSR_Value(_CPU_IRQ_info.msr_initial);
     90 
     91#if (PPC_USE_SPRG)
     92  i = _CPU_IRQ_info.msr_initial;
    10393  asm volatile("mtspr 0x112, %0" : "=r" (i) : "0" (i)); /* SPRG 2 */
    104 
    105 #ifdef Testing
    106   {
    107     unsigned32 tmp;
    108 
    109     asm volatile ("mfmsr %0" : "=&r" (tmp));
    110     msr = tmp;
    111 #ifdef ppc403
    112     asm volatile ("mfspr %0, 0x3d6" : "=&r" (tmp)); /* EVPR */
    113     evpr = tmp;
    114     asm volatile ("mfdcr %0, 0x42" : "=&r" (tmp)); /* EXIER */
    115     exier = tmp;
    116     asm volatile ("mtspr 0x3d6, %0" :: "r" (0)); /* EVPR */
    117 #endif
    118   }
    11994#endif
    12095
     
    130105/*PAGE
    131106 *
    132  *  _CPU_ISR_Get_level
    133  *
    134  *  COMMENTS FROM Andrew Bray <andy@i-cubed.co.uk>:
     107 *  _CPU_ISR_Calculate_level
    135108 *
    136109 *  The PowerPC puts its interrupt enable status in the MSR register
    137110 *  which also contains things like endianness control.  To be more
    138111 *  awkward, the layout varies from processor to processor.  This
    139  *  is why I adopted a table approach in my interrupt handling.
    140  *  Thus the inverse process is slow, because it requires a table
    141  *  search.
    142  *
    143  *  This could fail, and return 4 (an invalid level) if the MSR has been
    144  *  set to a value not in the table.  This is also quite an expensive
    145  *  operation - I do hope its not too common.
    146  *
     112 *  is why it was necessary to adopt a scheme which allowed the user
     113 *  to specify specifically which interrupt sources were enabled.
    147114 */
    148115 
     116unsigned32 _CPU_ISR_Calculate_level(
     117  unsigned32 new_level
     118)
     119{
     120  register unsigned32 new_msr = 0;
     121
     122  /*
     123   *  Set the critical interrupt enable bit
     124   */
     125
     126#if (PPC_HAS_RFCI)
     127  if ( !(new_level & PPC_INTERRUPT_LEVEL_CE) )
     128    new_msr |= PPC_MSR_CE;
     129#endif
     130
     131  if ( !(new_level & PPC_INTERRUPT_LEVEL_ME) )
     132    new_msr |= PPC_MSR_ME;
     133
     134  if ( !(new_level & PPC_INTERRUPT_LEVEL_EE) )
     135    new_msr |= PPC_MSR_EE;
     136
     137  return new_msr;
     138}
     139
     140/*PAGE
     141 *
     142 *  _CPU_ISR_Set_level
     143 *
     144 *  This routine sets the requested level in the MSR.
     145 */
     146
     147void _CPU_ISR_Set_level(
     148  unsigned32 new_level
     149)
     150{
     151  register unsigned32 tmp = 0;
     152  register unsigned32 new_msr;
     153
     154  new_msr = _CPU_ISR_Calculate_level( new_level );
     155
     156  asm volatile (
     157    "mfmsr %0; andc %0,%0,%1; and %2, %2, %1; or %0, %0, %2; mtmsr %0" :
     158    "=&r" ((tmp)) :
     159    "r" ((PPC_MSR_DISABLE_MASK)), "r" ((new_msr)), "0" ((tmp))
     160  );
     161}
     162
     163/*PAGE
     164 *
     165 *  _CPU_ISR_Get_level
     166 *
     167 *  This routine gets the current interrupt level from the MSR and
     168 *  converts it to an RTEMS interrupt level.
     169 */
     170
    149171unsigned32 _CPU_ISR_Get_level( void )
    150172{
    151   unsigned32 level, msr;
     173  unsigned32 level = 0;
     174  unsigned32 msr;
    152175 
    153176  asm volatile("mfmsr %0" : "=r" ((msr)));
    154177 
    155178  msr &= PPC_MSR_DISABLE_MASK;
     179
     180  /*
     181   *  Set the critical interrupt enable bit
     182   */
     183
     184#if (PPC_HAS_RFCI)
     185  if ( !(msr & PPC_MSR_CE) )
     186    level |= PPC_INTERRUPT_LEVEL_CE;
     187#endif
     188
     189  if ( !(msr & PPC_MSR_ME) )
     190    level |= PPC_INTERRUPT_LEVEL_ME;
     191
     192  if ( !(msr & PPC_MSR_EE) )
     193    level |= PPC_INTERRUPT_LEVEL_EE;
     194
     195  return level;
     196}
     197
     198/*PAGE
     199 *
     200 *  _CPU_Context_Initialize
     201 */
     202
     203#if (PPC_ABI == PPC_ABI_POWEROPEN)
     204#define CPU_MINIMUM_STACK_FRAME_SIZE 56
     205#else /* PPC_ABI_SVR4 or PPC_ABI_EABI */
     206#define CPU_MINIMUM_STACK_FRAME_SIZE 8
     207#endif
     208
     209void _CPU_Context_Initialize(
     210  Context_Control  *the_context,
     211  unsigned32       *stack_base,
     212  unsigned32        size,
     213  unsigned32        new_level,
     214  void             *entry_point,
     215  boolean           is_fp
     216)
     217{
     218  unsigned32 msr_value;
     219  unsigned32 sp;
     220
     221  sp = (unsigned32)stack_base + size - CPU_MINIMUM_STACK_FRAME_SIZE;
     222  *((unsigned32 *)sp) = 0;
     223  the_context->gpr1 = sp;
     224   
     225  the_context->msr = _CPU_ISR_Calculate_level( new_level );
     226
     227  /*
     228   *  The FP bit of the MSR should only be enabled if this is a floating
     229   *  point task.  Unfortunately, the vfprintf_r routine in newlib
     230   *  ends up pushing a floating point register regardless of whether or
     231   *  not a floating point number is being printed.  Serious restructuring
     232   *  of vfprintf.c will be required to avoid this behavior.  At this
     233   *  time (7 July 1997), this restructuring is not being done.
     234   */
     235
     236  /*if ( is_fp ) */
     237    the_context->msr |= PPC_MSR_FP;
     238
     239  /*
     240   *  Calculate the task's MSR value:
     241   *
     242   *     + Set the exception prefix bit to point to the exception table
     243   *     + Force the RI bit
     244   *     + Use the DR and IR bits
     245   */
     246  _CPU_MSR_Value( msr_value );
     247  the_context->msr |= (msr_value & PPC_MSR_EP);
     248  the_context->msr |= PPC_MSR_RI;
     249  the_context->msr |= msr_value & (PPC_MSR_DR|PPC_MSR_IR);
     250
     251#if (PPC_ABI == PPC_ABI_POWEROPEN)
     252  { unsigned32 *desc = (unsigned32 *)entry_point;
     253
     254    the_context->pc = desc[0];
     255    the_context->gpr2 = desc[1];
     256  }
     257#endif
     258
     259#if (PPC_ABI == PPC_ABI_SVR4)
     260  { unsigned    r13 = 0;
     261    asm volatile ("mr %0, 13" : "=r" ((r13)));
     262   
     263    the_context->pc = (unsigned32)entry_point;
     264    the_context->gpr13 = r13;
     265  }
     266#endif
     267
     268#if (PPC_ABI == PPC_ABI_EABI)
     269  { unsigned32  r2 = 0;
     270    unsigned    r13 = 0;
     271    asm volatile ("mr %0,2; mr %1,13" : "=r" ((r2)), "=r" ((r13)));
    156272 
    157   for (level = 0; level < 4; level++)
    158     if ((_CPU_msrs[level] & PPC_MSR_DISABLE_MASK) == msr)
    159       break;
    160  
    161   return level;
    162 }
     273    the_context->pc = (unsigned32)entry_point;
     274    the_context->gpr2 = r2;
     275    the_context->gpr13 = r13;
     276  }
     277#endif
     278}
     279
    163280
    164281/*  _CPU_ISR_install_vector
     
    182299)
    183300{
     301   proc_ptr   ignored;
    184302   *old_handler = _ISR_Vector_table[ vector ];
    185303
     
    191309
    192310   /*
     311    * Install the wrapper so this ISR can be invoked properly.
     312    */
     313   if (_CPU_Table.exceptions_in_RAM)
     314      _CPU_ISR_install_raw_handler( vector, _ISR_Handler, &ignored );
     315
     316   /*
    193317    *  We put the actual user ISR address in '_ISR_vector_table'.  This will
    194318    *  be used by the _ISR_Handler so the user gets control.
     
    227351            register int r = 0;
    228352
    229             asm volatile("mtdcr 0x42, %0" : "=r" ((r)) : "0" ((r))); /* EXIER */
     353            asm volatile("mtdcr 0x42, %0" :
     354                "=&r" ((r)) : "0" ((r))); /* EXIER */
    230355        }
    231356    else if (v == PPC_IRQ_PIT)
     
    233358            register int r = 0x08000000;
    234359
    235             asm volatile("mtspr 0x3d8, %0" : "=r" ((r)) : "0" ((r))); /* TSR */
     360            asm volatile("mtspr 0x3d8, %0" :
     361                "=&r" ((r)) : "0" ((r))); /* TSR */
    236362        }
    237363    else if (v == PPC_IRQ_FIT)
     
    239365            register int r = 0x04000000;
    240366
    241             asm volatile("mtspr 0x3d8, %0" : "=r" ((r)) : "0" ((r))); /* TSR */
     367            asm volatile("mtspr 0x3d8, %0" :
     368                "=&r" ((r)) : "0" ((r))); /* TSR */
    242369        }
    243370#endif
     
    246373void _CPU_Fatal_error(unsigned32 _error)
    247374{
    248 #ifdef Testing
    249   unsigned32 tmp;
    250 
    251   tmp = msr;
    252   asm volatile ("mtmsr %0" :: "r" (tmp));
    253 #ifdef ppc403
    254   tmp = evpr;
    255   asm volatile ("mtspr 0x3d6, %0" :: "r" (tmp)); /* EVPR */
    256   tmp = exier;
    257   asm volatile ("mtdcr 0x42, %0" :: "r" (tmp)); /* EXIER */
    258 #endif
    259 #endif
    260375  asm volatile ("mr 3, %0" : : "r" ((_error)));
    261376  asm volatile ("tweq 5,5");
     
    263378  while (1) ;
    264379}
     380
     381#define PPC_SYNCHRONOUS_TRAP_BIT_MASK    0x100
     382#define PPC_ASYNCHRONOUS_TRAP( _trap ) (_trap)
     383#define PPC_SYNCHRONOUS_TRAP ( _trap ) ((_trap)+PPC_SYNCHRONOUS_TRAP_BIT_MASK)
     384#define PPC_REAL_TRAP_NUMBER ( _trap ) ((_trap)%PPC_SYNCHRONOUS_TRAP_BIT_MASK)
     385
     386
     387const CPU_Trap_table_entry _CPU_Trap_slot_template = {
     388
     389#if (PPC_ABI == PPC_ABI_POWEROPEN || PPC_ABI == PPC_ABI_GCC27)
     390#error " Vector install not tested."
     391#if (PPC_HAS_FPU)
     392#error " Vector install not tested."
     393  0x9421feb0,           /* stwu r1, -(20*4 + 18*8 + IP_END)(r1) */
     394#else
     395#error " Vector install not tested."
     396  0x9421ff40,           /* stwu    r1, -(20*4 + IP_END)(r1)     */
     397#endif
     398#else
     399  0x9421ff90,           /* stwu    r1, -(IP_END)(r1)            */
     400#endif
     401
     402  0x90010008,           /* stw   %r0, IP_0(%r1)                 */
     403  0x38000000,           /* li    %r0, PPC_IRQ                   */
     404  0x48000002            /* ba    PROC (_ISR_Handler)            */
     405};
     406
     407unsigned32  ppc_exception_vector_addr(
     408  unsigned32 vector
     409);
     410
     411
     412/*PAGE
     413 *
     414 *  _CPU_ISR_install_raw_handler
     415 *
     416 *  This routine installs the specified handler as a "raw" non-executive
     417 *  supported trap handler (a.k.a. interrupt service routine).
     418 *
     419 *  Input Parameters:
     420 *    vector      - trap table entry number plus synchronous
     421 *                    vs. asynchronous information
     422 *    new_handler - address of the handler to be installed
     423 *    old_handler - pointer to an address of the handler previously installed
     424 *
     425 *  Output Parameters: NONE
     426 *    *new_handler - address of the handler previously installed
     427 *
     428 *  NOTE:
     429 *
     430 *  This routine is based on the SPARC routine _CPU_ISR_install_raw_handler.
     431 *  Install a software trap handler as an executive interrupt handler
     432 *  (which is desirable since RTEMS takes care of window and register issues),
     433 *  then the executive needs to know that the return address is to the trap
     434 *  rather than the instruction following the trap.
     435 *
     436 */
     437 
     438void _CPU_ISR_install_raw_handler(
     439  unsigned32  vector,
     440  proc_ptr    new_handler,
     441  proc_ptr   *old_handler
     442)
     443{
     444  unsigned32             real_vector;
     445  CPU_Trap_table_entry  *slot;
     446  unsigned32             u32_handler=0;
     447
     448  /*
     449   *  Get the "real" trap number for this vector ignoring the synchronous
     450   *  versus asynchronous indicator included with our vector numbers.
     451   */
     452
     453  real_vector = vector;
     454
     455  /*
     456   *  Get the current base address of the trap table and calculate a pointer
     457   *  to the slot we are interested in.
     458   */
     459  slot = (CPU_Trap_table_entry  *)ppc_exception_vector_addr( real_vector );
     460
     461  /*
     462   *  Get the address of the old_handler from the trap table.
     463   *
     464   *  NOTE: The old_handler returned will be bogus if it does not follow
     465   *        the RTEMS model.
     466   */
     467
     468#define HIGH_BITS_MASK   0xFFFFFC00
     469#define HIGH_BITS_SHIFT  10
     470#define LOW_BITS_MASK    0x000003FF
     471
     472  if (slot->stwu_r1 == _CPU_Trap_slot_template.stwu_r1) {
     473    /*
     474     * Set u32_handler = to target address 
     475     */
     476    u32_handler = slot->b_Handler & 0x03fffffc;
     477    *old_handler =  (proc_ptr) u32_handler;
     478  } else
     479    *old_handler = 0;
     480
     481  /*
     482   *  Copy the template to the slot and then fix it.
     483   */
     484  *slot = _CPU_Trap_slot_template;
     485
     486  u32_handler = (unsigned32) new_handler;
     487  slot->b_Handler |= u32_handler;
     488
     489  slot->li_r0_IRQ  |= vector;
     490
     491  _CPU_Data_Cache_Block_Flush( slot );
     492}
     493
     494unsigned32  ppc_exception_vector_addr(
     495  unsigned32 vector
     496)
     497{
     498  unsigned32 Msr;
     499  unsigned32 Top = 0;
     500  unsigned32 Offset = 0x000;
     501
     502  _CPU_MSR_Value ( Msr );
     503  if ( ( Msr & PPC_MSR_EP) != 0 ) /* Vectors at FFFx_xxxx */
     504    Top = 0xfff00000;
     505
     506  switch ( vector ) {
     507    case PPC_IRQ_SYSTEM_RESET:   /* on 40x aka PPC_IRQ_CRIT */
     508      Offset = 0x00100;
     509      break;
     510    case PPC_IRQ_MCHECK:
     511      Offset = 0x00200;
     512      break;
     513    case PPC_IRQ_PROTECT:
     514      Offset = 0x00300;
     515      break;
     516    case PPC_IRQ_ISI:
     517      Offset = 0x00400;
     518      break;
     519    case PPC_IRQ_EXTERNAL:
     520      Offset = 0x00500;
     521      break;
     522    case PPC_IRQ_ALIGNMENT:
     523      Offset = 0x00600;
     524      break;
     525    case PPC_IRQ_PROGRAM:
     526      Offset = 0x00700;
     527      break;
     528    case PPC_IRQ_NOFP:
     529      Offset = 0x00800;
     530      break;
     531    case PPC_IRQ_DECREMENTER:
     532      Offset = 0x00900;
     533      break;
     534    case PPC_IRQ_RESERVED_A:
     535      Offset = 0x00a00;
     536      break;
     537    case PPC_IRQ_RESERVED_B:
     538      Offset = 0x00b00;
     539      break;
     540    case PPC_IRQ_SCALL:
     541      Offset = 0x00c00;
     542      break;
     543    case PPC_IRQ_TRACE:
     544      Offset = 0x00d00;
     545      break;
     546    case PPC_IRQ_FP_ASST:
     547      Offset = 0x00e00;
     548      break;
     549
     550#if defined(ppc403)
     551                                 
     552/*  PPC_IRQ_CRIT is the same vector as PPC_IRQ_RESET
     553    case PPC_IRQ_CRIT:
     554      Offset = 0x00100;
     555      break;
     556*/
     557    case PPC_IRQ_PIT:
     558      Offset = 0x01000;
     559      break;
     560    case PPC_IRQ_FIT:
     561      Offset = 0x01010;
     562      break;
     563    case PPC_IRQ_WATCHDOG:
     564      Offset = 0x01020;
     565      break;
     566    case PPC_IRQ_DEBUG:
     567      Offset = 0x02000;
     568      break;
     569
     570#elif defined(ppc601)
     571    case PPC_IRQ_TRACE:
     572      Offset = 0x02000;
     573      break;
     574
     575#elif defined(ppc603)
     576    case PPC_IRQ_TRANS_MISS:
     577      Offset = 0x1000;
     578      break;
     579    case PPC_IRQ_DATA_LOAD:
     580      Offset = 0x1100;
     581      break;
     582    case PPC_IRQ_DATA_STORE:
     583      Offset = 0x1200;
     584      break;
     585    case PPC_IRQ_ADDR_BRK:
     586      Offset = 0x1300;
     587      break;
     588    case PPC_IRQ_SYS_MGT:
     589      Offset = 0x1400;
     590      break;
     591
     592#elif defined(ppc603e)
     593    case PPC_TLB_INST_MISS:
     594      Offset = 0x1000;
     595      break;
     596    case PPC_TLB_LOAD_MISS:
     597      Offset = 0x1100;
     598      break;
     599    case PPC_TLB_STORE_MISS:
     600      Offset = 0x1200;
     601      break;
     602    case PPC_IRQ_ADDRBRK:
     603      Offset = 0x1300;
     604      break;
     605    case PPC_IRQ_SYS_MGT:
     606      Offset = 0x1400;
     607      break;
     608
     609#elif defined(ppc604)
     610    case PPC_IRQ_ADDR_BRK:
     611      Offset = 0x1300;
     612      break;
     613    case PPC_IRQ_SYS_MGT:
     614      Offset = 0x1400;
     615      break;
     616#endif
     617
     618  }
     619  Top += Offset;
     620  return Top;
     621}
     622
  • c/src/exec/score/cpu/powerpc/cpu.h

    ra34ab1b2 r993e1b5  
    2121 *  Derived from c/src/exec/cpu/no_cpu/cpu.h:
    2222 *
    23  *  COPYRIGHT (c) 1989-1998.
     23 *  COPYRIGHT (c) 1989-1997.
    2424 *  On-Line Applications Research Corporation (OAR).
    2525 *  Copyright assigned to U.S. Government, 1994.
    2626 *
    27  *  The license and distribution terms for this file may be
    28  *  found in the file LICENSE in this distribution or at
     27 *  The license and distribution terms for this file may in
     28 *  the file LICENSE in this distribution or at
    2929 *  http://www.OARcorp.com/rtems/license.html.
    3030 *
     
    286286
    287287#define CPU_STRUCTURE_ALIGNMENT \
    288    __attribute__ ((aligned (PPC_CACHE_ALIGNMENT)))
     288  __attribute__ ((aligned (PPC_CACHE_ALIGNMENT)))
    289289
    290290/*
     
    301301 *  interrupt field of the task mode.  How those bits map to the
    302302 *  CPU interrupt levels is defined by the routine _CPU_ISR_Set_level().
    303  */
    304 /*
    305  *  ACB Note: Levels are:
    306  *   0: All maskable interrupts enabled
    307  *   1: Other critical exceptions enabled
    308  *   2: Machine check enabled
    309  *   3: All maskable IRQs disabled
    310  */
    311 
    312 #define CPU_MODES_INTERRUPT_MASK   0x00000003
     303 *
     304 *  The interrupt level is bit mapped for the PowerPC family. The
     305 *  bits are set to 0 to indicate that a particular exception source
     306 *  enabled and 1 if it is disabled.  This keeps with RTEMS convention
     307 *  that interrupt level 0 means all sources are enabled.
     308 *
     309 *  The bits are assigned to correspond to enable bits in the MSR.
     310 */
     311
     312#define PPC_INTERRUPT_LEVEL_ME   0x01
     313#define PPC_INTERRUPT_LEVEL_EE   0x02
     314#define PPC_INTERRUPT_LEVEL_CE   0x04
     315
     316/* XXX should these be maskable? */
     317#if 0
     318#define PPC_INTERRUPT_LEVEL_DE   0x08
     319#define PPC_INTERRUPT_LEVEL_BE   0x10
     320#define PPC_INTERRUPT_LEVEL_SE   0x20
     321#endif
     322
     323#define CPU_MODES_INTERRUPT_MASK   0x00000007
    313324
    314325/*
     
    451462  /* end of fields required on all CPUs */
    452463
    453   unsigned32   clicks_per_usec; /* Timer clicks per microsecond */
    454   unsigned32   serial_per_sec;  /* Serial clocks per second */
     464  unsigned32   clicks_per_usec;        /* Timer clicks per microsecond */
     465  void       (*spurious_handler)(unsigned32 vector, CPU_Interrupt_frame *);
     466  boolean      exceptions_in_RAM;     /* TRUE if in RAM */
     467
     468#if defined(ppc403)
     469  unsigned32   serial_per_sec;         /* Serial clocks per second */
    455470  boolean      serial_external_clock;
    456471  boolean      serial_xon_xoff;
     
    458473  unsigned32   serial_rate;
    459474  unsigned32   timer_average_overhead; /* Average overhead of timer in ticks */
    460   unsigned32   timer_least_valid; /* Least valid number from timer */
    461   void (*spurious_handler)(unsigned32 vector, CPU_Interrupt_frame *);
     475  unsigned32   timer_least_valid;      /* Least valid number from timer */
     476#endif
    462477}   rtems_cpu_table;
     478
     479/*
     480 *  The following type defines an entry in the PPC's trap table.
     481 *
     482 *  NOTE: The instructions chosen are RTEMS dependent although one is
     483 *        obligated to use two of the four instructions to perform a
     484 *        long jump.  The other instructions load one register with the
     485 *        trap type (a.k.a. vector) and another with the psr.
     486 */
     487 
     488typedef struct {
     489  unsigned32   stwu_r1;                       /* stwu  %r1, -(??+IP_END)(%1)*/
     490  unsigned32   stw_r0;                        /* stw   %r0, IP_0(%r1)       */
     491  unsigned32   li_r0_IRQ;                     /* li    %r0, _IRQ            */
     492  unsigned32   b_Handler;                     /* b     PROC (_ISR_Handler)  */
     493} CPU_Trap_table_entry;
    463494
    464495/*
     
    502533 *  Nothing prevents the porter from declaring more CPU specific variables.
    503534 */
     535
    504536
    505537SCORE_EXTERN struct {
     
    518550  volatile boolean *Switch_necessary;
    519551  boolean *Signal;
     552
     553  unsigned32 msr_initial;
    520554} _CPU_IRQ_info CPU_STRUCTURE_ALIGNMENT;
    521555
     
    550584 */
    551585
    552 #define CPU_INTERRUPT_NUMBER_OF_VECTORS  (PPC_INTERRUPT_MAX)
    553 #define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER  (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
     586#define CPU_INTERRUPT_NUMBER_OF_VECTORS     (PPC_INTERRUPT_MAX)
     587#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (PPC_INTERRUPT_MAX - 1)
    554588
    555589/*
     
    610644/*
    611645 *  Disable all interrupts for an RTEMS critical section.  The previous
    612  *  level is returned in _level.
     646 *  level is returned in _isr_cookie.
    613647 */
    614648
    615649#define loc_string(a,b) a " (" #b ")\n"
    616650
     651#define _CPU_MSR_Value( _msr_value ) \
     652  do { \
     653    _msr_value = 0; \
     654    asm volatile ("mfmsr %0" : "=&r" ((_msr_value)) : "0" ((_msr_value))); \
     655  } while (0)
     656
     657#define _CPU_MSR_SET( _msr_value ) \
     658{ asm volatile ("mtmsr %0" : "=&r" ((_msr_value)) : "0" ((_msr_value))); }
     659
     660#if 0
    617661#define _CPU_ISR_Disable( _isr_cookie ) \
    618   { \
     662  { register unsigned int _disable_mask = PPC_MSR_DISABLE_MASK; \
     663    _isr_cookie = 0; \
     664    asm volatile (
     665        "mfmsr %0" : \
     666        "=r" ((_isr_cookie)) : \
     667        "0" ((_isr_cookie)) \
     668    ); \
     669    asm volatile (
     670        "andc %1,%0,%1" : \
     671        "=r" ((_isr_cookie)), "=&r" ((_disable_mask)) : \
     672        "0" ((_isr_cookie)), "1" ((_disable_mask)) \
     673    ); \
     674    asm volatile (
     675        "mtmsr %1" : \
     676        "=r" ((_disable_mask)) : \
     677        "0" ((_disable_mask)) \
     678    ); \
     679  }
     680#endif
     681
     682#define _CPU_ISR_Disable( _isr_cookie ) \
     683  { register unsigned int _disable_mask = PPC_MSR_DISABLE_MASK; \
     684    _isr_cookie = 0; \
    619685    asm volatile ( \
    620686        "mfmsr %0; andc %1,%0,%1; mtmsr %1" : \
    621         "=&r" ((_isr_cookie)) : "r" ((PPC_MSR_DISABLE_MASK)) \
     687        "=&r" ((_isr_cookie)), "=&r" ((_disable_mask)) : \
     688        "0" ((_isr_cookie)), "1" ((_disable_mask)) \
    622689        ); \
    623690  }
    624691
     692
     693#define _CPU_Data_Cache_Block_Flush( _address ) \
     694  do { register void *__address = (_address); \
     695       register unsigned32 _zero = 0; \
     696       asm volatile ( "dcbf %0,%1" : \
     697                      "=r" (_zero), "=r" (__address) : \
     698                      "0" (_zero), "1" (__address) \
     699       ); \
     700  } while (0)
     701
     702
    625703/*
    626704 *  Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
    627705 *  This indicates the end of an RTEMS critical section.  The parameter
    628  *  _level is not modified.
     706 *  _isr_cookie is not modified.
    629707 */
    630708
     
    632710  { \
    633711     asm volatile ( "mtmsr %0" : \
    634                    "=&r" ((_isr_cookie)) : "0" ((_isr_cookie))); \
     712                   "=r" ((_isr_cookie)) : \
     713                   "0" ((_isr_cookie))); \
    635714  }
    636715
    637716/*
    638  *  This temporarily restores the interrupt to _level before immediately
     717 *  This temporarily restores the interrupt to _isr_cookie before immediately
    639718 *  disabling them again.  This is used to divide long RTEMS critical
    640  *  sections into two or more parts.  The parameter _level is not
    641  * modified.
     719 *  sections into two or more parts.  The parameter _isr_cookie is not
     720 *  modified.
     721 *
     722 *  NOTE:  The version being used is not very optimized but it does
     723 *         not trip a problem in gcc where the disable mask does not
     724 *         get loaded.  Check this for future (post 10/97 gcc versions.
    642725 */
    643726
    644727#define _CPU_ISR_Flash( _isr_cookie ) \
    645   { \
     728  { register unsigned int _disable_mask = PPC_MSR_DISABLE_MASK; \
    646729    asm volatile ( \
    647         "mtmsr %0; andc %1,%0,%1; mtmsr %1" : \
    648         "=r" ((_isr_cookie)) : \
    649         "r" ((PPC_MSR_DISABLE_MASK)), "0" ((_isr_cookie)) \
    650         ); \
     730      "mtmsr %0; andc %1,%0,%1; mtmsr %1" : \
     731      "=r" ((_isr_cookie)), "=r" ((_disable_mask)) : \
     732      "0" ((_isr_cookie)), "1" ((_disable_mask)) \
     733    ); \
    651734  }
    652735
     
    662745 */
    663746
    664 #define _CPU_ISR_Set_level( new_level ) \
    665   { \
    666     register unsigned32 tmp = 0; \
    667     asm volatile ( \
    668         "mfmsr %0; andc %0,%0,%1; and %2, %2, %1; or %0, %0, %2; mtmsr %0" : \
    669         "=r" ((tmp)) : \
    670         "r" ((PPC_MSR_DISABLE_MASK)), "r" ((_CPU_msrs[new_level])), "0" ((tmp)) \
    671         ); \
    672   }
    673 
     747unsigned32 _CPU_ISR_Calculate_level(
     748  unsigned32 new_level
     749);
     750
     751void _CPU_ISR_Set_level(
     752  unsigned32 new_level
     753);
     754 
    674755unsigned32 _CPU_ISR_Get_level( void );
    675756
     757void _CPU_ISR_install_raw_handler(
     758  unsigned32  vector,
     759  proc_ptr    new_handler,
     760  proc_ptr   *old_handler
     761);
     762
    676763/* end of ISR handler macros */
     764
     765/*
     766 *  Simple spin delay in microsecond units for device drivers.
     767 *  This is very dependent on the clock speed of the target.
     768 */
     769
     770#define CPU_Get_timebase_low( _value ) \
     771    asm volatile( "mftb  %0" : "=r" (_value) )
     772
     773#define delay( _microseconds ) \
     774  do { \
     775    unsigned32 start, ticks, now; \
     776    CPU_Get_timebase_low( start ) ; \
     777    ticks = (_microseconds) * Cpu_table.clicks_per_usec; \
     778    do \
     779      CPU_Get_timebase_low( now ) ; \
     780    while (now - start < ticks); \
     781  } while (0)
     782
     783#define delay_in_bus_cycles( _cycles ) \
     784  do { \
     785    unsigned32 start, now; \
     786    CPU_Get_timebase_low( start ); \
     787    do \
     788      CPU_Get_timebase_low( now ); \
     789    while (now - start < (_cycles)); \
     790  } while (0)
     791
     792
    677793
    678794/* Context handler macros */
     
    692808 *  in the context.  The state of the "general data" registers is
    693809 *  undefined at task start time.
    694  */
    695 
    696 #if PPC_ABI == PPC_ABI_POWEROPEN
    697 #define _CPU_Context_Initialize( _the_context, _stack_base, _size, \
    698                                  _isr, _entry_point, _is_fp ) \
    699   { \
    700     unsigned32 sp, *desc; \
    701     \
    702     sp = ((unsigned32)_stack_base) + (_size) - 56; \
    703     *((unsigned32 *)sp) = 0; \
    704     \
    705     desc = (unsigned32 *)_entry_point; \
    706     \
    707     (_the_context)->msr = PPC_MSR_INITIAL | \
    708       _CPU_msrs[ _isr ]; \
    709     (_the_context)->pc = desc[0]; \
    710     (_the_context)->gpr1 = sp; \
    711     (_the_context)->gpr2 = desc[1]; \
    712   }
    713 #endif
    714 #if PPC_ABI == PPC_ABI_SVR4
    715 #define _CPU_Context_Initialize( _the_context, _stack_base, _size, \
    716                                  _isr, _entry_point ) \
    717   { \
    718     unsigned32 sp, r13; \
    719     \
    720     sp = ((unsigned32)_stack_base) + (_size) - 8; \
    721     *((unsigned32 *)sp) = 0; \
    722     \
    723     asm volatile ("mr %0, 13" : "=r" ((r13))); \
    724     \
    725     (_the_context->msr) = PPC_MSR_INITIAL | \
    726       _CPU_msrs[ _isr ]; \
    727     (_the_context->pc) = _entry_point; \
    728     (_the_context->gpr1) = sp; \
    729     (_the_context->gpr13) = r13; \
    730   }
    731 #endif
    732 #if PPC_ABI == PPC_ABI_EABI
    733 #define _CPU_Context_Initialize( _the_context, _stack_base, _size, \
    734                                  _isr, _entry_point ) \
    735   { \
    736     unsigned32 sp, r2, r13; \
    737     \
    738     sp = ((unsigned32)_stack_base) + (_size) - 8; \
    739     *((unsigned32 *)sp) = 0; \
    740     \
    741     asm volatile ("mr %0,2; mr %1,13" : "=r" ((r2)), "=r" ((r13))); \
    742     \
    743     (_the_context)->msr = PPC_MSR_INITIAL | \
    744       _CPU_msrs[ _isr ]; \
    745     (_the_context->pc) = _entry_point; \
    746     (_the_context->gpr1) = sp; \
    747     (_the_context->gpr2) = r2; \
    748     (_the_context->gpr13) = r13; \
    749   }
    750 #endif
     810 *
     811 *  NOTE:  Implemented as a subroutine for the SPARC port.
     812 */
     813
     814void _CPU_Context_Initialize(
     815  Context_Control  *the_context,
     816  unsigned32       *stack_base,
     817  unsigned32        size,
     818  unsigned32        new_level,
     819  void             *entry_point,
     820  boolean           is_fp
     821);
    751822
    752823/*
     
    912983void _CPU_Initialize(
    913984  rtems_cpu_table  *cpu_table,
    914   void      (*thread_dispatch)
     985  void            (*thread_dispatch)
    915986);
    916987
     
    9521023 *  _CPU_Context_restore
    9531024 *
    954  *  This routine is generally used only to restart self in an
     1025 *  This routine is generallu used only to restart self in an
    9551026 *  efficient manner.  It may simply be a label in _CPU_Context_switch.
    9561027 *
  • c/src/exec/score/cpu/powerpc/cpu_asm.s

    ra34ab1b2 r993e1b5  
    2222 *  Derived from c/src/exec/cpu/no_cpu/cpu_asm.c:
    2323 *
    24  *  COPYRIGHT (c) 1989-1998.
     24 *  COPYRIGHT (c) 1989-1997.
    2525 *  On-Line Applications Research Corporation (OAR).
    2626 *  Copyright assigned to U.S. Government, 1994.
    2727 *
    28  *  The license and distribution terms for this file may be
    29  *  found in the file LICENSE in this distribution or at
     28 *  The license and distribution terms for this file may in
     29 *  the file LICENSE in this distribution or at
    3030 *  http://www.OARcorp.com/rtems/license.html.
    3131 *
     
    175175       
    176176        /* _CPU_IRQ_info offsets */
     177
    177178        /* These must be in this order */
    178179        .set    Nest_level, 0
     
    193194#endif
    194195        .set    Signal, Switch_necessary + 4
    195 
     196        .set    msr_initial, Signal + 4
     197       
    196198        BEGIN_CODE
    197199/*
     
    454456        li      r5, 16
    455457        addi    r3,r3,-4
    456         dcbz    r5, r3
     458#if ( PPC_USE_DATA_CACHE )
     459        dcbz    r5, r3
     460#endif
    457461        stw     r1, GP_1+4(r3)
    458462        stw     r2, GP_2+4(r3)
    459463#if (PPC_USE_MULTIPLE == 1)
    460464        addi    r3, r3, GP_14+4
    461         dcbz    r5, r3
     465#if ( PPC_USE_DATA_CACHE )
     466        dcbz    r5, r3
     467#endif
     468
    462469        addi    r3, r3, GP_18-GP_14
    463         dcbz    r5, r3
     470#if ( PPC_USE_DATA_CACHE )
     471        dcbz    r5, r3
     472#endif
    464473        addi    r3, r3, GP_22-GP_18
    465         dcbz    r5, r3
     474#if ( PPC_USE_DATA_CACHE )
     475        dcbz    r5, r3
     476#endif
    466477        addi    r3, r3, GP_26-GP_22
    467         dcbz    r5, r3
     478#if ( PPC_USE_DATA_CACHE )
     479        dcbz    r5, r3
     480#endif
    468481        stmw    r13, GP_13-GP_26(r3)
    469482#else
    470483        stw     r13, GP_13+4(r3)
    471484        stwu    r14, GP_14+4(r3)
    472         dcbz    r5, r3
     485#if ( PPC_USE_DATA_CACHE )
     486        dcbz    r5, r3
     487#endif
    473488        stw     r15, GP_15-GP_14(r3)
    474489        stw     r16, GP_16-GP_14(r3)
    475490        stw     r17, GP_17-GP_14(r3)
    476491        stwu    r18, GP_18-GP_14(r3)
    477         dcbz    r5, r3
     492#if ( PPC_USE_DATA_CACHE )
     493        dcbz    r5, r3
     494#endif
    478495        stw     r19, GP_19-GP_18(r3)
    479496        stw     r20, GP_20-GP_18(r3)
    480497        stw     r21, GP_21-GP_18(r3)
    481498        stwu    r22, GP_22-GP_18(r3)
    482         dcbz    r5, r3
     499#if ( PPC_USE_DATA_CACHE )
     500        dcbz    r5, r3
     501#endif
    483502        stw     r23, GP_23-GP_22(r3)
    484503        stw     r24, GP_24-GP_22(r3)
    485504        stw     r25, GP_25-GP_22(r3)
    486505        stwu    r26, GP_26-GP_22(r3)
    487         dcbz    r5, r3
     506#if ( PPC_USE_DATA_CACHE )
     507        dcbz    r5, r3
     508#endif
    488509        stw     r27, GP_27-GP_26(r3)
    489510        stw     r28, GP_28-GP_26(r3)
     
    492513        stw     r31, GP_31-GP_26(r3)
    493514#endif
     515#if ( PPC_USE_DATA_CACHE )
    494516        dcbt    r0, r4
     517#endif
    495518        mfcr    r6
    496519        stw     r6, GP_CR-GP_26(r3)
     
    500523        stw     r8, GP_MSR-GP_26(r3)
    501524       
    502         dcbt    r5, r4
     525#if ( PPC_USE_DATA_CACHE )
     526        dcbt    r5, r4
     527#endif
    503528        lwz     r1, GP_1(r4)
    504529        lwz     r2, GP_2(r4)
    505530#if (PPC_USE_MULTIPLE == 1)
    506531        addi    r4, r4, GP_15
    507         dcbt    r5, r4
     532#if ( PPC_USE_DATA_CACHE )
     533        dcbt    r5, r4
     534#endif
    508535        addi    r4, r4, GP_19-GP_15
    509         dcbt    r5, r4
     536#if ( PPC_USE_DATA_CACHE )
     537        dcbt    r5, r4
     538#endif
    510539        addi    r4, r4, GP_23-GP_19
    511         dcbt    r5, r4
     540#if ( PPC_USE_DATA_CACHE )
     541        dcbt    r5, r4
     542#endif
    512543        addi    r4, r4, GP_27-GP_23
    513         dcbt    r5, r4
     544#if ( PPC_USE_DATA_CACHE )
     545        dcbt    r5, r4
     546#endif
    514547        lmw     r13, GP_13-GP_27(r4)
    515548#else
     
    517550        lwz     r14, GP_14(r4)
    518551        lwzu    r15, GP_15(r4)
    519         dcbt    r5, r4
     552#if ( PPC_USE_DATA_CACHE )
     553        dcbt    r5, r4
     554#endif
    520555        lwz     r16, GP_16-GP_15(r4)
    521556        lwz     r17, GP_17-GP_15(r4)
    522557        lwz     r18, GP_18-GP_15(r4)
    523558        lwzu    r19, GP_19-GP_15(r4)
    524         dcbt    r5, r4
     559#if ( PPC_USE_DATA_CACHE )
     560        dcbt    r5, r4
     561#endif
    525562        lwz     r20, GP_20-GP_19(r4)
    526563        lwz     r21, GP_21-GP_19(r4)
    527564        lwz     r22, GP_22-GP_19(r4)
    528565        lwzu    r23, GP_23-GP_19(r4)
    529         dcbt    r5, r4
     566#if ( PPC_USE_DATA_CACHE )
     567        dcbt    r5, r4
     568#endif
    530569        lwz     r24, GP_24-GP_23(r4)
    531570        lwz     r25, GP_25-GP_23(r4)
    532571        lwz     r26, GP_26-GP_23(r4)
    533572        lwzu    r27, GP_27-GP_23(r4)
    534         dcbt    r5, r4
     573#if ( PPC_USE_DATA_CACHE )
     574        dcbt    r5, r4
     575#endif
    535576        lwz     r28, GP_28-GP_27(r4)
    536577        lwz     r29, GP_29-GP_27(r4)
     
    549590        li      r5, 32
    550591        addi    r3,r3,-4
    551         dcbz    r5, r3
     592#if ( PPC_USE_DATA_CACHE )
     593        dcbz    r5, r3
     594#endif
    552595        stw     r1, GP_1+4(r3)
    553596        stw     r2, GP_2+4(r3)
    554597#if (PPC_USE_MULTIPLE == 1)
    555598        addi    r3, r3, GP_18+4
    556         dcbz    r5, r3
     599#if ( PPC_USE_DATA_CACHE )
     600        dcbz    r5, r3
     601#endif
    557602        stmw    r13, GP_13-GP_18(r3)
    558603#else
     
    563608        stw     r17, GP_17+4(r3)
    564609        stwu    r18, GP_18+4(r3)
    565         dcbz    r5, r3
     610#if ( PPC_USE_DATA_CACHE )
     611        dcbz    r5, r3
     612#endif
    566613        stw     r19, GP_19-GP_18(r3)
    567614        stw     r20, GP_20-GP_18(r3)
     
    578625        stw     r31, GP_31-GP_18(r3)
    579626#endif
     627#if ( PPC_USE_DATA_CACHE )
    580628        dcbt    r0, r4
     629#endif
    581630        mfcr    r6
    582631        stw     r6, GP_CR-GP_18(r3)
     
    586635        stw     r8, GP_MSR-GP_18(r3)
    587636
    588         dcbt    r5, r4
     637#if ( PPC_USE_DATA_CACHE )
     638        dcbt    r5, r4
     639#endif
    589640        lwz     r1, GP_1(r4)
    590641        lwz     r2, GP_2(r4)
    591642#if (PPC_USE_MULTIPLE == 1)
    592643        addi    r4, r4, GP_19
    593         dcbt    r5, r4
     644#if ( PPC_USE_DATA_CACHE )
     645        dcbt    r5, r4
     646#endif
    594647        lmw     r13, GP_13-GP_19(r4)
    595648#else
     
    601654        lwz     r18, GP_18(r4)
    602655        lwzu    r19, GP_19(r4)
    603         dcbt    r5, r4
     656#if ( PPC_USE_DATA_CACHE )
     657        dcbt    r5, r4
     658#endif
    604659        lwz     r20, GP_20-GP_19(r4)
    605660        lwz     r21, GP_21-GP_19(r4)
     
    627682 *  _CPU_Context_restore
    628683 *
    629  *  This routine is generally used only to restart self in an
     684 *  This routine is generallu used only to restart self in an
    630685 *  efficient manner.  It may simply be a label in _CPU_Context_switch.
    631686 *
     
    698753PROC (_ISR_Handler):
    699754#define LABEL(x)        x
     755/*  XXX ??
    700756#define MTSAVE(x)       mtspr   sprg0, x
    701757#define MFSAVE(x)       mfspr   x, sprg0
     758*/
    702759#define MTPC(x)         mtspr   srr0, x
    703760#define MFPC(x)         mfspr   x, srr0
    704761#define MTMSR(x)        mtspr   srr1, x
    705762#define MFMSR(x)        mfspr   x, srr1
     763
    706764        #include        "irq_stub.s"
    707765        rfi
     
    725783#undef  MFMSR
    726784#define LABEL(x)        x##_C
     785/* XXX??
    727786#define MTSAVE(x)       mtspr   sprg1, x
    728787#define MFSAVE(x)       mfspr   x, sprg1
     788*/
    729789#define MTPC(x)         mtspr   srr2, x
    730790#define MFPC(x)         mfspr   x, srr2
  • c/src/exec/score/cpu/powerpc/irq_stub.s

    ra34ab1b2 r993e1b5  
    1 /*  irq_stub.s  1.1 - 95/12/04
    2  *
     1/*
    32 *  This file contains the interrupt handler assembly code for the PowerPC
    43 *  implementation of RTEMS.  It is #included from cpu_asm.s.
     
    2827 *
    2928 */
    30         /* Finish off the interrupt frame */
     29        PUBLIC_VAR (_CPU_IRQ_info )
     30
     31        /* Finish off the interrupt frame */
    3132        stw     r2, IP_2(r1)
    3233        stw     r3, IP_3(r1)
     
    4950        MFMSR   (r10)
    5051        /* Establish addressing */
    51         mfspr   r11, sprg3
     52#if (PPC_USE_SPRG)
     53        mfspr   r11, sprg3
     54#else
     55        lis     r11,_CPU_IRQ_info@ha
     56        addi    r11,r11,_CPU_IRQ_info@l
     57#endif
    5258        dcbt    r0, r11
    5359        stw     r5, IP_CR(r1)
     
    7379   */
    7480        /* Switch stacks, here we must prevent ALL interrupts */
    75         mfmsr   r5
    76         mfspr   r6, sprg2
     81#if (PPC_USE_SPRG)
     82        mfmsr   r5         
     83        mfspr   r6, sprg2   
     84#else   
     85        lwz     r6,msr_initial(r11)
     86        lis     r5,~PPC_MSR_DISABLE_MASK@ha
     87        ori     r5,r5,~PPC_MSR_DISABLE_MASK@l
     88        and     r6,r6,r5
     89        mfmsr   r5         
     90#endif
    7791        mtmsr   r6
    7892        cmpwi   r30, 0
     
    97111        addi    r31,r31,1
    98112        stw     r31, 0(r29)
     113/* SCE 980217
     114 *
     115 * We need address translation ON when we call our ISR routine
     116
    99117        mtmsr   r5
     118
     119 */
     120
    100121  /*
    101122   *  (*_ISR_Vector_table[ vector ])( vector );
     
    110131        lwz     r2, Default_r2(r11)
    111132        mtlr    r4
    112         lwz     r2, 0(r2)
     133        #lwz    r2, 0(r2)
    113134#endif
    114135#if (PPC_ABI == PPC_ABI_SVR4 || PPC_ABI == PPC_ABI_EABI)
     
    116137        lwz     r2, Default_r2(r11)
    117138        lwz     r13, Default_r13(r11)
    118         lwz     r2, 0(r2)
    119         lwz     r13, 0(r13)
     139        #lwz    r2, 0(r2)
     140        #lwz    r13, 0(r13)
    120141#endif
    121142        mr      r4,r1
     
    125146
    126147        /*      We must re-disable the interrupts */
     148#if (PPC_USE_SPRG)
    127149        mfspr   r11, sprg3
    128         mfspr   r0, sprg2
     150        mfspr   r0, sprg2 
     151#else
     152        lis     r11,_CPU_IRQ_info@ha
     153        addi    r11,r11,_CPU_IRQ_info@l
     154        lwz     r0,msr_initial(r11)
     155        lis     r30,~PPC_MSR_DISABLE_MASK@ha
     156        ori     r30,r30,~PPC_MSR_DISABLE_MASK@l
     157        and     r0,r0,r30
     158#endif
    129159        mtmsr   r0
    130160        lwz     r30, 0(r28)
     
    192222   */
    193223        /* Re-disable IRQs */
     224#if (PPC_USE_SPRG)
    194225        mfspr   r0, sprg2
     226#else
     227        lis     r11,_CPU_IRQ_info@ha
     228        addi    r11,r11,_CPU_IRQ_info@l
     229        lwz     r0,msr_initial(r11)
     230        lis     r5,~PPC_MSR_DISABLE_MASK@ha
     231        ori     r5,r5,~PPC_MSR_DISABLE_MASK@l
     232        and     r0,r0,r5
     233#endif
    195234        mtmsr   r0
     235       
    196236  /*
    197237   *  easy_exit:
  • c/src/exec/score/cpu/powerpc/ppc.h

    ra34ab1b2 r993e1b5  
    2121 *  Derived from c/src/exec/cpu/no_cpu/no_cpu.h:
    2222 *
    23  *  COPYRIGHT (c) 1989-1998.
     23 *  COPYRIGHT (c) 1989-1997.
    2424 *  On-Line Applications Research Corporation (OAR).
    2525 *
    26  *  The license and distribution terms for this file may be
    27  *  found in the file LICENSE in this distribution or at
     26 *  The license and distribution terms for this file may in
     27 *  the file LICENSE in this distribution or at
    2828 *  http://www.OARcorp.com/rtems/license.html.
    2929 *
     
    3535 */
    3636
     37
    3738#ifndef _INCLUDE_PPC_h
    3839#define _INCLUDE_PPC_h
     
    4344
    4445/*
     46 *  Define the name of the CPU family.
     47 */
     48
     49#define CPU_NAME "PowerPC"
     50
     51/*
    4552 *  This file contains the information required to build
    46  *  RTEMS for a particular member of the "no cpu"
    47  *  family when executing in protected mode.  It does
     53 *  RTEMS for a particular member of the PowerPC family.  It does
    4854 *  this by setting variables to indicate which implementation
    4955 *  dependent features are present in a particular member
    5056 *  of the family.
    51  */
    52  
     57 *
     58 *  The following architectural feature definitions are defaulted
     59 *  unless specifically set by the model definition:
     60 *
     61 *    + PPC_DEBUG_MODEL          - PPC_DEBUG_MODEL_STANDARD
     62 *    + PPC_INTERRUPT_MAX        - 16
     63 *    + PPC_CACHE_ALIGNMENT      - 32
     64 *    + PPC_LOW_POWER_MODE       - PPC_LOW_POWER_MODE_NONE
     65 *    + PPC_HAS_EXCEPTION_PREFIX - 1
     66 *    + PPC_HAS_FPU              - 1
     67 *    + PPC_HAS_DOUBLE           - 1 if PPC_HAS_FPU,
     68 *                               - 0 otherwise
     69 *    + PPC_USE_MULTIPLE         - 0
     70 */
     71 
     72/*
     73 *  Define the debugging assistance models found in the PPC family.
     74 *
     75 *  Standard:         single step and branch trace
     76 *  Single Step Only: single step only
     77 *  IBM 4xx:          debug exception
     78 */
     79
     80#define PPC_DEBUG_MODEL_STANDARD         1
     81#define PPC_DEBUG_MODEL_SINGLE_STEP_ONLY 2
     82#define PPC_DEBUG_MODEL_IBM4xx           3
     83
     84/*
     85 *  Define the low power mode models
     86 *
     87 *  Standard:   as defined for 603e
     88 *  Nap Mode:   nap mode only (604)
     89 *  XXX 403GB, 603, 603e, 604, 821
     90 */
     91
     92#define PPC_LOW_POWER_MODE_NONE      0
     93#define PPC_LOW_POWER_MODE_STANDARD  1
     94
    5395#if defined(ppc403)
    54  
    55 #define CPU_MODEL_NAME  "PowerPC 403"
    56 
    57 #define PPC_ALIGNMENT           4
     96/*
     97 *  IBM 403
     98 *
     99 *  Developed for 403GA.  Book checked for 403GB.
     100 *
     101 *  Does not have user mode.
     102 */
     103 
     104#define CPU_MODEL_NAME "PowerPC 403"
     105#define PPC_ALIGNMENT           4 
    58106#define PPC_CACHE_ALIGNMENT     16
    59 #define PPC_CACHE_ALIGN_POWER   4
    60 #define PPC_INTERRUPT_MAX       16
     107#define PPC_HAS_RFCI            1
    61108#define PPC_HAS_FPU             0
    62 #define PPC_HAS_DOUBLE          0
    63 #define PPC_HAS_RFCI            1
    64 #define PPC_MSR_DISABLE_MASK    0x00029200
    65 #define PPC_MSR_INITIAL         0x00000000
    66 #define PPC_INIT_FPSCR          0x00000000
    67109#define PPC_USE_MULTIPLE        1
    68110#define PPC_I_CACHE             2048
    69111#define PPC_D_CACHE             1024
    70112
    71 #define PPC_MSR_0               0x00029200
    72 #define PPC_MSR_1               0x00021200
    73 #define PPC_MSR_2               0x00021000
    74 #define PPC_MSR_3               0x00000000
     113#define PPC_DEBUG_MODEL          PPC_DEBUG_MODEL_IBM4xx
     114#define PPC_HAS_EXCEPTION_PREFIX 0
    75115
    76116#elif defined(ppc601)
     117/*
     118 *  Submitted with original port -- book checked only.
     119 */
    77120 
    78121#define CPU_MODEL_NAME  "PowerPC 601"
    79122
    80123#define PPC_ALIGNMENT           8
    81 #define PPC_CACHE_ALIGNMENT     32
    82 #define PPC_CACHE_ALIGN_POWER   5
    83 #define PPC_INTERRUPT_MAX       16
    84 #define PPC_HAS_FPU             1
    85 #define PPC_HAS_DOUBLE          1
    86 #define PPC_HAS_RFCI            0
    87 #define PPC_MSR_DISABLE_MASK    0x00009900
    88 #define PPC_MSR_INITIAL         0x00002000
    89 #define PPC_INIT_FPSCR          0x000000f8
    90124#define PPC_USE_MULTIPLE        1
    91125#define PPC_I_CACHE             0
    92126#define PPC_D_CACHE             32768
    93127
    94 #define PPC_MSR_0               0x00009900
    95 #define PPC_MSR_1               0x00001000
    96 #define PPC_MSR_2               0x00001000
    97 #define PPC_MSR_3               0x00000000
    98  
     128#define PPC_DEBUG_MODEL PPC_DEBUG_MODEL_SINGLE_STEP_ONLY
     129
    99130#elif defined(ppc602)
     131/*
     132 *  Submitted with original port -- book checked only.
     133 */
    100134 
    101135#define CPU_MODEL_NAME  "PowerPC 602"
    102136
    103137#define PPC_ALIGNMENT           4
    104 #define PPC_CACHE_ALIGNMENT     32
    105 #define PPC_CACHE_ALIGN_POWER   5
    106 #define PPC_INTERRUPT_MAX       16
    107 #define PPC_HAS_FPU             1
    108138#define PPC_HAS_DOUBLE          0
    109 #define PPC_HAS_RFCI            0
    110 #define PPC_MSR_DISABLE_MASK   
    111 #define PPC_MSR_INITIAL         
    112 #define PPC_INIT_FPSCR         
    113 #define PPC_USE_MULTIPLE        0
    114139#define PPC_I_CACHE             4096
    115140#define PPC_D_CACHE             4096
    116141
    117142#elif defined(ppc603)
     143/*
     144 *  Submitted with original port -- book checked only.
     145 */
    118146 
    119147#define CPU_MODEL_NAME  "PowerPC 603"
    120148
    121149#define PPC_ALIGNMENT           8
    122 #define PPC_CACHE_ALIGNMENT     32
    123 #define PPC_CACHE_ALIGN_POWER   5
    124 #define PPC_INTERRUPT_MAX       16
    125 #define PPC_HAS_FPU             1
    126 #define PPC_HAS_DOUBLE          1
    127 #define PPC_HAS_RFCI            0
    128 #define PPC_MSR_DISABLE_MASK    0x00009900
    129 #define PPC_MSR_INITIAL         0x00002000
    130 #define PPC_INIT_FPSCR          0x000000f8
    131 #define PPC_USE_MULTIPLE        0
    132150#define PPC_I_CACHE             8192
    133151#define PPC_D_CACHE             8192
    134152
    135 #define PPC_MSR_0               0x00009900
    136 #define PPC_MSR_1               0x00001000
    137 #define PPC_MSR_2               0x00001000
    138 #define PPC_MSR_3               0x00000000
    139 
    140153#elif defined(ppc603e)
    141154 
    142155#define CPU_MODEL_NAME  "PowerPC 603e"
     156/*
     157 *  Submitted with original port.
     158 *
     159 *  Known to work on real hardware.
     160 */
    143161
    144162#define PPC_ALIGNMENT           8
    145 #define PPC_CACHE_ALIGNMENT     32
    146 #define PPC_CACHE_ALIGN_POWER   5
    147 #define PPC_INTERRUPT_MAX       16
    148 #define PPC_HAS_FPU             1
    149 #define PPC_HAS_DOUBLE          1
    150 #define PPC_HAS_RFCI            0
    151 #define PPC_MSR_DISABLE_MASK    0x00009900
    152 #define PPC_MSR_INITIAL         0x00002000
    153 #define PPC_INIT_FPSCR          0x000000f8
    154 #define PPC_USE_MULTIPLE        0
    155163#define PPC_I_CACHE             16384
    156164#define PPC_D_CACHE             16384
    157165
    158 #define PPC_MSR_0               0x00009900
    159 #define PPC_MSR_1               0x00001000
    160 #define PPC_MSR_2               0x00001000
    161 #define PPC_MSR_3               0x00000000
     166#define PPC_LOW_POWER_MODE PPC_LOW_POWER_MODE_STANDARD
    162167
    163168#elif defined(ppc604)
     169/*
     170 *  Submitted with original port -- book checked only.
     171 */
    164172 
    165173#define CPU_MODEL_NAME  "PowerPC 604"
    166174
    167175#define PPC_ALIGNMENT           8
    168 #define PPC_CACHE_ALIGNMENT     32
    169 #define PPC_CACHE_ALIGN_POWER   5
    170 #define PPC_INTERRUPT_MAX       16
    171 #define PPC_HAS_FPU             1
    172 #define PPC_HAS_DOUBLE          1
    173 #define PPC_HAS_RFCI            0
    174 #define PPC_MSR_DISABLE_MASK    0x00009900
    175 #define PPC_MSR_INITIAL         0x00002000
    176 #define PPC_INIT_FPSCR          0x000000f8
    177 #define PPC_USE_MULTIPLE        0
    178176#define PPC_I_CACHE             16384
    179177#define PPC_D_CACHE             16384
    180178 
    181 #define PPC_MSR_0               0x00009900
    182 #define PPC_MSR_1               0x00001000
    183 #define PPC_MSR_2               0x00001000
    184 #define PPC_MSR_3               0x00000000
    185 
    186179#else
    187180 
     
    192185/*
    193186 *  Application binary interfaces.
     187 *
    194188 *  PPC_ABI MUST be defined as one of these.
    195189 *  Only PPC_ABI_POWEROPEN is currently fully supported.
     
    238232 *  Assemblers.
    239233 *  PPC_ASM MUST be defined as one of these.
    240  *  Only PPC_ABI_ELF is currently fully supported.
    241  */
    242 /*
    243  *  ELF assembler. Currently used for all ABIs.
    244  */
    245 #define PPC_ASM_ELF             0
    246 /*
    247  *  XCOFF assembler, may be needed for PowerOpen ABI.
    248  */
    249 #define PPC_ASM_XCOFF           1
    250 
    251 /*
    252  *  Define the name of the CPU family.
    253  */
    254 
    255 #define CPU_NAME "PowerPC"
    256 
    257 /*
    258  *  Interrupt vectors.
    259  */
    260 /* Machine check */
    261 #define PPC_IRQ_MCHECK          0
    262 /* Protection violation */
    263 #define PPC_IRQ_PROTECT         1
    264 /* External interrupt */
    265 #define PPC_IRQ_EXTERNAL        2
    266 /* Program exception */
    267 #define PPC_IRQ_PROGRAM         3
    268 /* System call */
    269 #define PPC_IRQ_SCALL           4
    270 /* Floating point unavailable */
    271 #define PPC_IRQ_NOFP            5
    272 /* Program interval timer */
    273 #define PPC_IRQ_PIT             6
    274 /* Fixed interval timer */
    275 #define PPC_IRQ_FIT             7
    276 /* Critical interrupt pin */
    277 #define PPC_IRQ_CRIT            8
    278 /* Watchdog timer */
    279 #define PPC_IRQ_WATCHDOG        9
    280 /* Debug exceptions */
    281 #define PPC_IRQ_DEBUG           10
     234 *
     235 *  PPC_ASM_ELF:   ELF assembler. Currently used for all ABIs.
     236 *  PPC_ASM_XCOFF: XCOFF assembler. May be needed for PowerOpen ABI.
     237 *
     238 *  NOTE: Only PPC_ABI_ELF is currently fully supported.
     239 */
     240
     241#define PPC_ASM_ELF   0
     242#define PPC_ASM_XCOFF 1
     243
     244/*
     245 *  Use the default debug scheme defined in the architectural specification
     246 *  if another model has not been specified.
     247 */
     248
     249#ifndef PPC_DEBUG_MODEL
     250#define PPC_DEBUG_MODEL PPC_DEBUG_MODEL_STANDARD
     251#endif
     252
     253/*
     254 *  If the maximum number of exception sources has not been defined,
     255 *  then default it to 16.
     256 */
     257
     258#ifndef PPC_INTERRUPT_MAX
     259#define PPC_INTERRUPT_MAX       16
     260#endif
     261
     262/*
     263 *  Unless specified otherwise, the cache line size is defaulted to 32.
     264 *
     265 *  The derive the power of 2 the cache line is.
     266 */
     267
     268#ifndef PPC_CACHE_ALIGNMENT
     269#define PPC_CACHE_ALIGNMENT 32
     270#endif
     271
     272#if (PPC_CACHE_ALIGNMENT == 16)
     273#define PPC_CACHE_ALIGN_POWER 4
     274#elif (PPC_CACHE_ALIGNMENT == 32)
     275#define PPC_CACHE_ALIGN_POWER 5
     276#else
     277#error "Undefined power of 2 for PPC_CACHE_ALIGNMENT"
     278#endif
     279
     280/*
     281 *  Unless otherwise specified, assume the model has an IP/EP bit to
     282 *  set the exception address prefix.
     283 */
     284
     285#ifndef PPC_HAS_EXCEPTION_PREFIX
     286#define PPC_HAS_EXCEPTION_PREFIX 1
     287#endif
     288
     289/*
     290 *  If no low power mode model was specified, then assume there is none.
     291 */
     292
     293#ifndef PPC_LOW_POWER_MODE
     294#define PPC_LOW_POWER_MODE PPC_LOW_POWER_MODE_NONE
     295#endif
     296
     297/*
     298 *  Unless specified above, then assume the model has FP support.
     299 */
     300
     301#ifndef PPC_HAS_FPU
     302#define PPC_HAS_FPU 1
     303#endif
     304
     305/*
     306 *  Unless specified above, If the model has FP support, it is assumed to
     307 *  support doubles (8-byte floating point numbers).
     308 *
     309 *  If the model does NOT have FP support, then the model does
     310 *  NOT have double length FP registers.
     311 */
     312
     313#ifndef PPC_HAS_DOUBLE
     314#if (PPC_HAS_FPU)
     315#define PPC_HAS_DOUBLE 1
     316#else
     317#define PPC_HAS_DOUBLE 0
     318#endif
     319#endif
     320
     321/*
     322 *  Unless specified above, then assume the model does NOT have critical
     323 *  interrupt support.
     324 */
     325
     326#ifndef PPC_HAS_RFCI
     327#define PPC_HAS_RFCI 0
     328#endif
     329
     330/*
     331 *  Unless specified above, do not use the load/store multiple instructions
     332 *  in a context switch.
     333 */
     334
     335#ifndef PPC_USE_MULTIPLE
     336#define PPC_USE_MULTIPLE 0
     337#endif
    282338
    283339/*
     
    289345 */
    290346
     347/*
     348 *  Base Interrupt vectors supported on all models.
     349 */
     350#define PPC_IRQ_SYSTEM_RESET     0 /* 0x00100 - System reset.              */
     351#define PPC_IRQ_MCHECK           1 /* 0x00200 - Machine check              */
     352#define PPC_IRQ_PROTECT          2 /* 0x00300 - Protection violation       */
     353#define PPC_IRQ_ISI              3 /* 0x00400 - Instruction Fetch error    */
     354#define PPC_IRQ_EXTERNAL         4 /* 0x00500 - External interrupt         */
     355#define PPC_IRQ_ALIGNMENT        5 /* 0X00600 - Alignment exception        */
     356#define PPC_IRQ_PROGRAM          6 /* 0x00700 - Program exception          */
     357#define PPC_IRQ_NOFP             7 /* 0x00800 - Floating point unavailable */
     358#define PPC_IRQ_DECREMENTER      8 /* 0x00900 - Decrementer interrupt      */
     359#define PPC_IRQ_RESERVED_A       9 /* 0x00a00 - Implementation Reserved    */
     360#define PPC_IRQ_RESERVED_B      10 /* 0x00a00 - Implementation Reserved    */
     361#define PPC_IRQ_SCALL           11 /* 0x00c00 - System call                */
     362#define PPC_IRQ_TRACE           12 /* 0x00d00 - Trace Exception            */
     363#define PPC_IRQ_FP_ASST         13 /* ox00e00 - Floating point assist      */
     364#define PPC_STD_IRQ_LAST        PPC_IRQ_FP_ASST
     365
     366#define PPC_IRQ_FIRST           PPC_IRQ_SYSTEM_RESET
     367
     368#if defined(ppc403)
     369                                 
     370#define PPC_IRQ_CRIT     PPC_IRQ_SYSTEM_RESET /*0x00100- Critical int. pin */
     371#define PPC_IRQ_PIT      (PPC_STD_IRQ_LAST+1) /*0x01000- Pgm interval timer*/
     372#define PPC_IRQ_FIT      (PPC_STD_IRQ_LAST+2) /*0x01010- Fixed int. timer  */
     373#define PPC_IRQ_WATCHDOG (PPC_STD_IRQ_LAST+3) /*0x01020- Watchdog timer    */
     374#define PPC_IRQ_DEBUG    (PPC_STD_IRQ_LAST+4) /*0x02000- Debug exceptions  */
     375#define PPC_IRQ_LAST     PPC_IRQ_DEBUG   
     376
     377#elif defined(ppc601)
     378#define PPC_IRQ_TRACE    (PPC_STD_IRQ_LAST+1) /*0x02000-Run/Trace Exception*/
     379#define PPC_IRQ_LAST     PPC_IRQ_TRACE       
     380
     381#elif defined(ppc602)
     382#define PPC_IRQ_LAST     (PPC_STD_IRQ_LAST)
     383
     384#elif defined(ppc603)
     385#define PPC_IRQ_TRANS_MISS (PPC_STD_IRQ_LAST+1) /*0x1000-Ins Translation Miss*/
     386#define PPC_IRQ_DATA_LOAD  (PPC_STD_IRQ_LAST+2) /*0x1100-Data Load Trans Miss*/
     387#define PPC_IRQ_DATA_STORE (PPC_STD_IRQ_LAST+3) /*0x1200-Data Store Miss     */
     388#define PPC_IRQ_ADDR_BRK   (PPC_STD_IRQ_LAST+4) /*0x1300-Instruction Bkpoint */
     389#define PPC_IRQ_SYS_MGT    (PPC_STD_IRQ_LAST+5) /*0x1400-System Management   */
     390#define PPC_IRQ_LAST       PPC_IRQ_SYS_MGT   
     391
     392#elif defined(ppc603e)
     393#define PPC_TLB_INST_MISS  (PPC_STD_IRQ_LAST+1) /*0x1000-Instruction TLB Miss*/
     394#define PPC_TLB_LOAD_MISS  (PPC_STD_IRQ_LAST+2) /*0x1100-TLB miss on load  */
     395#define PPC_TLB_STORE_MISS (PPC_STD_IRQ_LAST+3) /*0x1200-TLB Miss on store */
     396#define PPC_IRQ_ADDRBRK    (PPC_STD_IRQ_LAST+4) /*0x1300-Instruct addr break */
     397#define PPC_IRQ_SYS_MGT    (PPC_STD_IRQ_LAST+5) /*0x1400-System Management   */
     398#define PPC_IRQ_LAST       PPC_IRQ_SYS_MGT   
     399
     400
     401#elif defined(ppc604)
     402#define PPC_IRQ_ADDR_BRK (PPC_STD_IRQ_LAST+1) /*0x1300- Inst. addr break  */
     403#define PPC_IRQ_SYS_MGT  (PPC_STD_IRQ_LAST+2) /*0x1400- System Management */
     404#define PPC_IRQ_LAST     PPC604_IRQ_SYS_MGT 
     405
     406#endif
     407
     408/*
     409 *  Machine Status Register (MSR) Constants Used by RTEMS
     410 */
     411
     412/*
     413 *  Some PPC model manuals refer to the Exception Prefix (EP) bit as
     414 *  IP for no apparent reason.
     415 */
     416
     417#define PPC_MSR_RI       0x000000002 /* bit 30 - recoverable exception */
     418#define PPC_MSR_DR       0x000000010 /* bit 27 - data address translation */
     419#define PPC_MSR_IR       0x000000020 /* bit 26 - instruction addr translation*/
     420
     421#if (PPC_HAS_EXCEPTION_PREFIX)
     422#define PPC_MSR_EP       0x000000040 /* bit 25 - exception prefix */
     423#else
     424#define PPC_MSR_EP       0x000000000 /* bit 25 - exception prefix */
     425#endif
     426
     427#if (PPC_HAS_FPU)
     428#define PPC_MSR_FP       0x000002000 /* bit 18 - floating point enable */
     429#else
     430#define PPC_MSR_FP       0x000000000 /* bit 18 - floating point enable */
     431#endif
     432
     433#if (PPC_LOW_POWER_MODE == PPC_LOW_POWER_MODE_NONE)
     434#define PPC_MSR_POW      0x000000000 /* bit 13 - power management enable */
     435#else
     436#define PPC_MSR_POW      0x000040000 /* bit 13 - power management enable */
     437#endif
     438
     439/*
     440 *  Interrupt/exception MSR bits set as defined on p. 2-20 in "The Programming
     441 *  Environments" and the manuals for various PPC models.
     442 */
     443
     444#if (PPC_DEBUG_MODEL == PPC_DEBUG_MODEL_STANDARD)
     445#define PPC_MSR_DE       0x000000000 /* bit 22 - debug exception enable */
     446#define PPC_MSR_BE       0x000000200 /* bit 22 - branch trace enable */
     447#define PPC_MSR_SE       0x000000400 /* bit 21 - single step trace enable */
     448#elif (PPC_DEBUG_MODEL == PPC_DEBUG_MODEL_SINGLE_STEP_ONLY)
     449#define PPC_MSR_DE       0x000000000 /* bit 22 - debug exception enable */
     450#define PPC_MSR_BE       0x000000200 /* bit 22 - branch trace enable */
     451#define PPC_MSR_SE       0x000000000 /* bit 21 - single step trace enable */
     452#elif (PPC_DEBUG_MODEL == PPC_DEBUG_MODEL_IBM4xx)
     453#define PPC_MSR_DE       0x000000200 /* bit 22 - debug exception enable */
     454#define PPC_MSR_BE       0x000000000 /* bit 22 - branch trace enable */
     455#define PPC_MSR_SE       0x000000000 /* bit 21 - single step trace enable */
     456#else
     457#error "MSR constants -- unknown PPC_DEBUG_MODEL!!"
     458#endif
     459
     460#define PPC_MSR_ME       0x000001000 /* bit 19 - machine check enable */
     461#define PPC_MSR_EE       0x000008000 /* bit 16 - external interrupt enable */
     462
     463#if (PPC_HAS_RFCI)
     464#define PPC_MSR_CE       0x000020000 /* bit 14 - critical interrupt enable */
     465#else
     466#define PPC_MSR_CE       0x000000000 /* bit 14 - critical interrupt enable */
     467#endif
     468
     469#define PPC_MSR_DISABLE_MASK (PPC_MSR_ME|PPC_MSR_EE|PPC_MSR_CE)
     470
     471/*
     472 *  Initial value for the FPSCR register
     473 */
     474
     475#define PPC_INIT_FPSCR          0x000000f8
     476
    291477#ifdef __cplusplus
    292478}
     
    295481#endif /* ! _INCLUDE_PPC_h */
    296482/* end of include file */
     483
     484
  • c/src/exec/score/cpu/powerpc/ppctypes.h

    ra34ab1b2 r993e1b5  
    2121 *  Derived from c/src/exec/cpu/no_cpu/no_cputypes.h:
    2222 *
    23  *  COPYRIGHT (c) 1989-1998.
     23 *  COPYRIGHT (c) 1989-1997.
    2424 *  On-Line Applications Research Corporation (OAR).
    2525 *  Copyright assigned to U.S. Government, 1994.
    2626 *
    27  *  The license and distribution terms for this file may be
    28  *  found in the file LICENSE in this distribution or at
     27 *  The license and distribution terms for this file may in
     28 *  the file LICENSE in this distribution or at
    2929 *  http://www.OARcorp.com/rtems/license.html.
    3030 *
  • c/src/exec/score/cpu/powerpc/rtems.s

    ra34ab1b2 r993e1b5  
    2121 *  Derived from c/src/exec/cpu/no_cpu/rtems.c:
    2222 *
    23  *  COPYRIGHT (c) 1989-1998.
     23 *  COPYRIGHT (c) 1989-1997.
    2424 *  On-Line Applications Research Corporation (OAR).
    2525 *  Copyright assigned to U.S. Government, 1994.
    2626 *
    27  *  The license and distribution terms for this file may be
    28  *  found in the file LICENSE in this distribution or at
     27 *  The license and distribution terms for this file may in
     28 *  the file LICENSE in this distribution or at
    2929 *  http://www.OARcorp.com/rtems/license.html.
    3030 *
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