Changeset 9907dde in rtems


Ignore:
Timestamp:
Aug 26, 2014, 2:59:56 PM (6 years ago)
Author:
Sebastian Huber <sebastian.huber@…>
Branches:
4.11, 5, master
Children:
76386c1
Parents:
96ec8ee8
git-author:
Sebastian Huber <sebastian.huber@…> (08/26/14 14:59:56)
git-committer:
Sebastian Huber <sebastian.huber@…> (08/26/14 15:10:18)
Message:

bsp/altera-cyclone-v: Update to hwlib 13.1

This version is distributed with SoC EDS 14.0.0.200.

Location:
c/src/lib/libbsp/arm/altera-cyclone-v
Files:
1 added
15 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/arm/altera-cyclone-v/Makefile.am

    r96ec8ee8 r9907dde  
    7878
    7979# Some of the headers from hwlib need the files from socal. Install them.
     80include_bsp_socal_HEADERS += hwlib/include/socal/alt_acpidmap.h
    8081include_bsp_socal_HEADERS += hwlib/include/socal/alt_clkmgr.h
    8182include_bsp_socal_HEADERS += hwlib/include/socal/alt_gpio.h
     
    119120
    120121# for the Altera hwlib
    121 libbsp_a_CPPFLAGS += -I ${srcdir}/hwlib/include
     122libbsp_a_CPPFLAGS += -I${srcdir}/hwlib/include
    122123libbsp_a_CPPFLAGS += -std=gnu99
    123124CFLAGS += -Wno-missing-prototypes
  • c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/README.txt

    r96ec8ee8 r9907dde  
    1717HWLIB Version:
    1818--------------
    19 The files have been taken from the following hwlib versions:
    20 
    21 |========================================
    22 | Version | File
    23 |         |
    24 | 13.0SP1 | include/alt_address_space.h
    25 | 13.0SP1 | include/alt_clock_group.h
    26 | 13.0SP1 | include/alt_clock_manager.h
    27 | 13.0SP1 | include/alt_generalpurpose_io.h
    28 | 13.0SP1 | include/alt_hwlibs_ver.h
    29 | 13.1    | include/alt_i2c.h
    30 | 13.0SP1 | include/alt_interrupt_common.h
    31 | 13.0SP1 | include/alt_mpu_registers.h
    32 | 13.0SP1 | include/alt_reset_manager.h
    33 | 13.0SP1 | include/hwlib.h
    34 | 13.0SP1 | include/socal/alt_clkmgr.h
    35 | 13.0SP1 | include/socal/alt_gpio.h
    36 | 13.1    | include/socal/alt_i2c.h
    37 | 13.0SP1 | include/socal/alt_l3.h
    38 | 13.0SP1 | include/socal/alt_rstmgr.h
    39 | 13.0SP1 | include/socal/alt_sdr.h
    40 | 13.0SP1 | include/socal/alt_sysmgr.h
    41 | 13.0SP1 | include/socal/alt_uart.h
    42 | 13.0SP1 | include/socal/hps.h
    43 | 13.0SP1 | include/socal/socal.h
    44 | 13.0SP1 | src/hwmgr/alt_address_space.c
    45 | 13.0SP1 | src/hwmgr/alt_clock_manager.c
    46 | 13.0SP1 | src/hwmgr/alt_generalpurpose_io.c
    47 | 13.1    | src/hwmgr/alt_i2c.c
    48 | 13.0SP1 | src/hwmgr/alt_reset_manager.c
    49 |========================================
    50 
    51 hwlib 13.0SP1 is from SoC EDS 13.0.1.232
    52 hwlib 13.1 is from SoC EDS 14.0.0.200
     19All files are from hwlib 13.1 distributed with SoC EDS 14.0.0.200.
  • c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_address_space.h

    r96ec8ee8 r9907dde  
    3333******************************************************************************/
    3434
    35 #ifndef __ALT_ADDR_SPACE_H__
    36 #define __ALT_ADDR_SPACE_H__
     35#ifndef __ALT_ADDRESS_SPACE_H__
     36#define __ALT_ADDRESS_SPACE_H__
    3737
    3838#include <stdbool.h>
     
    8383// Address Filtering End Register - End Value Mask
    8484#define L2_CACHE_ADDR_FILTERING_END_ADDR_MASK   0xFFF00000
    85 // Address Filtering End Register - Reset End Address Value (3 GB)
     85// Address Filtering End Register - Reset End Address Value (3 GiB)
    8686#define L2_CACHE_ADDR_FILTERING_END_RESET       0xC0000000
    8787
     
    193193typedef enum ALT_ADDR_SPACE_NONMPU_ATTR_e
    194194{
    195     ALT_ADDR_SPACE_NONMPU_ZERO_AT_OCRAM,    /*!< Maps the SDRAM to address 0x0
     195    ALT_ADDR_SPACE_NONMPU_ZERO_AT_SDRAM,    /*!< Maps the SDRAM to address 0x0
    196196                                             *   for the non-MPU L3 masters.
    197197                                             */
    198     ALT_ADDR_SPACE_NONMPU_ZERO_AT_SDRAM     /*!< Maps the On-chip RAM to address
     198    ALT_ADDR_SPACE_NONMPU_ZERO_AT_OCRAM     /*!< Maps the On-chip RAM to address
    199199                                             *   0x0 for the non-MPU L3
    200200                                             *   masters. Note that the On-chip
     
    277277 * When address 0x0 is mapped to the Boot ROM or on-chip RAM, only the lowest
    278278 * 64KB of the boot region are accessible because the size of the Boot ROM and
    279  * on-chip RAM are only 64KB.  Addresses in the range 0x100000 (1MB) to
    280  * 0xC0000000 (3GB) access SDRAM and addresses in the range 0xC0000000 (3GB) to
    281  * 0xFFFFFFFF access the L3 interconnect. Thus, the lowest 1MB of SDRAM is not
     279 * on-chip RAM are only 64KB.  Addresses in the range 0x100000 (1MiB) to
     280 * 0xC0000000 (3GiB) access SDRAM and addresses in the range 0xC0000000 (3GiB) to
     281 * 0xFFFFFFFF access the L3 interconnect. Thus, the lowest 1MiB of SDRAM is not
    282282 * accessible to the MPU unless address 0 is remapped to SDRAM after reset.
    283283 *
    284  * This function remaps the addresses between 0x0 to 0x100000 (1MB) to access
     284 * This function remaps the addresses between 0x0 to 0x100000 (1MiB) to access
    285285 * SDRAM.
    286286 *
     
    333333 *              [out] An output parameter variable for the address filtering
    334334 *              start address for the range of physical addresses redirected to
    335  *              the SDRAM AXI master port. The value returned is always a 1 MB
     335 *              the SDRAM AXI master port. The value returned is always a 1 MiB
    336336 *              aligned address.
    337337 *             
     
    339339 *              [out] An output parameter variable for the address filtering
    340340 *              end address for the range of physical addresses redirected to
    341  *              the SDRAM AXI master port. The value returned is always a 1 MB
     341 *              the SDRAM AXI master port. The value returned is always a 1 MiB
    342342 *              aligned address.
    343343 *
     
    354354 * Set the L2 cache address filtering configuration settings.
    355355 *
    356  * Address filtering start and end values must be 1 MB aligned.
     356 * Address filtering start and end values must be 1 MiB aligned.
    357357 *
    358358 * \param       addr_filt_start
     
    381381/*! @} */
    382382
     383/******************************************************************************/
     384/*! \addtogroup ADDR_SPACE_MGR_MEM_COHERENCE ACP Memory Coherence and ID Mapping
     385 *
     386 * This API provides management of the ACP ID Mapper that enables data coherent
     387 * access to the MPU address space by external masters. The set of external
     388 * masters include L3 master peripherals and FPGA soft IP.
     389 *
     390 * The Accelerator Coherency Port (ACP) allows peripherals - including FPGA
     391 * based soft IP - to maintain data coherency with the Cortex-A9 MPCore
     392 * processors and the Snoop Control Unit (SCU).
     393 *
     394 * The ACP supports up to six masters. However, soft IP implemented in the FPGA
     395 * fabric can have a larger number of masters that need to access the ACP. The
     396 * ACP ID Mapper expands the number of masters able to access the ACP.  The ACP
     397 * ID Mapper is situated between the interconnect and the ACP of the MPU
     398 * subsystem. It has the following characteristics:
     399 * * Support for up to six concurrent ID mappings.
     400 * * 1 GiB coherent window into 4 GiB MPU address space
     401 * * Remaps the 5-bit user sideband signals used by the Snoop Control Unit (SCU)
     402 *   and L2 cache.
     403 *
     404 * The function of the ACP ID Mapper is to map 12-bit Advanced Microcontroller
     405 * Bus Architecture (AMBA) Advanced eXtensible Interface (AXI) IDs (input
     406 * identifiers) from the Level 3 (L3) interconnect to 3-bit AXI IDs (output
     407 * identifiers) required by the ACP slave port.
     408 *
     409 * The ACP ID Mapper supports the two ID mapping modes:
     410 * * Dynamic Mapping - In this mode an input ID is automatically mapped to an
     411 *   available output ID. The dynamic mode is more flexible because the hardware
     412 *   handles the mapping. The hardware mapping allows an output ID to be used
     413 *   for more than one input ID. Output IDs are assigned to input IDs on a
     414 *   first-come, first-served basis.
     415 * * Fixed Mapping - In this mode there is a one-to-one mapping from input IDs
     416 *   to output IDs.
     417 *
     418 * Out of the total of eight ACP output ID values, only six are available to the
     419 * ACP ID Mapper for remapping.  The first two output IDs (0 and 1) are
     420 * dedicated to the Cortex-A9 processor cores in the MPU subsystem, leaving the
     421 * last six output IDs (2-7) available to the ACP ID mapper. Output IDs 2-6
     422 * support fixed and dynamic modes of operation while output ID 7 supports
     423 * dynamic mode only.
     424 *
     425 * The following table summarizes the usage of the 3-bit ouput ID values by the
     426 * ACP ID Mapper and their settings at reset.
     427 *
     428 *  Output ID  | Usage                                             | Reset State     
     429 * :-----------|:--------------------------------------------------|:------------
     430 *         0   | Reserved for Cortex-A9 cores.                     | -               
     431 *         1   | Reserved for Cortex-A9 cores.                     | -               
     432 *         2   | Assigned to Debug Access Port (DAP) input ID at   | Fixed           
     433 * :           | reset. After reset, can be reconfigured to either | DAP Master
     434 * :           | fixed or dynamic.                                 |:
     435 *         3   | Configurable fixed or dynamic mode.               | Dynamic         
     436 *         4   | Configurable fixed or dynamic mode.               | Dynamic         
     437 *         5   | Configurable fixed or dynamic mode.               | Dynamic         
     438 *         6   | Configurable fixed or dynamic mode.               | Dynamic         
     439 *         7   | Dynamic mode only.                                | Dynamic         
     440 *
     441 * Where <em>Output ID</em> is the ACP ID Mapper output value that goes to the ACP.
     442 *
     443 * Additionally, for masters unable to drive the AXI user sideband signals of
     444 * incoming transactions, the ACP ID Mapper allows control of the AXI user
     445 * sideband signal values. Not all masters drive these signals, so the ACP ID
     446 * Mapper makes it possible to drive the 5-bit user sideband signal with either
     447 * a default value (in dynamic mode) or specific values (in fixed mode).
     448 *
     449 * The ACP ID Mapper can also control which 1 GiB coherent window into memory is
     450 * accessed by masters of the L3 interconnect. Each fixed mapping can be
     451 * assigned a different user sideband signal and memory window to allow specific
     452 * settings for different masters. All dynamic mappings share a common user
     453 * sideband signal and memory window setting.  One important exception, however,
     454 * is that the ACP ID mapper always allows user sideband signals from the
     455 * FPGA-to-HPS bridge to pass through to the ACP regardless of the configured
     456 * user sideband value associated with the ID.
     457 *
     458 * The ACP ID Mapper has a 1 GiB address window into the MPU address space, which
     459 * is by default a view into the bottom 1 GiB of SDRAM. The ACP ID Mapper allows
     460 * transactions to be routed to different 1 GiB-sized memory views, called pages,
     461 * in both dynamic and fixed modes.
     462 *
     463 * See: <em>Chapter 6: Cortex-A9 Microprocessor Unit Subsystem</em> in
     464 * <em>Volume 3: Hard Processor System Technical Reference Manual</em> of the
     465 * <em>Arria V or Cyclone V Device Handbook</em> for a complete discussion of
     466 * the operation and restrictions on the ACP and the ACP ID Mapper.
     467 *
     468 * @{
     469 */
     470
     471/******************************************************************************/
     472/*!
     473 * \name External Master ID Macros
     474 *
     475 * These macros define the HPS external master identifiers that are 12-bit input
     476 * IDs to the ACP ID Mapper. Some of the masters have a range of identifier
     477 * values assigned to them and are distinguished by taking a <em>(var)\</em>
     478 * argument.
     479 * @{
     480 */
     481
     482/*! Bit mask for the relevant 12 bits of an external master ID */
     483#define ALT_ACP_ID_MAP_MASTER_ID_MASK           0xfff
     484
     485/*! Master ID for L2M0 */
     486#define ALT_ACP_ID_MAP_MASTER_ID_L2M0(var)      (0x00000002 | (0x000007f8 & (var)))
     487/*! Master ID for DMA */
     488#define ALT_ACP_ID_MAP_MASTER_ID_DMA(var)       (0x00000001 | (0x00000078 & (var)))
     489/*! Master ID for EMAC0 */
     490#define ALT_ACP_ID_MAP_MASTER_ID_EMAC0(var)     (0x00000801 | (0x00000878 & (var)))
     491/*! Master ID for EMAC1 */
     492#define ALT_ACP_ID_MAP_MASTER_ID_EMAC1(var)     (0x00000802 | (0x00000878 & (var)))
     493/*! Master ID for USB0 */
     494#define ALT_ACP_ID_MAP_MASTER_ID_USB0           0x00000803
     495/*! Master ID for USB1 */
     496#define ALT_ACP_ID_MAP_MASTER_ID_USB1           0x00000806
     497/*! Master ID for NAND controller */
     498#define ALT_ACP_ID_MAP_MASTER_ID_NAND(var)      (0x00000804 | (0x00000ff8 & (var)))
     499/*! Master ID for Embedded Trace Router (ETR) */
     500#define ALT_ACP_ID_MAP_MASTER_ID_TMC            0x00000800
     501/*! Master ID for  Debug Access Port (DAP) */
     502#define ALT_ACP_ID_MAP_MASTER_ID_DAP            0x00000004
     503/*! Master ID for  SD/MMC controller */
     504#define ALT_ACP_ID_MAP_MASTER_ID_SDMMC          0x00000805
     505/*! Master ID for FPGA to HPS (F2H) bridge - conduit for soft IP masters in FPGA fabric */
     506#define ALT_ACP_ID_MAP_MASTER_ID_F2H(var)       (0x00000000 | (0x000007f8 & (var)))
     507/*! @} */
     508
     509/******************************************************************************/
     510/*!
     511  * This type defines the enumerations 3-bit output ids to ACP ID mapper.
     512 */
     513typedef enum ALT_ACP_ID_OUTPUT_ID_e
     514{
     515    ALT_ACP_ID_OUT_FIXED_ID_2 = 2,  /*!< Assigned to the input ID of the DAP at reset.
     516                                     *   After reset, can be either fixed or dynamic,
     517                                     *   programmed by software.
     518                                     */
     519    ALT_ACP_ID_OUT_DYNAM_ID_3 = 3,  /*!< Fixed or dynamic, programmed by software output id */
     520    ALT_ACP_ID_OUT_DYNAM_ID_4 = 4,  /*!< Fixed or dynamic, programmed by software output id */
     521    ALT_ACP_ID_OUT_DYNAM_ID_5 = 5,  /*!< Fixed or dynamic, programmed by software output id */
     522    ALT_ACP_ID_OUT_DYNAM_ID_6 = 6,  /*!< Fixed or dynamic, programmed by software output id */
     523    ALT_ACP_ID_OUT_DYNAM_ID_7 = 7   /*!< Dynamic mapping only */
     524} ALT_ACP_ID_OUTPUT_ID_t;
     525
     526/*!
     527 * This type defines the enumerations used to specify the 1 GiB page view of the
     528 * MPU address space used by an ACP ID mapping configuration.
     529 */
     530typedef enum ALT_ACP_ID_MAP_PAGE_e
     531{
     532    ALT_ACP_ID_MAP_PAGE_0 = 0,  /*!< Page 0 - MPU address range 0x00000000 - 0x3FFFFFFF */
     533    ALT_ACP_ID_MAP_PAGE_1 = 1,  /*!< Page 1 - MPU address range 0x40000000 - 0x7FFFFFFF */
     534    ALT_ACP_ID_MAP_PAGE_2 = 2,  /*!< Page 2 - MPU address range 0x80000000 - 0xBFFFFFFF */
     535    ALT_ACP_ID_MAP_PAGE_3 = 3   /*!< Page 3 - MPU address range 0xC0000000 - 0xFFFFFFFF */
     536} ALT_ACP_ID_MAP_PAGE_t;
     537
     538/******************************************************************************/
     539/*!
     540 * Configure a fixed ACP ID mapping for read transactions originating from
     541 * external masters identified by \e input_id. The \e input_id value is
     542 * translated to the specified 3-bit \e output_id required by the ACP slave
     543 * port.
     544 *
     545 * \param       input_id
     546 *              The 12 bit external master ID originating read transactions
     547 *              targeted for ID translation. Valid argument range must be 0 <=
     548 *              \e output_id <= 4095.
     549 *
     550 * \param       output_id
     551 *              The 3-bit output ID value the ACP ID Mapper translates read
     552 *              transactions identified by \e input_id to. This is the value
     553 *              propogated to the ACP slave port.  Valid argument values must be
     554 *              0 <= \e output_id <= 7.
     555 *
     556 * \param       page
     557 *              The MPU address space page view to use for the ACP window used
     558 *              by the ID tranlation mapping.
     559 *
     560 * \param       aruser
     561 *              The 5-bit AXI ARUSER read user sideband signal value to use for
     562 *              masters unable to drive the AXI user sideband signals.  Valid
     563 *              argument range is 0 <= \e aruser <= 31.
     564 *
     565 * \retval      ALT_E_SUCCESS   The operation was succesful.
     566 * \retval      ALT_E_ERROR     The operation failed.
     567 * \retval      ALT_E_RESERVED  The argument value is reserved or unavailable.
     568 * \retval      ALT_E_ARG_RANGE An argument violates a range constraint. One or
     569 *                              more of the \e input_id, and/or \e output_id
     570 *                              arguments violates its range constraint.
     571 * \retval      ALT_E_BAD_ARG   The \e page argument is invalid.
     572 */
     573ALT_STATUS_CODE alt_acp_id_map_fixed_read_set(const uint32_t input_id,
     574                                              const uint32_t output_id,
     575                                              const ALT_ACP_ID_MAP_PAGE_t page,
     576                                              const uint32_t aruser);
     577
     578/******************************************************************************/
     579/*!
     580 * Configure a fixed ACP ID mapping for write transactions originating from
     581 * external masters identified by \e input_id. The \e input_id value is
     582 * translated to the specified 3-bit \e output_id required by the ACP slave
     583 * port.
     584 *
     585 * \param       input_id
     586 *              The 12 bit external master ID originating write transactions
     587 *              targeted for ID translation. Valid argument range must be 0 <=
     588 *              \e output_id <= 4095.
     589 *
     590 * \param       output_id
     591 *              The 3-bit output ID value the ACP ID Mapper translates write
     592 *              transactions identified by \e input_id to. This is the value
     593 *              propogated to the ACP slave port.  Valid argument values must be
     594 *              0 <= \e output_id <= 7.
     595 *
     596 * \param       page
     597 *              The MPU address space page view to use for the ACP window used
     598 *              by the ID tranlation mapping.
     599 *
     600 * \param       awuser
     601 *              The 5-bit AXI AWUSER write user sideband signal value to use for
     602 *              masters unable to drive the AXI user sideband signals.  Valid
     603 *              argument range is 0 <= \e awuser <= 31.
     604 *
     605 * \retval      ALT_E_SUCCESS   The operation was succesful.
     606 * \retval      ALT_E_ERROR     The operation failed.
     607 * \retval      ALT_E_RESERVED  The argument value is reserved or unavailable.
     608 * \retval      ALT_E_ARG_RANGE An argument violates a range constraint. One or
     609 *                              more of the \e input_id, and/or \e output_id
     610 *                              arguments violates its range constraint.
     611 * \retval      ALT_E_BAD_ARG   The \e page argument is invalid.
     612 */
     613ALT_STATUS_CODE alt_acp_id_map_fixed_write_set(const uint32_t input_id,
     614                                               const uint32_t output_id,
     615                                               const ALT_ACP_ID_MAP_PAGE_t page,
     616                                               const uint32_t awuser);
     617
     618/******************************************************************************/
     619/*!
     620 * Configure the designated 3-bit output ID as an available identifier resource
     621 * for use by the dynamic ID mapping function of the ACP ID Mapper for read
     622 * transactions. The \e output_id value is available for dynamic assignment to
     623 * external master read transaction IDs that do not have an explicit fixed ID
     624 * mapping.
     625 *
     626 * \param       output_id
     627 *              The 3-bit output ID value designated as an available ID for use
     628 *              by the dynamic mapping function of the ACP ID Mapper. The \e
     629 *              ouput_id value is used exclusively for dynamic ID mapping until
     630 *              reconfigured as a fixed ID mapping by a call to
     631 *              alt_acp_id_map_fixed_read_set().  Valid argument values must be
     632 *              0 <= \e output_id <= 7.
     633 *
     634 * \retval      ALT_E_SUCCESS   The operation was succesful.
     635 * \retval      ALT_E_ERROR     The operation failed.
     636 * \retval      ALT_E_RESERVED  The argument value is reserved or unavailable.
     637 * \retval      ALT_E_ARG_RANGE An argument violates a range constraint.
     638 */
     639ALT_STATUS_CODE alt_acp_id_map_dynamic_read_set(const uint32_t output_id);
     640
     641/******************************************************************************/
     642/*!
     643 * Configure the designated 3-bit output ID as an available identifier resource
     644 * for use by the dynamic ID mapping function of the ACP ID Mapper for write
     645 * transactions. The \e output_id value is available for dynamic assignment to
     646 * external master write transaction IDs that do not have an explicit fixed ID
     647 * mapping.
     648 *
     649 * \param       output_id
     650 *              The 3-bit output ID value designated as an available ID for use
     651 *              by the dynamic mapping function of the ACP ID Mapper. The \e
     652 *              ouput_id value is used exclusively for dynamic ID mapping until
     653 *              reconfigured as a fixed ID mapping by a call to
     654 *              alt_acp_id_map_fixed_write_set().  Valid argument values must be
     655 *              0 <= \e output_id <= 7.
     656 *
     657 * \retval      ALT_E_SUCCESS   The operation was succesful.
     658 * \retval      ALT_E_ERROR     The operation failed.
     659 * \retval      ALT_E_RESERVED  The argument value is reserved or unavailable.
     660 * \retval      ALT_E_ARG_RANGE An argument violates a range constraint.
     661 */
     662ALT_STATUS_CODE alt_acp_id_map_dynamic_write_set(const uint32_t output_id);
     663
     664/******************************************************************************/
     665/*!
     666 * Configure the page and user read sideband signal options that are applied to
     667 * all read transactions that have their input IDs dynamically mapped.
     668 *
     669 * \param       page
     670 *              The MPU address space page view to use for the ACP window used
     671 *              by the dynamic ID tranlation mapping.
     672 *
     673 * \param       aruser
     674 *              The 5-bit AXI ARUSER read user sideband signal value to use for
     675 *              masters unable to drive the AXI user sideband signals.  Valid
     676 *              argument range is 0 <= \e aruser <= 31.
     677 *
     678 * \retval      ALT_E_SUCCESS   The operation was succesful.
     679 * \retval      ALT_E_ERROR     The operation failed.
     680 * \retval      ALT_E_RESERVED  The argument value is reserved or unavailable.
     681 * \retval      ALT_E_ARG_RANGE An argument violates a range constraint. One or
     682 *                              more of the \e page and/or \e aruser
     683 *                              arguments violates its range constraint.
     684 * \retval      ALT_E_BAD_ARG   The \e mid argument is not a valid master
     685 *                              identifier.
     686 */
     687ALT_STATUS_CODE alt_acp_id_map_dynamic_read_options_set(const ALT_ACP_ID_MAP_PAGE_t page,
     688                                                        const uint32_t aruser);
     689
     690/******************************************************************************/
     691/*!
     692 * Configure the page and user write sideband signal options that are applied to
     693 * all write transactions that have their input IDs dynamically mapped.
     694 *
     695 * \param       page
     696 *              The MPU address space page view to use for the ACP window used
     697 *              by the dynamic ID tranlation mapping.
     698 *
     699 * \param       awuser
     700 *              The 5-bit AXI AWUSER write user sideband signal value to use for
     701 *              masters unable to drive the AXI user sideband signals.  Valid
     702 *              argument range is 0 <= \e aruser <= 31.
     703 *
     704 * \retval      ALT_E_SUCCESS   The operation was succesful.
     705 * \retval      ALT_E_ERROR     The operation failed.
     706 * \retval      ALT_E_RESERVED  The argument value is reserved or unavailable.
     707 * \retval      ALT_E_ARG_RANGE An argument violates a range constraint. One or
     708 *                              more of the \e page and/or \e awuser
     709 *                              arguments violates its range constraint.
     710 * \retval      ALT_E_BAD_ARG   The \e mid argument is not a valid master
     711 *                              identifier.
     712 */
     713ALT_STATUS_CODE alt_acp_id_map_dynamic_write_options_set(const ALT_ACP_ID_MAP_PAGE_t page,
     714                                                         const uint32_t awuser);
     715
     716/******************************************************************************/
     717/*!
     718 * Return the current read transaction mapping configuration used by the ACP ID
     719 * Mapper for the specified output ID.
     720 *
     721 * If \e output_id is configured as a fixed mapping then \b true is returned in
     722 * the \e fixed output parameter and the translation mapping options configured
     723 * for that \e output_id are returned in the other output parameters.
     724 *
     725 * If \e output_id is configured as a dynamic mapping then \b false is returned
     726 * in the \e fixed output parameter and the translation mapping options
     727 * configured for all dynamically remapped output IDs are returned in the other
     728 * output parameters.
     729 *
     730 * \param       output_id
     731 *              The output ID to return the mapping configuration for. 0 <= \e
     732 *              output_id <= 7.
     733 *
     734 * \param       fixed
     735 *              [out] Set to \b true if the specified \e output_id is a fixed ID
     736 *              mapping configuration. Set to \b false if the mapping
     737 *              configuration is dynamic.
     738 *
     739 * \param       input_id
     740 *              [out] The input ID of the external master that a fixed ID
     741 *              mapping is applied to for the \e output_id. If \e fixed is \b
     742 *              false then this output parameter is set to 0 and its value
     743 *              should be considered as not applicable.
     744 *
     745 * \param       page
     746 *              [out] The MPU address space page view used by the mapping
     747 *              configuration.
     748 *
     749 * \param       aruser
     750 *              [out] The 5-bit AXI ARUSER read user sideband signal value used
     751 *              by the mapping configuration when masters are unable to drive
     752 *              the AXI user sideband signals.
     753 *
     754 * \retval      ALT_E_SUCCESS   The operation was succesful.
     755 * \retval      ALT_E_ERROR     The operation failed.
     756 * \retval      ALT_E_RESERVED  The argument value is reserved or unavailable.
     757 * \retval      ALT_E_ARG_RANGE An argument violates a range constraint. The \e
     758 *                              output_id argument violates its range constraint.
     759 */
     760ALT_STATUS_CODE alt_acp_id_map_read_options_get(const uint32_t output_id,
     761                                                bool* fixed,
     762                                                uint32_t* input_id,
     763                                                ALT_ACP_ID_MAP_PAGE_t* page,
     764                                                uint32_t* aruser);
     765
     766/******************************************************************************/
     767/*!
     768 * Return the current write transaction mapping configuration used by the ACP ID
     769 * Mapper for the specified output ID.
     770 *
     771 * If \e output_id is configured as a fixed mapping then \b true is returned in
     772 * the \e fixed output parameter and the translation mapping options configured
     773 * for that \e output_id are returned in the other output parameters.
     774 *
     775 * If \e output_id is configured as a dynamic mapping then \b false is returned
     776 * in the \e fixed output parameter and the translation mapping options
     777 * configured for all dynamically remapped output IDs are returned in the other
     778 * output parameters.
     779 *
     780 * \param       output_id
     781 *              The output ID to return the mapping configuration for. 0 <= \e
     782 *              output_id <= 7.
     783 *
     784 * \param       fixed
     785 *              [out] Set to \b true if the specified \e output_id is a fixed ID
     786 *              mapping configuration. Set to \b false if the mapping
     787 *              configuration is dynamic.
     788 *
     789 * \param       input_id
     790 *              [out] The input ID of the external master that a fixed ID
     791 *              mapping is applied to for the \e output_id. If \e fixed is \b
     792 *              false then this output parameter is set to 0 and its value
     793 *              should be considered as not applicable.
     794 *
     795 * \param       page
     796 *              [out] The MPU address space page view used by the mapping
     797 *              configuration.
     798 *
     799 * \param       awuser
     800 *              [out] The 5-bit AXI AWUSER write user sideband signal value used
     801 *              by the mapping configuration when masters are unable to drive
     802 *              the AXI user sideband signals.
     803 *
     804 * \retval      ALT_E_SUCCESS   The operation was succesful.
     805 * \retval      ALT_E_ERROR     The operation failed.
     806 * \retval      ALT_E_RESERVED  The argument value is reserved or unavailable.
     807 * \retval      ALT_E_ARG_RANGE An argument violates a range constraint. The \e
     808 *                              output_id argument violates its range constraint.
     809 */
     810ALT_STATUS_CODE alt_acp_id_map_write_options_get(const uint32_t output_id,
     811                                                 bool* fixed,
     812                                                 uint32_t* input_id,
     813                                                 ALT_ACP_ID_MAP_PAGE_t* page,
     814                                                 uint32_t* awuser);
     815
     816/*! @} */
     817
    383818/*! @} */
    384819
     
    388823}
    389824#endif  /* __cplusplus */
    390 #endif  /* __ALT_ADDR_SPACE_H__ */
     825#endif  /* __ALT_ADDRESS_SPACE_H__ */
  • c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_clock_group.h

    r96ec8ee8 r9907dde  
    1 /*! \file
    2  *  Contains the definition of an opaque data structure that contains raw
    3  *  configuration information for a clock group.
     1/******************************************************************************
     2 *
     3 * Copyright 2013 Altera Corporation. All Rights Reserved.
     4 *
     5 * Redistribution and use in source and binary forms, with or without
     6 * modification, are permitted provided that the following conditions are met:
     7 *
     8 * 1. Redistributions of source code must retain the above copyright notice,
     9 * this list of conditions and the following disclaimer.
     10 *
     11 * 2. Redistributions in binary form must reproduce the above copyright notice,
     12 * this list of conditions and the following disclaimer in the documentation
     13 * and/or other materials provided with the distribution.
     14 *
     15 * 3. The name of the author may not be used to endorse or promote products
     16 * derived from this software without specific prior written permission.
     17 *
     18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR
     19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
     20 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO
     21 * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
     22 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
     23 * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
     26 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
     27 * OF SUCH DAMAGE.
     28 *
     29 ******************************************************************************/
     30
     31/*!
     32 * \file
     33 *
     34 * Contains the definition of an opaque data structure that contains raw
     35 * configuration information for a clock group.
    436 */
    5 
    6 /******************************************************************************
    7 *
    8 * Copyright 2013 Altera Corporation. All Rights Reserved.
    9 *
    10 * Redistribution and use in source and binary forms, with or without
    11 * modification, are permitted provided that the following conditions are met:
    12 *
    13 * 1. Redistributions of source code must retain the above copyright notice,
    14 * this list of conditions and the following disclaimer.
    15 *
    16 * 2. Redistributions in binary form must reproduce the above copyright notice,
    17 * this list of conditions and the following disclaimer in the documentation
    18 * and/or other materials provided with the distribution.
    19 *
    20 * 3. The name of the author may not be used to endorse or promote products
    21 * derived from this software without specific prior written permission.
    22 *
    23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR
    24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
    25 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO
    26 * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
    27 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
    28 * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
    29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
    30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
    31 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
    32 * OF SUCH DAMAGE.
    33 *
    34 ******************************************************************************/
    3537
    3638#ifndef __ALT_CLK_GRP_H__
     
    4547#endif  /* __cplusplus */
    4648
    47 
    48 /*! This type definition enumerates the clock groups
    49 */
     49/*!
     50 * This type definition enumerates the clock groups
     51 */
    5052typedef enum ALT_CLK_GRP_e
    5153{
    52         ALT_MAIN_PLL_CLK_GRP,                                   /*!< Main PLL clock group */
     54    ALT_MAIN_PLL_CLK_GRP,        /*!< Main PLL clock group */
    5355
    54         ALT_PERIPH_PLL_CLK_GRP,                                 /*!< Peripheral PLL clock group */
     56    ALT_PERIPH_PLL_CLK_GRP,      /*!< Peripheral PLL clock group */
    5557
    56         ALT_SDRAM_PLL_CLK_GRP                                   /*!< SDRAM PLL clock group */
     58    ALT_SDRAM_PLL_CLK_GRP        /*!< SDRAM PLL clock group */
    5759
    5860} ALT_CLK_GRP_t;
    5961
    60 
    61 
    62 /*! This type definition defines an opaque data structure for holding the
    63  *  configuration settings for a complete clock group.
     62/*!
     63 * This type definition defines an opaque data structure for holding the
     64 * configuration settings for a complete clock group.
    6465 */
    6566typedef struct ALT_CLK_GROUP_RAW_CFG_s
    6667{
    67     uint32_t                              verid;                /*!< SoC FPGA version identifier. This field
    68                                                                                         *   encapsulates the silicon identifier and
    69                                                                                         *   version information associated with this
    70                                                                                         *   clock group configuration. It is used to
    71                                                                                         *   assert that this clock group configuration
    72                                                                                         *   is valid for this device.
    73                                                                                         */
    74     uint32_t                              siliid2;              /*!< Reserved register - reserved for future
    75                                                                                 *        device IDs or capability flags/
    76                                                                                 */
    77     ALT_CLK_GRP_t                 clkgrpsel;    /*!< Clock group union discriminator */
     68    uint32_t      verid;     /*!< SoC FPGA version identifier. This field
     69                              *   encapsulates the silicon identifier and
     70                              *   version information associated with this
     71                              *   clock group configuration. It is used to
     72                              *   assert that this clock group configuration
     73                              *   is valid for this device. */
    7874
     75    uint32_t      siliid2;   /*!< Reserved register - reserved for future
     76                              *   device IDs or capability flags. */
    7977
    80     /*! This union holds the raw register values for configuration of the set of
    81      *  possible clock groups on the SoC FPGA. The \e clkgrpsel discriminator
    82      *  identifies the valid clock group union data member.
     78    ALT_CLK_GRP_t clkgrpsel; /*!< Clock group union discriminator. */
     79
     80    /*!
     81     * This union holds the register values for configuration of the set of
     82     * possible clock groups on the SoC FPGA. The \e clkgrpsel discriminator
     83     * identifies the valid clock group union data member.
    8384     */
    8485    union ALT_CLK_GROUP_RAW_CFG_u
    8586    {
    86         ALT_CLKMGR_MAINPLL_t  mainpllgrp;   /*!< Raw clock group configuration for Main PLL group */
    87         ALT_CLKMGR_PERPLL_t   perpllgrp;    /*!< Raw clock group configuration for Peripheral PLL group */
    88         ALT_CLKMGR_SDRPLL_t   sdrpllgrp;    /*!< Raw clock group configuration for SDRAM PLL group */
     87        /*! Clock group configuration for Main PLL group. */
     88        union
     89        {
     90            ALT_CLKMGR_MAINPLL_t     fld; /*!< Field access. */
     91            ALT_CLKMGR_MAINPLL_raw_t raw; /*!< Raw access. */
     92        } mainpllgrp;
     93
     94        /*! Clock group configuration for Peripheral PLL group. */
     95        union
     96        {
     97            ALT_CLKMGR_PERPLL_t     fld; /*!< Field access. */
     98            ALT_CLKMGR_PERPLL_raw_t raw; /*!< Raw access. */
     99        } perpllgrp;
     100
     101        /*! Clock group configuration for SDRAM PLL group. */
     102        union
     103        {
     104            ALT_CLKMGR_SDRPLL_t     fld; /*!< Field access. */
     105            ALT_CLKMGR_SDRPLL_raw_t raw; /*!< Raw access. */
     106        } sdrpllgrp;
     107
    89108    } clkgrp;
    90109} ALT_CLK_GROUP_RAW_CFG_t;
  • c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_clock_manager.h

    r96ec8ee8 r9907dde  
    77*
    88* Copyright 2013 Altera Corporation. All Rights Reserved.
    9 * 
     9*
    1010* Redistribution and use in source and binary forms, with or without
    1111* modification, are permitted provided that the following conditions are met:
    12 * 
     12*
    1313* 1. Redistributions of source code must retain the above copyright notice,
    1414* this list of conditions and the following disclaimer.
    15 * 
     15*
    1616* 2. Redistributions in binary form must reproduce the above copyright notice,
    1717* this list of conditions and the following disclaimer in the documentation
    1818* and/or other materials provided with the distribution.
    19 * 
     19*
    2020* 3. The name of the author may not be used to endorse or promote products
    2121* derived from this software without specific prior written permission.
    22 * 
     22*
    2323* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR
    2424* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
     
    3131* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
    3232* OF SUCH DAMAGE.
    33 * 
     33*
    3434******************************************************************************/
    3535
     
    8383                                         *   External Oscillator input:
    8484                                         *   * Input Pin
    85                                          *   * Optional clock source to SDRAM PLL 
     85                                         *   * Optional clock source to SDRAM PLL
    8686                                         *     and Peripheral PLL if selected
    8787                                         *   * Typically used for Ethernet
     
    133133                                         */
    134134
    135    
     135
    136136    /* PLLs */
    137137    ALT_CLK_MAIN_PLL,
     
    143143
    144144    ALT_CLK_PERIPHERAL_PLL,
    145                                         /*!< \b periph_pll_ref_clkin 
     145                                        /*!< \b periph_pll_ref_clkin
    146146                                         *   Peripheral PLL input reference
    147147                                         *   clock, used to designate the
     
    237237    ALT_CLK_L4_SP,
    238238                                        /*!< \b l4_sp_clk
    239                                          *   Clock for L4 slave peripherals (SP) bus 
     239                                         *   Clock for L4 slave peripherals (SP) bus
    240240                                         */
    241241
     
    280280
    281281    ALT_CLK_MAIN_NAND_SDMMC,
    282                                         /*!< \b main_nand_sdmmc_clk 
     282                                        /*!< \b main_nand_sdmmc_clk
    283283                                         *   Main PLL C4 Output. Input clock to
    284284                                         *   flash controller clocks block.
     
    287287
    288288    ALT_CLK_CFG,
    289                                         /*!< \b cfg_clk 
     289                                        /*!< \b cfg_clk
    290290                                         *   FPGA manager configuration clock.
    291291                                         */
     
    296296                                         */
    297297
    298    
     298
    299299    /* Peripherals Clock Group - The following clocks are derived from the Peripheral PLL */
    300300    ALT_CLK_PERIPHERAL_PLL_C0,
     
    557557 *
    558558 * \param       lock_stat_mask
    559  *              Specifies the PLL lock status conditions to clear. \e lock_stat_mask 
     559 *              Specifies the PLL lock status conditions to clear. \e lock_stat_mask
    560560 *              is a mask of logically OR'ed \ref ALT_CLK_PLL_LOCK_STATUS_t
    561561 *              values designating the PLL lock conditions to clear.
     
    589589 * \retval      ALT_E_TRUE      The specified PLL is currently locked.
    590590 * \retval      ALT_E_FALSE     The specified PLL is currently not locked.
    591  * \retval      ALT_E_BAD_ARG   The \e pll argument designates a non PLL clock 
     591 * \retval      ALT_E_BAD_ARG   The \e pll argument designates a non PLL clock
    592592 *                              value.
    593593 * \internal
    594594 * NOTE: This function uses the
    595595 *       * \b hps::clkmgr::inter::mainplllocked
    596  *       * \b hps::clkmgr::inter::perplllocked, 
     596 *       * \b hps::clkmgr::inter::perplllocked,
    597597 *       * \b hps::clkmgr::inter::sdrplllocked
    598598 *
     
    613613 * control register. No other control register bits are affected by the safe
    614614 * mode request from the reset manager.
    615  * 
     615 *
    616616 * While in safe mode, clock manager register settings which control clock
    617617 * behavior are not changed. However, the output of the registers which control
     
    620620 * * All PLLs are bypassed to the \b osc1_clk clock, including their counters.
    621621 * * Clock dividers select their default reset values.
    622  * * The flash controllers source clock selections are set to the peripheral 
     622 * * The flash controllers source clock selections are set to the peripheral
    623623 *   PLL.
    624624 * * All clocks are enabled.
    625625 * * Safe mode is optionally applied to debug clocks.
    626  * 
     626 *
    627627 * A write by software is the only way to clear the safe mode bit. All registers
    628628 * and clocks need to be configured correctly and all software-managed clocks
    629629 * need to be gated off before clearing safe mode. Software can then gate clocks
    630630 * on as required.
    631  * 
     631 *
    632632 * On cold reset, all clocks are put in safe mode.
    633  * 
     633 *
    634634 * On warm reset, safe mode is optionally and independently applied to debug
    635635 * clocks and normal (i.e.non-debug) clocks based on clock manager register
    636636 * settings. The default response for warm reset is to put all clocks in safe
    637637 * mode.
    638  * 
     638 *
    639639 * The APIs in this group provide control of the Clock Manager safe mode warm
    640640 * reset response behavior.
     
    652652     * This enumeration literal specifies the normal safe mode domain. The
    653653     * normal domain consists of all clocks except debug clocks.
    654      */ 
     654     */
    655655    ALT_CLK_DOMAIN_NORMAL,
    656656    /*!
    657657     * This enumeration literal specifies the debug safe mode domain. The debug
    658658     * domain consists of all debug clocks.
    659      */ 
     659     */
    660660    ALT_CLK_DOMAIN_DEBUG
    661661} ALT_CLK_SAFE_DOMAIN_t;
     
    704704 * In summary, the PLL bypass controls permit:
    705705 * * Each PLL to be individually bypassed.
    706  * * Bypass of all PLL clock outputs to \b osc1_clk or alternatively the PLLs 
     706 * * Bypass of all PLL clock outputs to \b osc1_clk or alternatively the PLLs
    707707 *   reference clock input source reference clock selection.
    708708 * * Isolation of a the PLL VCO frequency registers (multiplier and divider),
     
    721721 * \retval      ALT_E_SUCCESS   The operation was succesful.
    722722 * \retval      ALT_E_ERROR     The operation failed.
    723  * \retval      ALT_E_BAD_ARG   The \e pll argument specified a non PLL clock 
     723 * \retval      ALT_E_BAD_ARG   The \e pll argument specified a non PLL clock
    724724 *                              value.
    725725 */
     
    752752 * Return whether the specified PLL is in bypass or not.
    753753 *
    754  * \internal 
     754 * \internal
    755755 * This function must also test the \b clkmgr.ctrl.safemode bit in
    756756 * addition to the PLLs bypass bit to tell whether the bypass mode is
     
    763763 * \retval      ALT_E_TRUE      The PLL is in bypass mode.
    764764 * \retval      ALT_E_FALSE     The PLL is not in bypass mode.
    765  * \retval      ALT_E_BAD_ARG   The \e pll argument designates a non PLL clock 
     765 * \retval      ALT_E_BAD_ARG   The \e pll argument designates a non PLL clock
    766766 *                              value.
    767767 */
     
    825825 * \retval      ALT_E_SUCCESS   The operation was succesful.
    826826 * \retval      ALT_E_ERROR     The operation failed.
    827  * \retval      ALT_E_BAD_ARG   The \e clk argument designates a non gated clock 
     827 * \retval      ALT_E_BAD_ARG   The \e clk argument designates a non gated clock
    828828 *                              value.
    829829 */
     
    840840 * \retval      ALT_E_SUCCESS   The operation was succesful.
    841841 * \retval      ALT_E_ERROR     The operation failed.
    842  * \retval      ALT_E_BAD_ARG   The \e clk argument designates a non gated clock 
     842 * \retval      ALT_E_BAD_ARG   The \e clk argument designates a non gated clock
    843843 *                              value.
    844844 */
     
    854854 * \retval      ALT_E_TRUE      The clock is enabled.
    855855 * \retval      ALT_E_FALSE     The clock is not enabled.
    856  * \retval      ALT_E_BAD_ARG   The \e clk argument designates a non gated clock 
     856 * \retval      ALT_E_BAD_ARG   The \e clk argument designates a non gated clock
    857857 *                              value.
    858858 */
     
    913913 * or PLL.
    914914 *
    915  * NOTE: This function returns a clock value even though \e clk may specify a 
    916  *       clock that does not have a selectable input reference clock source. In 
    917  *       this case, the clock value returned is the static clock source for the 
     915 * NOTE: This function returns a clock value even though \e clk may specify a
     916 *       clock that does not have a selectable input reference clock source. In
     917 *       this case, the clock value returned is the static clock source for the
    918918 *       specified clock. For example calling alt_clk_source_get() with \e clk
    919919 *       set to \ref ALT_CLK_MAIN_PLL will return \ref ALT_CLK_OSC1.
    920  *       
     920 *
    921921 * \param       clk
    922922 *              The clock or PLL to retrieve the input reference clock source
     
    940940 * \retval      ALT_E_SUCCESS       The operation was succesful.
    941941 * \retval      ALT_E_ERROR         The operation failed.
    942  * \retval      ALT_E_BAD_ARG       The \e clk argument designates a clock that 
    943  *                                  does not have a selectable input reference 
     942 * \retval      ALT_E_BAD_ARG       The \e clk argument designates a clock that
     943 *                                  does not have a selectable input reference
    944944 *                                  clock source.
    945  * \retval      ALT_E_INV_OPTION    The \e ref_clk argument designates a clock that 
    946  *                                  is an invalid reference clock source for the 
     945 * \retval      ALT_E_INV_OPTION    The \e ref_clk argument designates a clock that
     946 *                                  is an invalid reference clock source for the
    947947 *                                  specified clock.
    948948 */
    949 ALT_STATUS_CODE alt_clk_source_set(ALT_CLK_t clk, 
     949ALT_STATUS_CODE alt_clk_source_set(ALT_CLK_t clk,
    950950                                   ALT_CLK_t ref_clk);
    951951
     
    982982 * \retval      ALT_E_ERROR     The operation failed.
    983983 * \retval      ALT_E_BAD_ARG   A bad argument value was passed. Either the \e clk
    984  *                              argument is bad or not a valid external clock 
     984 *                              argument is bad or not a valid external clock
    985985 *                              source
    986986 * \retval      ALT_E_ARG_RANGE The frequency value violates the range constraints
     
    10191019{
    10201020    ALT_CLK_t           ref_clk;        /*!< PLL Reference Clock Source */
    1021     uint32_t            mult;           /*!< VCO Frequency Configuration - 
     1021    uint32_t            mult;           /*!< VCO Frequency Configuration -
    10221022                                         *   Multiplier (M) value, range 1 to 4096
    10231023                                         */
    1024     uint32_t            div;            /*!< VCO Frequency Configuration - 
     1024    uint32_t            div;            /*!< VCO Frequency Configuration -
    10251025                                         *   Divider (N) value, range 1 to 64
    10261026                                         */
     
    10291029                                         */
    10301030    uint32_t            pshift[6];      /*!< Phase Shift - 1/8 (45 degrees) of
    1031                                                                         *   negative phase shift per increment,
     1031                                        *   negative phase shift per increment,
    10321032                                         *   range 0 to 4096
    10331033                                         */
     
    12631263 * Manager:
    12641264 *
    1265  * * \b clkmgr_IRQ - Clock Manager lock status interrupt output.  The PLL lock 
     1265 * * \b clkmgr_IRQ - Clock Manager lock status interrupt output.  The PLL lock
    12661266 *                   status interrupt is the logical \e OR of six interrupt
    12671267 *                   sources defining the loss or achievement of lock status for
     
    12761276 *                   They are enumeratated by the type \ref ALT_CLK_PLL_LOCK_STATUS_t.
    12771277 *
    1278  *                   Each PLL lock condition may be individually disabled/enabled 
     1278 *                   Each PLL lock condition may be individually disabled/enabled
    12791279 *                   as a contributor to the determination of the \b clkmgr_IRQ
    12801280 *                   assertion status.
     
    12841284 *                   assertion.
    12851285 *
    1286  * * \b mpuwakeup_IRQ - MPU wakeup interrupt output. This interrupt notifies the 
     1286 * * \b mpuwakeup_IRQ - MPU wakeup interrupt output. This interrupt notifies the
    12871287 *                      MPU to "wake up" after a transition of the Main PLL into
    12881288 *                      or out of bypass mode has been safely achieved. The need
     
    13691369 * A known good clock group configuration may be generated by one of the
    13701370 * following methods:
    1371  * 
    1372  * * As static design information generated by an ACDS clock configuration tool 
     1371 *
     1372 * * As static design information generated by an ACDS clock configuration tool
    13731373 *   and passed to embedded software for dynamic loading.
    1374  * 
     1374 *
    13751375 * * By calling alt_clk_group_cfg_raw_get() at run-time from an SoC FPGA that has
    13761376 *   programmatically established a known good clock group configuration using
    13771377 *   the clock manager API configuration functions.
    1378  * 
     1378 *
    13791379 * @{
    13801380 */
     
    14081408 * This function is used to safely set the configuration state of a clock
    14091409 * group from a raw clock group configuration specification.  The raw clock
    1410  * group configuration specification may be a configuration previously 
     1410 * group configuration specification may be a configuration previously
    14111411 * captured with alt_clk_group_cfg_raw_get() or a group clock configuration
    14121412 * generated by an external utility.
     
    14231423ALT_STATUS_CODE alt_clk_group_cfg_raw_set(const ALT_CLK_GROUP_RAW_CFG_t* clk_group_raw_cfg);
    14241424
     1425ALT_STATUS_CODE alt_clk_clkmgr_init(void);
     1426
    14251427/*! @} */
    14261428
     
    14281430#ifdef __cplusplus
    14291431}
     1432
    14301433#endif  /* __cplusplus */
    14311434#endif  /* __ALT_CLK_MGR_H__ */
  • c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_generalpurpose_io.h

    r96ec8ee8 r9907dde  
    66*
    77* Copyright 2013 Altera Corporation. All Rights Reserved.
    8 * 
     8*
    99* Redistribution and use in source and binary forms, with or without
    1010* modification, are permitted provided that the following conditions are met:
    11 * 
     11*
    1212* 1. Redistributions of source code must retain the above copyright notice,
    1313* this list of conditions and the following disclaimer.
    14 * 
     14*
    1515* 2. Redistributions in binary form must reproduce the above copyright notice,
    1616* this list of conditions and the following disclaimer in the documentation
    1717* and/or other materials provided with the distribution.
    18 * 
     18*
    1919* 3. The name of the author may not be used to endorse or promote products
    2020* derived from this software without specific prior written permission.
    21 * 
     21*
    2222* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR
    2323* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
     
    3030* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
    3131* OF SUCH DAMAGE.
    32 * 
     32*
    3333******************************************************************************/
    3434
     
    5858/*! \addtogroup ALT_GPIO_API The General Purpose Input/Output Manager API
    5959 *
    60  * This module defines the General Purpose Input/Output Manager API for 
    61  * accessing, configuring, and controlling the General Purpose Input/Output 
     60 * This module defines the General Purpose Input/Output Manager API for
     61 * accessing, configuring, and controlling the General Purpose Input/Output
    6262 * Manager resources. These include both the general-purpose GPIO signals and
    6363 * the input-only GPI signals that are shared with the DDR interface.\n \n
     
    101101/******************************************************************************/
    102102/*!
    103  * This type definition enumerates the data direction (input or output) of 
     103 * This type definition enumerates the data direction (input or output) of
    104104 * the GPIO signals.
    105105 */
     
    115115/******************************************************************************/
    116116/*!
    117  * This type definition enumerates the type of interrupt source 
     117 * This type definition enumerates the type of interrupt source
    118118 * (level-triggered or edge-triggered) of the GPIO signals.
    119119 */
     
    129129/******************************************************************************/
    130130/*!
    131  * This type definition enumerates the polarity of the interrupt sources 
     131 * This type definition enumerates the polarity of the interrupt sources
    132132 * (falling-edge or rising-edge for edge-triggered interrupts, active-low or
    133133 * active-high for level-triggered interrupts) of the GPIO signals.
     
    194194/******************************************************************************/
    195195/*!
    196  * This type definition enumerates the GPIO ports that the GPIO manager 
     196 * This type definition enumerates the GPIO ports that the GPIO manager
    197197 * handles.
    198198 */
     
    209209     */
    210210    ALT_GPIO_PORTB,
    211    
     211
    212212    /*!
    213213     * \b Port \b C - 29-bit GPIO port C. \n 13 bits are used for GPIO signals,
     
    225225} ALT_GPIO_PORT_t;
    226226
    227    
     227
    228228/******************************************************************************/
    229229/*!
    230230 * This type definition enumerates the individual bits within the GPIO ports
    231  * used by the GPIO manager. The bit-ordering must match the hardware 
    232  * bit-ordering. Since the ordering and packing of bitfields is not 
     231 * used by the GPIO manager. The bit-ordering must match the hardware
     232 * bit-ordering. Since the ordering and packing of bitfields is not
    233233 * standardized in C/C++, the following are defined as masks. \n
    234234 * For example, to set bits 3 and 4 of GPIO port B outputs (assuming the bits
     
    311311/******************************************************************************/
    312312/*!
    313  * Sets the specified GPIO data bits to use the data direction(s)
     313 * Initialize the GPIO modules before use
     314 *
     315 * \retval      ALT_E_SUCCESS   The operation was successful.
     316 * \retval      ALT_E_ERROR     The operation failed.
     317 */
     318ALT_STATUS_CODE alt_gpio_init(void);
     319
     320/******************************************************************************/
     321/*!
     322 * Uninitialize the GPIO modules & return to reset state
     323 *
     324 * \retval      ALT_E_SUCCESS   The operation was successful.
     325 * \retval      ALT_E_ERROR     The operation failed.
     326 */
     327ALT_STATUS_CODE alt_gpio_uninit(void);
     328
     329/******************************************************************************/
     330/*!
     331 * Sets the specified GPIO data bits to use the data direction(s)
    314332 * specified.
    315333 *
     
    318336 *              The GPIO port identifier.
    319337 * \param       mask
    320  *              The group of bits (where mask bits equal one) to apply this 
    321  *              operation to. Other bits (where mask bits equal zero) are 
     338 *              The group of bits (where mask bits equal one) to apply this
     339 *              operation to. Other bits (where mask bits equal zero) are
    322340 *              not changed. Specify mask = ALT_GPIO_BITMASK (0x1FFFFFFF) to
    323341 *              configure all data direction bits of the port.
    324342 * \param       config
    325343 *              The data-directions of the bits to be set in this operation.
    326  *              Individual bits are: \n \b 0 - Use as an input (default). \n 
     344 *              Individual bits are: \n \b 0 - Use as an input (default). \n
    327345 *              \b 1 - Use as an output.
    328346 *
     
    336354/******************************************************************************/
    337355/*!
    338  * Returns the data direction configuration of selected bits of the 
     356 * Returns the data direction configuration of selected bits of the
    339357 * specified GPIO module.
    340358 *
     
    343361 * \param       mask
    344362 *              The group of bits (where mask bits equal one) to read and
    345  *              return. Other bits (where mask bits equal zero) are returned 
     363 *              return. Other bits (where mask bits equal zero) are returned
    346364 *              as zero. Specify mask = ALT_GPIO_BITMASK (0x1FFFFFFF) to
    347365 *              return all data direction bits of the port.
    348366 *
    349  * \retval      uint32_t \n Individual bits are: \n \b 0 - The signal is 
     367 * \retval      uint32_t \n Individual bits are: \n \b 0 - The signal is
    350368 *              configured as an input.
    351369 *              \n \b 1 - The signal is configured as an output.
     
    368386 *              not changed.
    369387 * \param       val
    370  *              The 32-bit word to write to the GPIO outputs. Only the 29 LSBs 
     388 *              The 32-bit word to write to the GPIO outputs. Only the 29 LSBs
    371389 *              are used. Setting the three MSBs causes an error.
    372390 *
     
    388406 *              The GPIO port identifier.
    389407 * \param       mask
    390  *              The group of bits (where mask bits equal one) to return. Other 
    391  *              bits (where mask bits equal zero) are returned as zero. Specify 
     408 *              The group of bits (where mask bits equal one) to return. Other
     409 *              bits (where mask bits equal zero) are returned as zero. Specify
    392410 *              mask = ALT_GPIO_BITMASK (0x1FFFFFFF) to return all data bits of
    393411 *              the port.
     
    409427/******************************************************************************/
    410428/*!
    411  * Sets edge-triggered or level-triggered interrupt configuration for the 
     429 * Sets edge-triggered or level-triggered interrupt configuration for the
    412430 * specified signals of the specified GPIO module.
    413431 *
     
    416434 *              The GPIO port identifier.
    417435 * \param       mask
    418  *              The group of bits (where mask bits equal one) to apply this 
     436 *              The group of bits (where mask bits equal one) to apply this
    419437 *              operation to. Other bits (where mask bits equal zero) are
    420438 *              not changed. Specify mask = ALT_GPIO_BITMASK (0x1FFFFFFF) to
    421439 *              configure all interrupt type bits of the port.
    422440 * \param       config
    423  *              The interrupt configuration to write. Individual bits 
    424  *              are: \n \b 0 - Set the 
    425  *              interrupt for this bit to be level-sensitive (default). \n \b 
     441 *              The interrupt configuration to write. Individual bits
     442 *              are: \n \b 0 - Set the
     443 *              interrupt for this bit to be level-sensitive (default). \n \b
    426444 *              1 - Set the interrupt for this bit to be edge-sensitive.
    427445 *
     
    435453/******************************************************************************/
    436454/*!
    437  * Returns the interrupt configuration (edge-triggered or level-triggered) for 
    438  * the specified bits of the specified GPIO module. 
     455 * Returns the interrupt configuration (edge-triggered or level-triggered) for
     456 * the specified bits of the specified GPIO module.
    439457 *
    440458 * \param       gpio_pid
    441459 *              The GPIO port identifier.
    442460 * \param       mask
    443  *              The group of bits (where mask bits equal one) to return. Other 
    444  *              bits (where mask bits equal zero) are returned as zero. Specify 
     461 *              The group of bits (where mask bits equal one) to return. Other
     462 *              bits (where mask bits equal zero) are returned as zero. Specify
    445463 *              mask = ALT_GPIO_BITMASK (0x1FFFFFFF) to return all configuration
    446464 *              bits of the port.
    447465 * \retval      uint32_t
    448  *              The current interrupt source configuration. Individual bits 
    449  *              are: \n \b 0 - The interrupt for this bit is set to be 
    450  *              level-sensitive. \n \b 1 - 
     466 *              The current interrupt source configuration. Individual bits
     467 *              are: \n \b 0 - The interrupt for this bit is set to be
     468 *              level-sensitive. \n \b 1 -
    451469 *              The interrupt for this bit is set to be edge-sensitive.
    452470 *
     
    464482 *              The GPIO port identifier.
    465483 * \param       mask
    466  *              The group of bits (where mask bits equal one) to apply this 
     484 *              The group of bits (where mask bits equal one) to apply this
    467485 *              operation to. Other bits (where mask bits equal zero) are
    468486 *              not changed.
    469487 * \param       config
    470  *              The interrupt polarity configuration to set. Individual bits 
    471  *              are: \n \b 0 - Set the interrupt polarity for this bit to 
     488 *              The interrupt polarity configuration to set. Individual bits
     489 *              are: \n \b 0 - Set the interrupt polarity for this bit to
    472490 *              active-low or falling-edge mode (default). \n \b 1 - Set the
    473491 *              interrupt polarity for this bit to active-high or rising-edge mode.
     
    482500/******************************************************************************/
    483501/*!
    484  * Returns the active-high or active-low polarity configuration for the 
     502 * Returns the active-high or active-low polarity configuration for the
    485503 * possible interrupt sources of the specified GPIO module.
    486504 *
     
    489507 *              The GPIO port identifier.
    490508 * \param       mask
    491  *              The group of bits (where mask bits equal one) to return. Other 
    492  *              bits (where mask bits equal zero) are returned as zero. Specify 
     509 *              The group of bits (where mask bits equal one) to return. Other
     510 *              bits (where mask bits equal zero) are returned as zero. Specify
    493511 *              mask = ALT_GPIO_BITMASK (0x1FFFFFFF) to return all the
    494512 *              configuration bits of the port.
    495  *                 
     513 *
    496514 * \retval      uint32_t
    497  *              The current polarity configuration. Individual bits are: \n 
    498  *              \b 0 = The interrupt polarity for this bit is set to 
     515 *              The current polarity configuration. Individual bits are: \n
     516 *              \b 0 = The interrupt polarity for this bit is set to
    499517 *              active-low or falling-edge mode. \n \b 1 = The interrupt
    500518 *              polarity for this bit is set to active-high or rising-edge mode.
     
    513531/******************************************************************************/
    514532/*!
    515  * Sets the debounce configuration for input signals of the specified GPIO 
     533 * Sets the debounce configuration for input signals of the specified GPIO
    516534 * module. If debounce is selected, metastability flip-flops are inserted to
    517535 * debounce signals presented to the GPIO inputs. A signal must be steady for
     
    522540 *              The GPIO port identifier.
    523541 * \param       mask
    524  *              The group of bits (where mask bits equal one) to apply this 
     542 *              The group of bits (where mask bits equal one) to apply this
    525543 *              operation to. Other bits (where mask bits equal zero) are
    526544 *              not changed. Specify mask = ALT_GPIO_BITMASK (0x1FFFFFFF) to
     
    528546 * \param       config
    529547 *              The debounce configuration to set. Individual bits are: \n
    530  *              \b 0 - Debounce is not selected for this signal (default). \n 
     548 *              \b 0 - Debounce is not selected for this signal (default). \n
    531549 *              \b 1 - Debounce is selected for this signal.
    532550 *
     
    547565 *              The GPIO port identifier.
    548566 * \param       mask
    549  *              The group of bits (where mask bits equal one) to return. Other 
    550  *              bits (where mask bits equal zero) are returned as zero. Specify 
     567 *              The group of bits (where mask bits equal one) to return. Other
     568 *              bits (where mask bits equal zero) are returned as zero. Specify
    551569 *              mask = ALT_GPIO_BITMASK (0x1FFFFFFF) to return all debounce
    552570 *              configuration bits of the port.
    553  *                 
     571 *
    554572 * \retval      uint32_t
    555  *              The current debounce configuration.Individual bits are: \n 
    556  *              \b 0 - Debounce is not selected for this signal. \n \b 1 - 
     573 *              The current debounce configuration.Individual bits are: \n
     574 *              \b 0 - Debounce is not selected for this signal. \n \b 1 -
    557575 *              Debounce is selected for this signal.
    558576 *
     
    563581/******************************************************************************/
    564582/*!
    565  * Sets the synchronization configuration for the signals of the specified 
    566  * GPIO register. This allows for synchronizing level-sensitive interrupts to 
     583 * Sets the synchronization configuration for the signals of the specified
     584 * GPIO register. This allows for synchronizing level-sensitive interrupts to
    567585 * an internal clock signal. This is a port-wide option that controls all
    568586 * level-sensitive interrupt signals of that GPIO port.
     
    573591 *              \n \b Any \b non-zero \b value - Synchronize to internal clock signal.
    574592 *              \n \b Zero - Do not synchronize to internal clock signal.
    575  * 
     593 *
    576594 *
    577595 * \retval      ALT_E_SUCCESS   The operation was successful.
     
    585603/*!
    586604 *
    587  * Returns the synchronization configuration for the signals of the 
    588  * specified GPIO register. This allows for synchronizing level-sensitive 
     605 * Returns the synchronization configuration for the signals of the
     606 * specified GPIO register. This allows for synchronizing level-sensitive
    589607 * interrupts to the internal clock signal. This is a port-wide option that
    590608 * controls all level-sensitive interrupt signals of that GPIO port.
     
    606624 * Configures a group of GPIO signals with identical setup parameters. Allows
    607625 * for configuring all parameters of a given port at one time.
    608  * 
     626 *
    609627 * \param       gpio_pid
    610628 *              The GPIO port identifier.
     
    622640 * \param       data
    623641 *              Set the data output to this value.
    624  *                 
     642 *
    625643 * \retval      ALT_E_SUCCESS   The operation was successful.
    626644 * \retval      ALT_E_ERROR     The operation failed.
    627645 * \retval      ALT_E_BAD_ARG   Invalid input argument.
    628        
     646
    629647 */
    630648ALT_STATUS_CODE alt_gpio_port_config(ALT_GPIO_PORT_t gpio_pid,
     
    700718 *              The GPIO port identifier.
    701719 * \param       mask
    702  *              Which bits to change among the port \n \b 0 = 
     720 *              Which bits to change among the port \n \b 0 =
    703721 *              Do not change this bit. \n \b 1 = Allow this bit to change.
    704722 * \param       val
    705  *              The interrupt mask to write. Individual bits are: \n \b 0 = 
    706  *              Do not mask the interrupt for this bit (default). \n \b 1 = 
     723 *              The interrupt mask to write. Individual bits are: \n \b 0 =
     724 *              Do not mask the interrupt for this bit (default). \n \b 1 =
    707725 *              Mask the interrupt for this bit.
    708726 *
     
    721739 * \param       gpio_pid
    722740 *              The GPIO port identifier.
    723  *                 
     741 *
    724742 * \retval      uint32_t
    725  *              The interrupt mask that was read. Individual bits are: \n 
    726  *              \b 0 = The interrupt for this bit is not masked. \n \b 1 = The 
     743 *              The interrupt mask that was read. Individual bits are: \n
     744 *              \b 0 = The interrupt for this bit is not masked. \n \b 1 = The
    727745 *              interrupt for this bit is masked.
    728746 *
     
    732750/******************************************************************************/
    733751/*!
    734  * Returns the interrupt pending status of all signals of the specified GPIO 
     752 * Returns the interrupt pending status of all signals of the specified GPIO
    735753 * register.
    736754 *
     
    738756 * \param       gpio_pid
    739757 *              The GPIO port identifier.
    740  
     758
    741759 * \retval      uint32_t
    742  *              The current interrupt pending status. Individual bits are: \n 
    743  *              \b 0 - The interrupt for this bit is not pending. \n \b 1 - 
     760 *              The current interrupt pending status. Individual bits are: \n
     761 *              \b 0 - The interrupt for this bit is not pending. \n \b 1 -
    744762 *              The interrupt for this bit is pending.
    745763 *
     
    749767/******************************************************************************/
    750768/*!
    751  * Clear the interrupt pending status of selected signals of the 
     769 * Clear the interrupt pending status of selected signals of the
    752770 * specified GPIO register.
    753771 *
     
    756774 *              The GPIO port identifier.
    757775 * \param       clrmask
    758  *              The interrupt bits to clear. Individual bits are: \n \b 0 - 
    759  *              The interrupt for this bit will not be changed. \n \b 1 - 
     776 *              The interrupt bits to clear. Individual bits are: \n \b 0 -
     777 *              The interrupt for this bit will not be changed. \n \b 1 -
    760778 *              The interrupt for this bit will be cleared.
    761779 *
     
    10301048/*!
    10311049 * Configures all parameters for one bit (signal) of the GPIO ports.
    1032  * 
     1050 *
    10331051 * \param       signal_num
    10341052 *              The GPIO port signal index.
     
    10441062 *              If the GPIO signal is set to be an output, set it to
    10451063 *              this value
    1046  *                 
     1064 *
    10471065 * \retval      ALT_E_SUCCESS   The operation was successful.
    10481066 * \retval      ALT_E_ERROR     The operation failed.
     
    10571075/*!
    10581076 * Returns the configuration parameters of a given GPIO bit.
    1059  * 
     1077 *
    10601078 * \param       signal_num
    10611079 *              The GPIO port signal index.
     
    10631081 *              Pointer to a single GPIO_CONFIG_RECORD_s configuration record.
    10641082 *              The fields of this configuration record are filled in
    1065  *              by the function.         
    1066  *                 
     1083 *              by the function.
     1084 *
    10671085 * \retval      ALT_E_SUCCESS   The operation was successful.
    10681086 * \retval      ALT_E_ERROR     The operation failed.
    10691087 * \retval      ALT_E_BAD_ARG   Invalid input argument.
    1070        
     1088
    10711089 */
    10721090ALT_STATUS_CODE alt_gpio_bitconfig_get(ALT_GPIO_1BIT_t signal_num,
     
    10751093/******************************************************************************/
    10761094/*!
    1077  * Configures a list of GPIO bits. The GPIO bits do not have to be 
    1078  * configured the same, as was the case for the mask version of this function, 
     1095 * Configures a list of GPIO bits. The GPIO bits do not have to be
     1096 * configured the same, as was the case for the mask version of this function,
    10791097 * alt_gpio_port_config(). Each bit may be configured differently and bits may
    10801098 * be listed in any order.
    1081  * 
     1099 *
    10821100 * \param       config_array
    10831101 *              Pointer to an array of GPIO_CONFIG_RECORD_s configuration
    10841102 *              records. These definitions contain all the parameters
    1085  *              needed to set up the listed pins. All or 
    1086  *              any subset of the GPIO signals can be configured. Signals do 
    1087  *              not have to be listed in numerical order or be unique. If a 
    1088  *              signal number is listed multiple times, the last configuration 
     1103 *              needed to set up the listed pins. All or
     1104 *              any subset of the GPIO signals can be configured. Signals do
     1105 *              not have to be listed in numerical order or be unique. If a
     1106 *              signal number is listed multiple times, the last configuration
    10891107 *              listed is used. \n Configuration terminates either when \b len
    10901108 *              signals have been configured or if the next signal number index
    10911109 *              in the array is equal to \b ALT_END_OF_GPIO_SIGNALS (-1).
    1092  *             
     1110 *
    10931111 * \param       len
    1094  *              Length of array to configure. 
    1095  *                 
     1112 *              Length of array to configure.
     1113 *
    10961114 * \retval      ALT_E_SUCCESS   The operation was successful.
    10971115 * \retval      ALT_E_ERROR     The operation failed.
    10981116 * \retval      ALT_E_BAD_ARG   Invalid input argument.
    1099        
     1117
    11001118 */
    11011119ALT_STATUS_CODE alt_gpio_group_config(ALT_GPIO_CONFIG_RECORD_t* config_array,
     
    11041122/******************************************************************************/
    11051123/*!
    1106  * Returns a list of the pin signal indices and the associated configuration 
     1124 * Returns a list of the pin signal indices and the associated configuration
    11071125 * settings (data direction, interrupt type, polarity, and debounce) of that
    11081126 * list of signals.
    1109  * 
     1127 *
    11101128 * \param       config_array
    11111129 *              Pointer to an array of ALT_GPIO_CONFIG_RECORD_t configuration
     
    11141132 *              fill in all the other fields of the configuration record,
    11151133 *              returning all configuration parameters in the array.
    1116  *              Signals do not have to be listed in numerical order or be 
    1117  *              unique. If a signal number is listed multiple times, the 
     1134 *              Signals do not have to be listed in numerical order or be
     1135 *              unique. If a signal number is listed multiple times, the
    11181136 *              configuration record will contain multiple entries for
    11191137 *              that signal. \n Configuration reading terminates either when
     
    11221140 *              \b ALT_END_OF_GPIO_SIGNALS (-1).
    11231141 * \param       len
    1124  *              Length of configuration array to read and return. 
    1125  *                 
    1126  *                 
     1142 *              Length of configuration array to read and return.
     1143 *
     1144 *
    11271145 * \retval      ALT_E_SUCCESS   The operation was successful.
    11281146 * \retval      ALT_E_ERROR     The operation failed.
    11291147 * \retval      ALT_E_BAD_ARG   Invalid input argument.
    1130        
     1148
    11311149 */
    11321150ALT_STATUS_CODE alt_gpio_group_config_get(ALT_GPIO_CONFIG_RECORD_t *config_array,
     
    11411159 * signal indices instead of having the signal list provided in the first
    11421160 * field of the configuration records in the array.
    1143  *               
     1161 *
    11441162 * \param       pinid_array
    11451163 *              Pointer to a list of signal index numbers. These indices
     
    11481166 * \param       config_array
    11491167 *              Pointer to an array of ALT_GPIO_CONFIG_RECORD_t configuration
    1150  *              records. This function will fill in the fields of the 
    1151  *              configuration record, returning all configuration parameters 
    1152  *              in the array. Signals do not have to be listed in numerical 
    1153  *              order or be unique. If a signal number is listed multiple 
    1154  *              times, the configuration record array will contain multiple 
     1168 *              records. This function will fill in the fields of the
     1169 *              configuration record, returning all configuration parameters
     1170 *              in the array. Signals do not have to be listed in numerical
     1171 *              order or be unique. If a signal number is listed multiple
     1172 *              times, the configuration record array will contain multiple
    11551173 *              identical entries for that signal. \n Configuration reading
    11561174 *              terminates either when \b len signal configurations have been
     
    11581176 *              to \b ALT_END_OF_GPIO_SIGNALS (-1).
    11591177 * \param       len
    1160  *              Length of configuration array to read. 
    1161  *                 
    1162  *                 
     1178 *              Length of configuration array to read.
     1179 *
     1180 *
    11631181 * \retval      ALT_E_SUCCESS   The operation was successful.
    11641182 * \retval      ALT_E_ERROR     The operation failed.
    11651183 * \retval      ALT_E_BAD_ARG   Invalid input argument.
    1166  *         
     1184 *
    11671185 */
    11681186ALT_STATUS_CODE alt_gpio_group_config_get2(ALT_GPIO_1BIT_t* pinid_array,
     
    12191237/******************************************************************************/
    12201238/*!
    1221  * Extracts the GPIO Signal Index Number from the supplied GPIO port ID and 
    1222  * signal mask. If passed a bitmask composed of more than one signal, the 
     1239 * Extracts the GPIO Signal Index Number from the supplied GPIO port ID and
     1240 * signal mask. If passed a bitmask composed of more than one signal, the
    12231241 * signal number of the lowest bit in the bitmask presented is returned.
    1224  * 
     1242 *
    12251243 */
    12261244ALT_GPIO_1BIT_t alt_gpio_port_pin_to_bit(ALT_GPIO_PORT_t pid,
  • c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_hwlibs_ver.h

    r96ec8ee8 r9907dde  
    3737 ***********************************************************************/
    3838
    39 /* This is the major revision of the Altera ACDS Release    */
     39/* This is the major revision of the Altera ACDS Release        */
    4040#define ALTERA_ACDS_MAJOR_REV           13
    4141
    42 /* This is the minor revision of the Altera ACDS Release    */
    43 #define ALTERA_ACDS_MINOR_REV            0
     42/* This is the minor revision of the Altera ACDS Release        */
     43#define ALTERA_ACDS_MINOR_REV            1
    4444
    45 /* This is an internal HwLibs revision control code.        */
    46 /* End-users should NOT depend upon the value of this field */
     45/* This is an internal HwLibs revision/feature control code.    */
     46/* End-users should NOT depend upon the value of this field     */
    4747#define ALTERA_HWLIBS_REV                0
    4848
    4949/* This is a text string containing the current release and service pack IDs */
    50 #define ALTERA_ACDS_REV_STR             "13.0SP1"
     50#define ALTERA_ACDS_REV_STR             "13.1"
     51
     52/* This is a text string containing the current SoC EDS ID              */
     53#define ALTERA_SOCEDS_REV_STR           "Altera SoC Embedded Design Suite v13.1"
     54
    5155
    5256#endif   /* __ALT_HWLIBS_VER_H__ */
  • c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_interrupt_common.h

    r96ec8ee8 r9907dde  
    344344    /*!<
    345345     * Interrupts sourced from the SPI Controllers 0 - 3.
     346     * SPI0_IRQ corresponds to SPIM0. SPI1_IRQ corresponds to SPIM1.
     347     * SPI2_IRQ corresponds to SPIS0. SPI3_IRQ corresponds to SPIS1.
    346348     *  * All interrupts in this group are level triggered.
    347349     */
  • c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_reset_manager.h

    r96ec8ee8 r9907dde  
    240240                                     bool etr_stall);
    241241
     242#if 0
     243/*! \addtogroup RST_MGR_MPU
     244 *
     245 * This functional group provides reset control for the Cortex-A9 MPU module.
     246 *
     247 * @{
     248 */
     249
     250/*! @} */
     251
     252/*! \addtogroup RST_MGR_PERIPH
     253 *
     254 * This functional group provides inidividual reset control for the HPS
     255 * peripheral modules.
     256 *
     257 * @{
     258 */
     259
     260/*! @} */
     261
     262/*! \addtogroup RST_MGR_BRG
     263 *
     264 * This functional group provides inidividual reset control for the bridge
     265 * interfaces between the HPS and FPGA.
     266 *
     267 * @{
     268 */
     269
     270/*! @} */
     271
     272/*! \addtogroup RST_MGR_MISC
     273 *
     274 * This functional group provides inidividual reset control for miscellaneous
     275 * HPS modules.
     276 *
     277 * @{
     278 */
     279
     280/*! @} */
     281
     282#endif
     283
    242284/*! @} */
    243285
  • c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/hwlib.h

    r96ec8ee8 r9907dde  
    9191/*! The buffer does not contain enough free space for the operation. */
    9292#define ALT_E_BUF_OVF               (-20)
    93 
    9493
    9594/*!
  • c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/socal/socal.h

    r96ec8ee8 r9907dde  
    1 /*******************************************************************************
    2 *                                                                              *
    3 * Copyright 2013 Altera Corporation. All Rights Reserved.                      *
    4 *                                                                              *
    5 * Redistribution and use in source and binary forms, with or without           *
    6 * modification, are permitted provided that the following conditions are met:  *
    7 *                                                                              *
    8 * 1. Redistributions of source code must retain the above copyright notice,    *
    9 *    this list of conditions and the following disclaimer.                     *
    10 *                                                                              *
    11 * 2. Redistributions in binary form must reproduce the above copyright notice, *
    12 *    this list of conditions and the following disclaimer in the documentation *
    13 *    and/or other materials provided with the distribution.                    *
    14 *                                                                              *
    15 * 3. The name of the author may not be used to endorse or promote products     *
    16 *    derived from this software without specific prior written permission.     *
    17 *                                                                              *
    18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR *
    19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF *
    20 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO  *
    21 * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,       *
    22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, *
    23 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;  *
    24 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,     *
    25 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR      *
    26 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF       *
    27 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                                   *
    28 *                                                                              *
    29 *******************************************************************************/
     1/******************************************************************************
     2 *
     3 * Copyright 2013 Altera Corporation. All Rights Reserved.
     4 *
     5 * Redistribution and use in source and binary forms, with or without
     6 * modification, are permitted provided that the following conditions are met:
     7 *
     8 * 1. Redistributions of source code must retain the above copyright notice,
     9 * this list of conditions and the following disclaimer.
     10 *
     11 * 2. Redistributions in binary form must reproduce the above copyright notice,
     12 * this list of conditions and the following disclaimer in the documentation
     13 * and/or other materials provided with the distribution.
     14 *
     15 * 3. The name of the author may not be used to endorse or promote products
     16 * derived from this software without specific prior written permission.
     17 *
     18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR
     19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
     20 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO
     21 * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
     22 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
     23 * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
     26 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
     27 * OF SUCH DAMAGE.
     28 *
     29 ******************************************************************************/
     30
    3031
    3132/*! \file Altera - ALT_SOCAL */
     
    3435#define __ALTERA_SOCAL_H__
    3536
    36 #include <rtems/score/basedefs.h>
     37#ifndef __ASSEMBLY__
     38#ifdef __cplusplus
     39#include <cstddef>
     40#include <cstdbool>
     41#include <cstdint>
     42#else   /* __cplusplus */
     43#include <stddef.h>
     44#include <stdbool.h>
     45#include <stdint.h>
     46#endif  /* __cplusplus */
     47#endif  /* __ASSEMBLY__ */
    3748
    3849#ifdef __cplusplus
     
    6172#define ALT_CAST(type, ptr)  ((type) (ptr))
    6273#endif  /* __ASSEMBLY__ */
    63 
    6474
    6575/*!
     
    240250#define     alt_replbits_dword(dest, msk, src)   (alt_write_dword(dest,(alt_read_dword(dest) & ~(msk)) | ((src) & (msk))))
    241251
    242 
    243 
    244252/*! @} */
    245253
    246 /*!
    247  * \addtogroup ALT_SOCAL_TYPE_IND_FUNC SoCAL Indirect (pointer-based) Utilities
    248  *
    249  * This section implements two other useful forms of the alt_write_*() macros above that
    250  * are preferable to use in some situations. These use an intermediate pointer (defined
    251  * in the containing compile unit) to move data in an indirect manner. These compile to very
    252  * tight ARM code, equivalent to the above versions.
    253  *
    254  * @{
    255  */
    256 
    257 /*! Write the 8 bit byte to the destination address in device memory.
    258  *  \param dest  - Write destination pointer address
    259  *  \param tmptr - Temporary pointer to byte data
    260  *  \param src   - 8 bit data value to write to memory
    261  */
    262 #define alt_indwrite_byte(dest, tmptr, src)  {(tmptr)=ALT_CAST(uint8_t*,(dest));(*ALT_CAST(volatile uint8_t*,(tmptr))=(src));}
    263 
    264 /*! Write the 8 bit byte to the destination address in device memory.
    265  *  \param dest  - Write destination pointer address
    266  *  \param tmptr - Temporary pointer to byte data
    267  *  \param src   - Read destination pointer address
    268  */
    269 #define alt_indread_byte(dest, tmptr, src)   {(tmptr)=ALT_CAST(uint8_t*,(src));(*ALT_CAST(volatile uint8_t*,(dest))=*(tmptr));}
    270 
    271 /*! Write the 16 bit halfword to the destination address in device memory.
    272  *  \param dest  - Write destination pointer address
    273  *  \param tmptr - Temporary pointer to halfword data
    274  *  \param src   - 16 bit data value to write to memory
    275  */
    276 #define alt_indwrite_hword(dest, tmptr, src) {(tmptr)=ALT_CAST(uint16_t*,(dest));(*ALT_CAST(volatile uint16_t*,(tmptr))=(src));}
    277 
    278 /*! Write the 16 bit halfword to the destination address in device memory.
    279  *  \param dest  - Write destination pointer address
    280  *  \param tmptr - Temporary pointer to halfword data
    281  *  \param src   - Read destination pointer address
    282  */
    283 #define alt_indread_hword(dest, tmptr, src)  {(tmptr)=ALT_CAST(uint16_t*,(src));(*ALT_CAST(volatile uint16_t*,(dest))=*(tmptr));}
    284 
    285 /*! Write the 32 bit word to the destination address in device memory.
    286  *  \param dest  - Write destination pointer address
    287  *  \param tmptr - Temporary pointer to word data
    288  *  \param src   - 32 bit data value to write to memory
    289  */
    290 #define alt_indwrite_word(dest, tmptr, src)  {(tmptr)=ALT_CAST(uint32_t*,(dest));(*ALT_CAST(volatile uint32_t*,(tmptr))=(src));}
    291 
    292 /*! Write the 32 bit word to the destination address in device memory.
    293  *  \param dest  - Write destination pointer address
    294  *  \param tmptr - Temporary pointer to word data
    295  *  \param src   - Read destination pointer address
    296  */
    297 #define alt_indread_word(dest, tmptr, src)   {(tmptr)=ALT_CAST(uint32_t*,(src));(*ALT_CAST(volatile uint32_t*,(dest))=*(tmptr));}
    298 
    299 /*! Write the 64 bit dword to the destination address in device memory.
    300  *  \param dest  - Write destination pointer address
    301  *  \param tmptr - Temporary pointer to double-word data
    302  *  \param src   - 64 bit data value to write to memory
    303  */
    304 #define alt_indwrite_dword(dest, tmptr, src) {(tmptr)=ALT_CAST(uint64_t*,(dest));(*ALT_CAST(volatile uint64_t*,(tmptr))=(src));}
    305 
    306 /*! Write the 64 bit dword to the destination address in device memory.
    307  *  \param dest  - Write destination pointer address
    308  *  \param tmptr - Temporary pointer to double-word data
    309  *  \param src   - Read destination pointer address
    310  */
    311 #define alt_indread_dword(dest, tmptr, src)  {(tmptr)=ALT_CAST(uint64_t*,(src));(*ALT_CAST(volatile uint64_t*,(dest))=*(tmptr));}
    312 
    313 
    314 /*! @} */
    315 
    316 /*!
    317  * \addtogroup ALT_SOCAL_CMPL_ASRT_FUNC SoCAL Compile Assert Utilities
    318  *
    319  * This section implements an assert-type functionality in the compiler rather than in the
    320  * debug run-time code. Additional macros can be built on the basic structure and defined
    321  * to test various conditions and throw a compile-time error if necessary.
    322  *
    323  * @{
    324  */
    325 
    326 /*! alt_cat_compile_assert_text() concatenates text.
    327  *  \param txta - The first text fragment to be joined
    328  *  \param txtb - The second text fragment to be joined
    329  */
    330 #define alt_cat_compile_assert_text(txta, txtb) txta##txtb
    331 
    332 /*! alt_form_compile_assert_line() is the basis of other functions that check various
    333  *  conditions and possibly throw a compile-time error in response, giving an
    334  *  assert equivalent that operates at compile time rather than at run-time.
    335  *  \param test - Any valid boolean expression
    336  *  \param file - The filename where this expression is located (ASCII string)
    337  *  \param line - The line number where this expression is located
    338  */
    339 #define alt_form_compile_assert_line(test, file, line) \
    340 typedef char alt_cat_compile_assert_text(assertion_at_##file##_line_, line)[2*!!(test)-1]
    341 
    342 /*! alt_check_struct_size() throws a compile-time error if the structure size (a) is
    343  *  larger than the size of the reference (b). \n
    344  *  alt_check_struct_size() works with groups of bitfields up to much larger
    345  *  structure sizes.
    346  *  \param a - Structure to be evaluated
    347  *  \param b - Reference size
    348  */
    349 #define alt_check_struct_size(a, b) RTEMS_STATIC_ASSERT((sizeof(a) <= sizeof(b)), Invalid_stuct_size)
    350 
    351 
    352 /*! @} */
    353254/*! @} */
    354255
  • c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/src/hwmgr/alt_address_space.c

    r96ec8ee8 r9907dde  
    1 
    21/******************************************************************************
    3 *
    4 * alt_address_space.c - API for the Altera SoC FPGA address space.
    5 *
    6 ******************************************************************************/
     2 *
     3 * alt_address_space.c - API for the Altera SoC FPGA address space.
     4 *
     5 ******************************************************************************/
    76
    87/******************************************************************************
    9 *
    10 * Copyright 2013 Altera Corporation. All Rights Reserved.
    11 *
    12 * Redistribution and use in source and binary forms, with or without
    13 * modification, are permitted provided that the following conditions are met:
    14 *
    15 * 1. Redistributions of source code must retain the above copyright notice,
    16 * this list of conditions and the following disclaimer.
    17 *
    18 * 2. Redistributions in binary form must reproduce the above copyright notice,
    19 * this list of conditions and the following disclaimer in the documentation
    20 * and/or other materials provided with the distribution.
    21 *
    22 * 3. The name of the author may not be used to endorse or promote products
    23 * derived from this software without specific prior written permission.
    24 *
    25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR
    26 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
    27 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO
    28 * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
    29 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
    30 * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
    31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
    32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
    33 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
    34 * OF SUCH DAMAGE.
    35 *
    36 ******************************************************************************/
     8 *
     9 * Copyright 2013 Altera Corporation. All Rights Reserved.
     10 *
     11 * Redistribution and use in source and binary forms, with or without
     12 * modification, are permitted provided that the following conditions are met:
     13 *
     14 * 1. Redistributions of source code must retain the above copyright notice,
     15 * this list of conditions and the following disclaimer.
     16 *
     17 * 2. Redistributions in binary form must reproduce the above copyright notice,
     18 * this list of conditions and the following disclaimer in the documentation
     19 * and/or other materials provided with the distribution.
     20 *
     21 * 3. The name of the author may not be used to endorse or promote products
     22 * derived from this software without specific prior written permission.
     23 *
     24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR
     25 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
     26 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO
     27 * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
     28 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
     29 * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
     32 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
     33 * OF SUCH DAMAGE.
     34 *
     35 ******************************************************************************/
    3736
    3837#include <stddef.h>
     
    4039#include "socal/alt_l3.h"
    4140#include "socal/socal.h"
    42 
     41#include "socal/alt_acpidmap.h"
     42#include "hwlib.h"
     43
     44
     45#define ALT_ACP_ID_MAX_INPUT_ID     7
     46#define ALT_ACP_ID_MAX_OUTPUT_ID    4096
    4347
    4448/******************************************************************************/
     
    155159    // Address filtering start and end values must be 1 MB aligned.
    156160    if (  (addr_filt_start & ~L2_CACHE_ADDR_FILTERING_START_ADDR_MASK)
    157        || (addr_filt_end & ~L2_CACHE_ADDR_FILTERING_END_ADDR_MASK)  )
     161       || (addr_filt_end   & ~L2_CACHE_ADDR_FILTERING_END_ADDR_MASK)  )
    158162    {
    159163        return ALT_E_ARG_RANGE;
     
    182186
    183187/******************************************************************************/
    184 /******************************************************************************/
     188ALT_STATUS_CODE alt_acp_id_map_fixed_read_set(const uint32_t input_id,
     189                                              const uint32_t output_id,
     190                                              const ALT_ACP_ID_MAP_PAGE_t page,
     191                                              const uint32_t aruser)
     192{
     193    if (input_id > ALT_ACP_ID_OUT_DYNAM_ID_7 || output_id == ALT_ACP_ID_MAX_OUTPUT_ID)
     194    {
     195        return ALT_E_BAD_ARG;
     196    }
     197
     198    switch (output_id)
     199    {
     200    case ALT_ACP_ID_OUT_FIXED_ID_2:
     201        alt_write_word(ALT_ACPIDMAP_VID2RD_ADDR,
     202                         ALT_ACPIDMAP_VID2RD_MID_SET(input_id)
     203                       | ALT_ACPIDMAP_VID2RD_PAGE_SET(page)
     204                       | ALT_ACPIDMAP_VID2RD_USER_SET(aruser)
     205                       | ALT_ACPIDMAP_VID2RD_FORCE_SET(1UL));
     206        break;
     207    case ALT_ACP_ID_OUT_DYNAM_ID_3:
     208        alt_write_word(ALT_ACPIDMAP_VID3RD_ADDR,
     209                         ALT_ACPIDMAP_VID3RD_MID_SET(input_id)
     210                       | ALT_ACPIDMAP_VID3RD_PAGE_SET(page)
     211                       | ALT_ACPIDMAP_VID3RD_USER_SET(aruser)
     212                       | ALT_ACPIDMAP_VID3RD_FORCE_SET(1UL));
     213        break;
     214    case ALT_ACP_ID_OUT_DYNAM_ID_4:
     215        alt_write_word(ALT_ACPIDMAP_VID4RD_ADDR,
     216                         ALT_ACPIDMAP_VID4RD_MID_SET(input_id)
     217                       | ALT_ACPIDMAP_VID4RD_PAGE_SET(page)
     218                       | ALT_ACPIDMAP_VID4RD_USER_SET(aruser)
     219                       | ALT_ACPIDMAP_VID4RD_FORCE_SET(1UL));
     220        break;
     221    case ALT_ACP_ID_OUT_DYNAM_ID_5:
     222        alt_write_word(ALT_ACPIDMAP_VID5RD_ADDR,
     223                         ALT_ACPIDMAP_VID5RD_MID_SET(input_id)
     224                       | ALT_ACPIDMAP_VID5RD_PAGE_SET(page)
     225                       | ALT_ACPIDMAP_VID5RD_USER_SET(aruser)
     226                       | ALT_ACPIDMAP_VID5RD_FORCE_SET(1UL));
     227        break;
     228    case ALT_ACP_ID_OUT_DYNAM_ID_6:
     229        alt_write_word(ALT_ACPIDMAP_VID6RD_ADDR,
     230                         ALT_ACPIDMAP_VID6RD_MID_SET(input_id)
     231                       | ALT_ACPIDMAP_VID6RD_PAGE_SET(page)
     232                       | ALT_ACPIDMAP_VID6RD_USER_SET(aruser)
     233                       | ALT_ACPIDMAP_VID6RD_FORCE_SET(1UL));
     234        break;
     235    default:
     236        return ALT_E_BAD_ARG;
     237    }
     238
     239    return ALT_E_SUCCESS;
     240}
     241
     242/******************************************************************************/
     243ALT_STATUS_CODE alt_acp_id_map_fixed_write_set(const uint32_t input_id,
     244                                               const uint32_t output_id,
     245                                               const ALT_ACP_ID_MAP_PAGE_t page,
     246                                               const uint32_t awuser)
     247{
     248    if (input_id > ALT_ACP_ID_OUT_DYNAM_ID_7 || output_id == ALT_ACP_ID_MAX_OUTPUT_ID)
     249    {
     250        return ALT_E_BAD_ARG;
     251    }
     252
     253    switch (output_id)
     254    {
     255    case ALT_ACP_ID_OUT_FIXED_ID_2:
     256        alt_write_word(ALT_ACPIDMAP_VID2WR_ADDR,
     257                         ALT_ACPIDMAP_VID2WR_MID_SET(input_id)
     258                       | ALT_ACPIDMAP_VID2WR_PAGE_SET(page)
     259                       | ALT_ACPIDMAP_VID2WR_USER_SET(awuser)
     260                       | ALT_ACPIDMAP_VID2WR_FORCE_SET(1UL));
     261        break;
     262    case ALT_ACP_ID_OUT_DYNAM_ID_3:
     263        alt_write_word(ALT_ACPIDMAP_VID3WR_ADDR,
     264                         ALT_ACPIDMAP_VID3WR_MID_SET(input_id)
     265                       | ALT_ACPIDMAP_VID3WR_PAGE_SET(page)
     266                       | ALT_ACPIDMAP_VID3WR_USER_SET(awuser)
     267                       | ALT_ACPIDMAP_VID3WR_FORCE_SET(1UL));
     268        break;
     269    case ALT_ACP_ID_OUT_DYNAM_ID_4:
     270        alt_write_word(ALT_ACPIDMAP_VID4WR_ADDR,
     271                         ALT_ACPIDMAP_VID4WR_MID_SET(input_id)
     272                       | ALT_ACPIDMAP_VID4WR_PAGE_SET(page)
     273                       | ALT_ACPIDMAP_VID4WR_USER_SET(awuser)
     274                       | ALT_ACPIDMAP_VID4WR_FORCE_SET(1UL));
     275        break;
     276    case ALT_ACP_ID_OUT_DYNAM_ID_5:
     277        alt_write_word(ALT_ACPIDMAP_VID5WR_ADDR,
     278                         ALT_ACPIDMAP_VID5WR_MID_SET(input_id)
     279                       | ALT_ACPIDMAP_VID5WR_PAGE_SET(page)
     280                       | ALT_ACPIDMAP_VID5WR_USER_SET(awuser)
     281                       | ALT_ACPIDMAP_VID5WR_FORCE_SET(1UL));
     282        break;
     283    case ALT_ACP_ID_OUT_DYNAM_ID_6:
     284        alt_write_word(ALT_ACPIDMAP_VID6WR_ADDR,
     285                         ALT_ACPIDMAP_VID6WR_MID_SET(input_id)
     286                       | ALT_ACPIDMAP_VID6WR_PAGE_SET(page)
     287                       | ALT_ACPIDMAP_VID6WR_USER_SET(awuser)
     288                       | ALT_ACPIDMAP_VID6WR_FORCE_SET(1UL)
     289            );
     290        break;
     291    default:
     292        return ALT_E_BAD_ARG;
     293    }
     294
     295    return ALT_E_SUCCESS;
     296}
     297
     298/******************************************************************************/
     299ALT_STATUS_CODE alt_acp_id_map_dynamic_read_set(const uint32_t output_id)
     300{
     301    if (output_id == ALT_ACP_ID_MAX_OUTPUT_ID)
     302    {
     303        return ALT_E_BAD_ARG;
     304    }
     305
     306    uint32_t aruser, page;
     307
     308    switch (output_id)
     309    {
     310    case ALT_ACP_ID_OUT_FIXED_ID_2:
     311        aruser = ALT_ACPIDMAP_VID2RD_USER_GET(alt_read_word(ALT_ACPIDMAP_VID2RD_ADDR));
     312        page = ALT_ACPIDMAP_VID2RD_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID2RD_ADDR));
     313        break;
     314    case ALT_ACP_ID_OUT_DYNAM_ID_3:
     315        aruser = ALT_ACPIDMAP_VID3RD_USER_GET(alt_read_word(ALT_ACPIDMAP_VID3RD_ADDR));
     316        page = ALT_ACPIDMAP_VID3RD_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID3RD_ADDR));
     317        break;
     318    case ALT_ACP_ID_OUT_DYNAM_ID_4:
     319        aruser = ALT_ACPIDMAP_VID4RD_USER_GET(alt_read_word(ALT_ACPIDMAP_VID4RD_ADDR));
     320        page = ALT_ACPIDMAP_VID4RD_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID4RD_ADDR));
     321        break;
     322    case ALT_ACP_ID_OUT_DYNAM_ID_5:
     323        aruser = ALT_ACPIDMAP_VID5RD_USER_GET(alt_read_word(ALT_ACPIDMAP_VID5RD_ADDR));
     324        page = ALT_ACPIDMAP_VID5RD_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID5RD_ADDR));
     325        break;
     326    case ALT_ACP_ID_OUT_DYNAM_ID_6:
     327        aruser = ALT_ACPIDMAP_VID6RD_USER_GET(alt_read_word(ALT_ACPIDMAP_VID6RD_ADDR));
     328        page = ALT_ACPIDMAP_VID6RD_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID6RD_ADDR));
     329        break;
     330    default:
     331        return ALT_E_BAD_ARG;
     332    }
     333
     334    alt_write_word(ALT_ACPIDMAP_DYNRD_ADDR,
     335                     ALT_ACPIDMAP_DYNRD_PAGE_SET(page)
     336                   | ALT_ACPIDMAP_DYNRD_USER_SET(aruser));
     337    return ALT_E_SUCCESS;
     338}
     339
     340/******************************************************************************/
     341ALT_STATUS_CODE alt_acp_id_map_dynamic_write_set(const uint32_t output_id)
     342{
     343    if (output_id == ALT_ACP_ID_MAX_OUTPUT_ID)
     344    {
     345        return ALT_E_BAD_ARG;
     346    }
     347
     348    uint32_t awuser, page;
     349
     350    switch (output_id)
     351    {
     352    case ALT_ACP_ID_OUT_FIXED_ID_2:
     353        awuser = ALT_ACPIDMAP_VID2WR_USER_GET(alt_read_word(ALT_ACPIDMAP_VID2WR_ADDR));
     354        page   = ALT_ACPIDMAP_VID2WR_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID2WR_ADDR));
     355        break;
     356    case ALT_ACP_ID_OUT_DYNAM_ID_3:
     357        awuser = ALT_ACPIDMAP_VID3WR_USER_GET(alt_read_word(ALT_ACPIDMAP_VID3WR_ADDR));
     358        page   = ALT_ACPIDMAP_VID3WR_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID3WR_ADDR));
     359        break;
     360    case ALT_ACP_ID_OUT_DYNAM_ID_4:
     361        awuser = ALT_ACPIDMAP_VID4WR_USER_GET(alt_read_word(ALT_ACPIDMAP_VID4WR_ADDR));
     362        page   = ALT_ACPIDMAP_VID4WR_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID4WR_ADDR));
     363        break;
     364    case ALT_ACP_ID_OUT_DYNAM_ID_5:
     365        awuser = ALT_ACPIDMAP_VID5WR_USER_GET(alt_read_word(ALT_ACPIDMAP_VID5WR_ADDR));
     366        page   = ALT_ACPIDMAP_VID5WR_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID5WR_ADDR));
     367        break;
     368    case ALT_ACP_ID_OUT_DYNAM_ID_6:
     369        awuser = ALT_ACPIDMAP_VID6WR_USER_GET(alt_read_word(ALT_ACPIDMAP_VID6WR_ADDR));
     370        page   = ALT_ACPIDMAP_VID6WR_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID6WR_ADDR));
     371        break;
     372    default:
     373        return ALT_E_BAD_ARG;
     374    }
     375
     376    alt_write_word(ALT_ACPIDMAP_DYNWR_ADDR,
     377                     ALT_ACPIDMAP_DYNWR_PAGE_SET(page)
     378                   | ALT_ACPIDMAP_DYNWR_USER_SET(awuser));
     379    return ALT_E_SUCCESS;
     380}
     381
     382/******************************************************************************/
     383ALT_STATUS_CODE alt_acp_id_map_dynamic_read_options_set(const ALT_ACP_ID_MAP_PAGE_t page,
     384                                                        const uint32_t aruser)
     385{
     386    alt_write_word(ALT_ACPIDMAP_DYNRD_ADDR,
     387                     ALT_ACPIDMAP_DYNRD_PAGE_SET(page)
     388                   | ALT_ACPIDMAP_DYNRD_USER_SET(aruser));
     389    return ALT_E_SUCCESS;
     390}
     391
     392/******************************************************************************/
     393ALT_STATUS_CODE alt_acp_id_map_dynamic_write_options_set(const ALT_ACP_ID_MAP_PAGE_t page,
     394                                                         const uint32_t awuser)
     395{
     396    alt_write_word(ALT_ACPIDMAP_DYNWR_ADDR,
     397                     ALT_ACPIDMAP_DYNWR_PAGE_SET(page)
     398                   | ALT_ACPIDMAP_DYNWR_USER_SET(awuser));
     399    return ALT_E_SUCCESS;
     400}
     401
     402/******************************************************************************/
     403ALT_STATUS_CODE alt_acp_id_map_read_options_get(const uint32_t output_id,
     404                                                bool * fixed,
     405                                                uint32_t * input_id,
     406                                                ALT_ACP_ID_MAP_PAGE_t * page,
     407                                                uint32_t * aruser)
     408{
     409    if (output_id == ALT_ACP_ID_MAX_OUTPUT_ID)
     410    {
     411        return ALT_E_BAD_ARG;
     412    }
     413
     414    switch (output_id)
     415    {
     416    case ALT_ACP_ID_OUT_FIXED_ID_2:
     417        *aruser   = ALT_ACPIDMAP_VID2RD_S_USER_GET(alt_read_word(ALT_ACPIDMAP_VID2RD_S_ADDR));
     418        *page     = (ALT_ACP_ID_MAP_PAGE_t)ALT_ACPIDMAP_VID2RD_S_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID2RD_S_ADDR));
     419        *input_id = ALT_ACPIDMAP_VID2RD_S_MID_GET(alt_read_word(ALT_ACPIDMAP_VID2RD_S_ADDR));
     420        *fixed    = ALT_ACPIDMAP_VID2RD_S_FORCE_GET(alt_read_word(ALT_ACPIDMAP_VID2RD_S_ADDR));
     421        break;
     422    case ALT_ACP_ID_OUT_DYNAM_ID_3:
     423        *aruser   = ALT_ACPIDMAP_VID3RD_S_USER_GET(alt_read_word(ALT_ACPIDMAP_VID3RD_S_ADDR));
     424        *page     = (ALT_ACP_ID_MAP_PAGE_t)ALT_ACPIDMAP_VID3RD_S_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID3RD_S_ADDR));
     425        *input_id = ALT_ACPIDMAP_VID3RD_S_MID_GET(alt_read_word(ALT_ACPIDMAP_VID3RD_S_ADDR));
     426        *fixed    = ALT_ACPIDMAP_VID3RD_S_FORCE_GET(alt_read_word(ALT_ACPIDMAP_VID3RD_S_ADDR));
     427        break;
     428    case ALT_ACP_ID_OUT_DYNAM_ID_4:
     429        *aruser   = ALT_ACPIDMAP_VID4RD_S_USER_GET(alt_read_word(ALT_ACPIDMAP_VID4RD_S_ADDR));
     430        *page     = (ALT_ACP_ID_MAP_PAGE_t)ALT_ACPIDMAP_VID4RD_S_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID4RD_S_ADDR));
     431        *input_id = ALT_ACPIDMAP_VID4RD_S_MID_GET(alt_read_word(ALT_ACPIDMAP_VID4RD_S_ADDR));
     432        *fixed    = ALT_ACPIDMAP_VID4RD_S_FORCE_GET(alt_read_word(ALT_ACPIDMAP_VID4RD_S_ADDR));
     433        break;
     434    case ALT_ACP_ID_OUT_DYNAM_ID_5:
     435        *aruser   = ALT_ACPIDMAP_VID5RD_S_USER_GET(alt_read_word(ALT_ACPIDMAP_VID5RD_S_ADDR));
     436        *page     = (ALT_ACP_ID_MAP_PAGE_t)ALT_ACPIDMAP_VID5RD_S_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID5RD_S_ADDR));
     437        *input_id = ALT_ACPIDMAP_VID5RD_S_MID_GET(alt_read_word(ALT_ACPIDMAP_VID5RD_S_ADDR));
     438        *fixed    = ALT_ACPIDMAP_VID5RD_S_FORCE_GET(alt_read_word(ALT_ACPIDMAP_VID5RD_S_ADDR));
     439        break;
     440    case ALT_ACP_ID_OUT_DYNAM_ID_6:
     441        *aruser   = ALT_ACPIDMAP_VID6RD_S_USER_GET(alt_read_word(ALT_ACPIDMAP_VID6RD_S_ADDR));
     442        *page     = (ALT_ACP_ID_MAP_PAGE_t)ALT_ACPIDMAP_VID6RD_S_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID6RD_S_ADDR));
     443        *input_id = ALT_ACPIDMAP_VID6RD_S_MID_GET(alt_read_word(ALT_ACPIDMAP_VID6RD_S_ADDR));
     444        *fixed    = ALT_ACPIDMAP_VID6RD_S_FORCE_GET(alt_read_word(ALT_ACPIDMAP_VID6RD_S_ADDR));
     445        break;
     446    case ALT_ACP_ID_OUT_DYNAM_ID_7:
     447        *aruser   = ALT_ACPIDMAP_DYNRD_S_USER_GET(alt_read_word(ALT_ACPIDMAP_DYNRD_S_ADDR));
     448        *page     = (ALT_ACP_ID_MAP_PAGE_t)ALT_ACPIDMAP_DYNRD_S_PAGE_GET(alt_read_word(ALT_ACPIDMAP_DYNRD_S_ADDR));
     449        break;
     450    default:
     451        return ALT_E_BAD_ARG;
     452    }
     453
     454    return ALT_E_SUCCESS;
     455}
     456
     457ALT_STATUS_CODE alt_acp_id_map_write_options_get(const uint32_t output_id,
     458                                                 bool * fixed,
     459                                                 uint32_t * input_id,
     460                                                 ALT_ACP_ID_MAP_PAGE_t * page,
     461                                                 uint32_t * awuser)
     462{
     463    if (output_id == ALT_ACP_ID_MAX_OUTPUT_ID)
     464    {
     465        return ALT_E_BAD_ARG;
     466    }
     467
     468    switch (output_id)
     469    {
     470    case ALT_ACP_ID_OUT_FIXED_ID_2:
     471        *awuser   = ALT_ACPIDMAP_VID2WR_S_USER_GET(alt_read_word(ALT_ACPIDMAP_VID2WR_S_ADDR));
     472        *page     = (ALT_ACP_ID_MAP_PAGE_t)ALT_ACPIDMAP_VID2WR_S_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID2WR_S_ADDR));
     473        *input_id = ALT_ACPIDMAP_VID2WR_S_MID_GET(alt_read_word(ALT_ACPIDMAP_VID2WR_S_ADDR));
     474        *fixed    = ALT_ACPIDMAP_VID2WR_S_FORCE_GET(alt_read_word(ALT_ACPIDMAP_VID2WR_S_ADDR));
     475        break;
     476    case ALT_ACP_ID_OUT_DYNAM_ID_3:
     477        *awuser   = ALT_ACPIDMAP_VID3WR_S_USER_GET(alt_read_word(ALT_ACPIDMAP_VID3WR_S_ADDR));
     478        *page     = (ALT_ACP_ID_MAP_PAGE_t)ALT_ACPIDMAP_VID3WR_S_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID3WR_S_ADDR));
     479        *input_id = ALT_ACPIDMAP_VID3WR_S_MID_GET(alt_read_word(ALT_ACPIDMAP_VID3WR_S_ADDR));
     480        *fixed    = ALT_ACPIDMAP_VID3WR_S_FORCE_GET(alt_read_word(ALT_ACPIDMAP_VID3WR_S_ADDR));
     481        break;
     482    case ALT_ACP_ID_OUT_DYNAM_ID_4:
     483        *awuser   = ALT_ACPIDMAP_VID4WR_S_USER_GET(alt_read_word(ALT_ACPIDMAP_VID4WR_S_ADDR));
     484        *page     = (ALT_ACP_ID_MAP_PAGE_t)ALT_ACPIDMAP_VID4WR_S_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID4WR_S_ADDR));
     485        *input_id = ALT_ACPIDMAP_VID4WR_S_MID_GET(alt_read_word(ALT_ACPIDMAP_VID4WR_S_ADDR));
     486        *fixed    = ALT_ACPIDMAP_VID4WR_S_FORCE_GET(alt_read_word(ALT_ACPIDMAP_VID4WR_S_ADDR));
     487        break;
     488    case ALT_ACP_ID_OUT_DYNAM_ID_5:
     489        *awuser   = ALT_ACPIDMAP_VID5WR_S_USER_GET(alt_read_word(ALT_ACPIDMAP_VID5WR_S_ADDR));
     490        *page     = (ALT_ACP_ID_MAP_PAGE_t)ALT_ACPIDMAP_VID5WR_S_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID5WR_S_ADDR));
     491        *input_id = ALT_ACPIDMAP_VID5WR_S_MID_GET(alt_read_word(ALT_ACPIDMAP_VID5WR_S_ADDR));
     492        *fixed    = ALT_ACPIDMAP_VID5WR_S_FORCE_GET(alt_read_word(ALT_ACPIDMAP_VID5WR_S_ADDR));
     493        break;
     494    case ALT_ACP_ID_OUT_DYNAM_ID_6:
     495        *awuser   = ALT_ACPIDMAP_VID6WR_S_USER_GET(alt_read_word(ALT_ACPIDMAP_VID6WR_S_ADDR));
     496        *page     = (ALT_ACP_ID_MAP_PAGE_t)ALT_ACPIDMAP_VID6WR_S_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID6WR_S_ADDR));
     497        *input_id = ALT_ACPIDMAP_VID6WR_S_MID_GET(alt_read_word(ALT_ACPIDMAP_VID6WR_S_ADDR));
     498        *fixed    = ALT_ACPIDMAP_VID6WR_S_FORCE_GET(alt_read_word(ALT_ACPIDMAP_VID6WR_S_ADDR));
     499        break;
     500    case ALT_ACP_ID_OUT_DYNAM_ID_7:
     501        *awuser   = ALT_ACPIDMAP_DYNWR_S_USER_GET(alt_read_word(ALT_ACPIDMAP_DYNWR_S_ADDR));
     502        *page     = (ALT_ACP_ID_MAP_PAGE_t)ALT_ACPIDMAP_DYNWR_S_PAGE_GET(alt_read_word(ALT_ACPIDMAP_DYNWR_S_ADDR));
     503        break;
     504    default:
     505        return ALT_E_BAD_ARG;
     506    }
     507
     508    return ALT_E_SUCCESS;
     509}
  • c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/src/hwmgr/alt_clock_manager.c

    r96ec8ee8 r9907dde  
    11/******************************************************************************
    2 *
    3 * Copyright 2013 Altera Corporation. All Rights Reserved.
    4 *
    5 * Redistribution and use in source and binary forms, with or without
    6 * modification, are permitted provided that the following conditions are met:
    7 *
    8 * 1. Redistributions of source code must retain the above copyright notice,
    9 * this list of conditions and the following disclaimer.
    10 *
    11 * 2. Redistributions in binary form must reproduce the above copyright notice,
    12 * this list of conditions and the following disclaimer in the documentation
    13 * and/or other materials provided with the distribution.
    14 *
    15 * 3. The name of the author may not be used to endorse or promote products
    16 * derived from this software without specific prior written permission.
    17 *
    18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR
    19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
    20 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO
    21 * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
    22 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
    23 * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
    24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
    25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
    26 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
    27 * OF SUCH DAMAGE.
    28 *
    29 ******************************************************************************/
    30 
    31 
    32 #include    <stdint.h>
    33 #include    <stdlib.h>
    34 #include    <stdbool.h>
    35 #include    <string.h>
    36 #include    <assert.h>
    37 
    38 #include    "socal/hps.h"
    39 #include    "socal/socal.h"
    40 #include    "socal/alt_sysmgr.h"
    41 #include    "hwlib.h"
    42 #include    "alt_clock_manager.h"
    43 #include    "alt_mpu_registers.h"
     2 *
     3 * Copyright 2013 Altera Corporation. All Rights Reserved.
     4 *
     5 * Redistribution and use in source and binary forms, with or without
     6 * modification, are permitted provided that the following conditions are met:
     7 *
     8 * 1. Redistributions of source code must retain the above copyright notice,
     9 * this list of conditions and the following disclaimer.
     10 *
     11 * 2. Redistributions in binary form must reproduce the above copyright notice,
     12 * this list of conditions and the following disclaimer in the documentation
     13 * and/or other materials provided with the distribution.
     14 *
     15 * 3. The name of the author may not be used to endorse or promote products
     16 * derived from this software without specific prior written permission.
     17 *
     18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR
     19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
     20 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO
     21 * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
     22 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
     23 * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
     26 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
     27 * OF SUCH DAMAGE.
     28 *
     29 ******************************************************************************/
     30
     31#include <stdint.h>
     32#include <stdlib.h>
     33#include <stdbool.h>
     34#include <stdio.h>
     35
     36#include "socal/hps.h"
     37#include "socal/socal.h"
     38#include "socal/alt_sysmgr.h"
     39#include "hwlib.h"
     40#include "alt_clock_manager.h"
     41#include "alt_mpu_registers.h"
    4442
    4543#define UINT12_MAX              (4096)
     
    7876        /* Values taken from Section 2.3 and Section 2.7.1 of the HHP HPS-Clocking      */
    7977        /* NPP specification.                                                           */
    80 static ALT_EXT_CLK_PARAMBLOK_t alt_ext_clk_paramblok = {{25000000, 10000000, 50000000, 0, 1},
    81                                                         {25000000, 10000000, 50000000, 0, 1},
    82                                                                {0, 10000000, 50000000, 0, 1},
    83                                                                {0, 10000000, 50000000, 0, 1}};
     78static ALT_EXT_CLK_PARAMBLOK_t alt_ext_clk_paramblok =
     79{
     80    { 25000000, 10000000, 50000000, 0, 1 },
     81    { 25000000, 10000000, 50000000, 0, 1 },
     82    {        0, 10000000, 50000000, 0, 1 },
     83    {        0, 10000000, 50000000, 0, 1 }
     84};
    8485
    8586
     
    105106#define     ALT_GUARDBAND_LIMIT             20
    106107
    107 static ALT_PLL_CLK_PARAMBLOK_t alt_pll_clk_paramblok = {{0, 320000000, 1200000000, ALT_ORIGINAL_GUARDBAND_VAL, 0},
    108                                                         {0, 320000000,  900000000, ALT_ORIGINAL_GUARDBAND_VAL, 0},
    109                                                         {0, 320000000,  800000000, ALT_ORIGINAL_GUARDBAND_VAL, 0},
    110                                                         {0, 320000000, 1600000000, ALT_ORIGINAL_GUARDBAND_VAL, 1},
    111                                                         {0, 320000000, 1250000000, ALT_ORIGINAL_GUARDBAND_VAL, 1},
    112                                                         {0, 320000000, 1066000000, ALT_ORIGINAL_GUARDBAND_VAL, 1}};
     108static ALT_PLL_CLK_PARAMBLOK_t alt_pll_clk_paramblok =
     109{
     110    { 0, 320000000, 1200000000, ALT_ORIGINAL_GUARDBAND_VAL, 0 },
     111    { 0, 320000000,  900000000, ALT_ORIGINAL_GUARDBAND_VAL, 0 },
     112    { 0, 320000000,  800000000, ALT_ORIGINAL_GUARDBAND_VAL, 0 },
     113    { 0, 320000000, 1600000000, ALT_ORIGINAL_GUARDBAND_VAL, 1 },
     114    { 0, 320000000, 1250000000, ALT_ORIGINAL_GUARDBAND_VAL, 1 },
     115    { 0, 320000000, 1066000000, ALT_ORIGINAL_GUARDBAND_VAL, 1 }
     116};
    113117
    114118
     
    134138} ALT_PLL_CNTR_FREQMAX_t;
    135139
     140//
     141// The following pll max frequency array statically defined must be recalculated each time
     142// when powering up, by calling alt_clk_clkmgr_init()
     143//
     144// for 14.1 uboot preloader, the following values are calculated dynamically.
     145//
     146// Arrial 5
     147// alt_pll_cntr_maxfreq.MainPLL_C0   = 1050000000
     148// alt_pll_cntr_maxfreq.MainPLL_C1   =  350000000
     149// alt_pll_cntr_maxfreq.MainPLL_C2   =  262500000
     150// alt_pll_cntr_maxfreq.MainPLL_C3   =  350000000
     151// alt_pll_cntr_maxfreq.MainPLL_C4   =    2050781
     152// alt_pll_cntr_maxfreq.MainPLL_C5   =  116666666
     153// alt_pll_cntr_maxfreq.PeriphPLL_C0 =    1953125
     154// alt_pll_cntr_maxfreq.PeriphPLL_C1 =  250000000
     155// alt_pll_cntr_maxfreq.PeriphPLL_C2 =    1953125
     156// alt_pll_cntr_maxfreq.PeriphPLL_C3 =  200000000
     157// alt_pll_cntr_maxfreq.PeriphPLL_C4 =  200000000
     158// alt_pll_cntr_maxfreq.PeriphPLL_C5 =    1953125
     159// alt_pll_cntr_maxfreq.SDRAMPLL_C0  =  533333333
     160// alt_pll_cntr_maxfreq.SDRAMPLL_C1  = 1066666666
     161// alt_pll_cntr_maxfreq.SDRAMPLL_C2  =  533333333
     162// alt_pll_cntr_maxfreq.SDRAMPLL_C5  =  177777777
     163
     164// Cyclone V
     165// alt_pll_cntr_maxfreq.MainPLL_C0   =  925000000
     166// alt_pll_cntr_maxfreq.MainPLL_C1   =  370000000
     167// alt_pll_cntr_maxfreq.MainPLL_C2   =  462500000
     168// alt_pll_cntr_maxfreq.MainPLL_C3   =  370000000
     169// alt_pll_cntr_maxfreq.MainPLL_C4   =    3613281
     170// alt_pll_cntr_maxfreq.MainPLL_C5   =  123333333
     171// alt_pll_cntr_maxfreq.PeriphPLL_C0 =    1953125
     172// alt_pll_cntr_maxfreq.PeriphPLL_C1 =  250000000
     173// alt_pll_cntr_maxfreq.PeriphPLL_C2 =    1953125
     174// alt_pll_cntr_maxfreq.PeriphPLL_C3 =  200000000
     175// alt_pll_cntr_maxfreq.PeriphPLL_C4 =  200000000
     176// alt_pll_cntr_maxfreq.PeriphPLL_C5 =    1953125
     177// alt_pll_cntr_maxfreq.SDRAMPLL_C0  =  400000000
     178// alt_pll_cntr_maxfreq.SDRAMPLL_C1  =  800000000
     179// alt_pll_cntr_maxfreq.SDRAMPLL_C2  =  400000000
     180// alt_pll_cntr_maxfreq.SDRAMPLL_C5  =  133333333
    136181
    137182
    138183/* Initializes the PLL Counter output maximum frequency block  */
    139 static ALT_PLL_CNTR_FREQMAX_t alt_pll_cntr_maxfreq = {800000000,    /* Main PLL Outputs */
    140                                                       400000000,
    141                                                       400000000,
    142                                                       432000000,
    143                                                       250000000,
    144                                                       125000000,
    145                                                       250000000,    /* Peripheral PLL Outputs */
    146                                                       250000000,
    147                                                       432000000,
    148                                                       250000000,
    149                                                       200000000,
    150                                                       100000000,    /* SDRAM PLL Outputs */
    151                                                       533000000,
    152                                                       1066000000,
    153                                                       533000000,
    154                                                       200000000 };
     184static ALT_PLL_CNTR_FREQMAX_t alt_pll_cntr_maxfreq =
     185{
     186    800000000,    /* Main PLL Outputs */
     187    400000000,
     188    400000000,
     189    432000000,
     190    250000000,
     191    125000000,
     192    250000000,    /* Peripheral PLL Outputs */
     193    250000000,
     194    432000000,
     195    250000000,
     196    200000000,
     197    100000000,    /* SDRAM PLL Outputs */
     198    533000000,
     199    1066000000,
     200    533000000,
     201    200000000
     202};
    155203
    156204
     
    182230
    183231
     232// Undocumented register which determines clock dividers for main PLL C0, C1, and C2. These should be considered RO.
     233#define ALT_CLKMGR_ALTERA_OFST           0xe0
     234#define ALT_CLKMGR_ALTERA_MPUCLK_OFST    0x0
     235#define ALT_CLKMGR_ALTERA_MAINCLK_OFST   0x4
     236#define ALT_CLKMGR_ALTERA_DBGATCLK_OFST  0x8
     237#define ALT_CLKMGR_ALTERA_ADDR           ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_ADDR) + ALT_CLKMGR_ALTERA_OFST))
     238#define ALT_CLKMGR_ALTERA_MPUCLK_ADDR    ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_ALTERA_ADDR) + ALT_CLKMGR_ALTERA_MPUCLK_OFST))
     239#define ALT_CLKMGR_ALTERA_MAINCLK_ADDR   ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_ALTERA_ADDR) + ALT_CLKMGR_ALTERA_MAINCLK_OFST))
     240#define ALT_CLKMGR_ALTERA_DBGATCLK_ADDR  ALT_CAST(void *, (ALT_CAST(char *, ALT_CLKMGR_ALTERA_ADDR) + ALT_CLKMGR_ALTERA_DBGATCLK_OFST))
     241#define ALT_CLKMGR_ALTERA_MPUCLK_CNT_GET(value)   (((value) & 0x000001ff) >> 0)
     242#define ALT_CLKMGR_ALTERA_MAINCLK_CNT_GET(value)  (((value) & 0x000001ff) >> 0)
     243#define ALT_CLKMGR_ALTERA_DBGATCLK_CNT_GET(value) (((value) & 0x000001ff) >> 0)
    184244
    185245/*~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~*/
     
    200260/****************************************************************************************/
    201261
    202 static void inline alt_clk_mgr_wait(void* reg, uint32_t cnt)
     262inline static void alt_clk_mgr_wait(void* reg, uint32_t cnt)
    203263{
    204264    for (; cnt ; cnt--)
     
    207267    }
    208268}
    209 
    210269
    211270    /* Wait time constants */
     
    225284        // to zero and allow for writing a new divisor ratio to it
    226285
    227 
    228 static ALT_STATUS_CODE alt_clk_plls_settle_wait(void)
     286ALT_STATUS_CODE alt_clk_plls_settle_wait(void)
    229287{
    230288    int32_t     i = ALT_BYPASS_TIMEOUT_CNT;
     
    239297}
    240298
    241 
    242 
    243 static ALT_STATUS_CODE alt_clk_pll_lock_wait(ALT_CLK_t pll, uint32_t cnt)
     299static ALT_STATUS_CODE alt_clk_pll_lock_wait(ALT_CLK_t pll, uint32_t timeout)
    244300{
    245     ALT_STATUS_CODE     ret = ALT_E_ERROR;
    246     uint32_t            temp;
    247     uint32_t            mask = 0;
    248 
    249     if (pll == ALT_CLK_MAIN_PLL)  { mask = ALT_CLKMGR_INTER_MAINPLLLOCKED_SET_MSK; }
    250     else if (pll == ALT_CLK_PERIPHERAL_PLL)  { mask = ALT_CLKMGR_INTER_PERPLLLOCKED_SET_MSK; }
    251     else if (pll == ALT_CLK_SDRAM_PLL)  { mask = ALT_CLKMGR_INTER_SDRPLLLOCKED_SET_MSK; }
    252     else { return ret; }
     301    uint32_t locked_mask = 0;
     302
     303    if      (pll == ALT_CLK_MAIN_PLL)       { locked_mask = ALT_CLKMGR_INTER_MAINPLLLOCKED_SET_MSK; }
     304    else if (pll == ALT_CLK_PERIPHERAL_PLL) { locked_mask = ALT_CLKMGR_INTER_PERPLLLOCKED_SET_MSK; }
     305    else if (pll == ALT_CLK_SDRAM_PLL)      { locked_mask = ALT_CLKMGR_INTER_SDRPLLLOCKED_SET_MSK; }
     306    else
     307    {
     308        return ALT_E_BAD_ARG;
     309    }
     310
    253311    do
    254312    {
    255         temp = alt_read_word(ALT_CLKMGR_INTER_ADDR);
    256     } while (!(temp & mask) && --cnt);
    257     if (cnt > 0) { ret = ALT_E_SUCCESS; }
    258     return ret;
     313        uint32_t int_status = alt_read_word(ALT_CLKMGR_INTER_ADDR);
     314        if (int_status & locked_mask)
     315        {
     316            return ALT_E_SUCCESS;
     317        }
     318
     319    } while (timeout--);
     320
     321    return ALT_E_TMO;
    259322}
    260 
    261323
    262324        /* Useful utility macro for checking if two values  */
     
    322384/****************************************************************************************/
    323385
    324  ALT_STATUS_CODE alt_clk_lock_status_clear(ALT_CLK_PLL_LOCK_STATUS_t lock_stat_mask)
     386ALT_STATUS_CODE alt_clk_lock_status_clear(ALT_CLK_PLL_LOCK_STATUS_t lock_stat_mask)
    325387{
    326     ALT_STATUS_CODE ret;
    327 
    328     if (lock_stat_mask & (ALT_CLKMGR_INTER_MAINPLLACHIEVED_CLR_MSK
    329                             & ALT_CLKMGR_INTER_PERPLLACHIEVED_CLR_MSK
    330                             & ALT_CLKMGR_INTER_SDRPLLACHIEVED_CLR_MSK
    331                             & ALT_CLKMGR_INTER_MAINPLLLOST_CLR_MSK
    332                             & ALT_CLKMGR_INTER_PERPLLLOST_CLR_MSK
    333                             & ALT_CLKMGR_INTER_SDRPLLLOST_CLR_MSK))
    334     {
    335         ret = ALT_E_BAD_ARG;
     388    if (lock_stat_mask & (  ALT_CLKMGR_INTER_MAINPLLACHIEVED_CLR_MSK
     389                          & ALT_CLKMGR_INTER_PERPLLACHIEVED_CLR_MSK
     390                          & ALT_CLKMGR_INTER_SDRPLLACHIEVED_CLR_MSK
     391                          & ALT_CLKMGR_INTER_MAINPLLLOST_CLR_MSK
     392                          & ALT_CLKMGR_INTER_PERPLLLOST_CLR_MSK
     393                          & ALT_CLKMGR_INTER_SDRPLLLOST_CLR_MSK)
     394        )
     395    {
     396        return ALT_E_BAD_ARG;
    336397    }
    337398    else
    338399    {
    339400        alt_setbits_word(ALT_CLKMGR_INTER_ADDR, lock_stat_mask);
    340         ret = ALT_E_SUCCESS;
    341     }
    342     return ret;
     401        return ALT_E_SUCCESS;
     402    }
    343403}
    344404
     
    350410uint32_t alt_clk_lock_status_get(void)
    351411{
    352     return alt_read_word(ALT_CLKMGR_INTER_ADDR) & (ALT_CLKMGR_INTER_MAINPLLACHIEVED_SET_MSK
    353             | ALT_CLKMGR_INTER_PERPLLACHIEVED_SET_MSK
    354             | ALT_CLKMGR_INTER_SDRPLLACHIEVED_SET_MSK
    355             | ALT_CLKMGR_INTER_MAINPLLLOST_SET_MSK
    356             | ALT_CLKMGR_INTER_PERPLLLOST_SET_MSK
    357             | ALT_CLKMGR_INTER_SDRPLLLOST_SET_MSK
    358             | ALT_CLKMGR_INTER_MAINPLLLOCKED_SET_MSK
    359             | ALT_CLKMGR_INTER_PERPLLLOCKED_SET_MSK
    360             | ALT_CLKMGR_INTER_SDRPLLLOCKED_SET_MSK );
     412    return alt_read_word(ALT_CLKMGR_INTER_ADDR) & (  ALT_CLKMGR_INTER_MAINPLLACHIEVED_SET_MSK
     413                                                   | ALT_CLKMGR_INTER_PERPLLACHIEVED_SET_MSK
     414                                                   | ALT_CLKMGR_INTER_SDRPLLACHIEVED_SET_MSK
     415                                                   | ALT_CLKMGR_INTER_MAINPLLLOST_SET_MSK
     416                                                   | ALT_CLKMGR_INTER_PERPLLLOST_SET_MSK
     417                                                   | ALT_CLKMGR_INTER_SDRPLLLOST_SET_MSK
     418                                                   | ALT_CLKMGR_INTER_MAINPLLLOCKED_SET_MSK
     419                                                   | ALT_CLKMGR_INTER_PERPLLLOCKED_SET_MSK
     420                                                   | ALT_CLKMGR_INTER_SDRPLLLOCKED_SET_MSK );
    361421}
    362422
     
    369429ALT_STATUS_CODE alt_clk_pll_is_locked(ALT_CLK_t pll)
    370430{
    371     ALT_STATUS_CODE     ret = ALT_E_BAD_ARG;
     431    ALT_STATUS_CODE status = ALT_E_BAD_ARG;
    372432
    373433    if (pll == ALT_CLK_MAIN_PLL)
    374434    {
    375         ret = (alt_read_word(ALT_CLKMGR_INTER_ADDR) & ALT_CLKMGR_INTER_MAINPLLLOCKED_SET_MSK)
     435        status = (alt_read_word(ALT_CLKMGR_INTER_ADDR) & ALT_CLKMGR_INTER_MAINPLLLOCKED_SET_MSK)
    376436                ? ALT_E_TRUE : ALT_E_FALSE;
    377437    }
    378438    else if (pll == ALT_CLK_PERIPHERAL_PLL)
    379439    {
    380         ret = (alt_read_word(ALT_CLKMGR_INTER_ADDR) & ALT_CLKMGR_INTER_PERPLLLOCKED_SET_MSK)
     440        status = (alt_read_word(ALT_CLKMGR_INTER_ADDR) & ALT_CLKMGR_INTER_PERPLLLOCKED_SET_MSK)
    381441                ? ALT_E_TRUE : ALT_E_FALSE;
    382442    }
    383443    else if (pll == ALT_CLK_SDRAM_PLL)
    384444    {
    385         ret = (alt_read_word(ALT_CLKMGR_INTER_ADDR) & ALT_CLKMGR_INTER_SDRPLLLOCKED_SET_MSK)
     445        status = (alt_read_word(ALT_CLKMGR_INTER_ADDR) & ALT_CLKMGR_INTER_SDRPLLLOCKED_SET_MSK)
    386446                ? ALT_E_TRUE : ALT_E_FALSE;
    387447    }
    388     return ret;
     448    return status;
    389449}
    390450
     
    397457ALT_STATUS_CODE alt_clk_safe_mode_clear(void)
    398458{
    399     ALT_STATUS_CODE     ret = ALT_E_ERROR;
     459    ALT_STATUS_CODE status = ALT_E_ERROR;
    400460#if ALT_PREVENT_GLITCH_EXSAFE
    401461    uint32_t        temp;
     
    408468    alt_setbits_word(ALT_CLKMGR_CTL_ADDR, ALT_CLKMGR_CTL_SAFEMOD_SET_MSK);
    409469                    // clear safe mode bit
    410     ret = alt_clk_plls_settle_wait();
     470    status = alt_clk_plls_settle_wait();
    411471    alt_replbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR,
    412472            ALT_CLKMGR_MAINPLL_EN_L4MPCLK_SET_MSK | ALT_CLKMGR_MAINPLL_EN_L4SPCLK_SET_MSK,
     
    417477    alt_setbits_word(ALT_CLKMGR_CTL_ADDR, ALT_CLKMGR_CTL_SAFEMOD_SET_MSK);
    418478                    // clear safe mode bit
    419     ret = alt_clk_plls_settle_wait();
     479    status = alt_clk_plls_settle_wait();
    420480
    421481#endif
    422     return ret;
     482    return status;
    423483}
    424484
     
    464524ALT_STATUS_CODE alt_clk_pll_bypass_disable(ALT_CLK_t pll)
    465525{
    466     ALT_STATUS_CODE     ret = ALT_E_BAD_ARG;
    467     uint32_t            temp;
     526    ALT_STATUS_CODE status = ALT_E_BAD_ARG;
     527    uint32_t        temp;
    468528#if  ALT_PREVENT_GLITCH_BYP
    469     uint32_t            temp1;
    470     bool                restore_0 = false;
    471     bool                restore_1 = false;
     529    uint32_t        temp1;
     530    bool            restore_0 = false;
     531    bool            restore_1 = false;
    472532#endif
    473533
     
    476536    {
    477537        if (pll == ALT_CLK_MAIN_PLL)
     538        {
     539#if  ALT_PREVENT_GLITCH_BYP
     540            // if L4MP or L4SP source is set to Main PLL C1, gate it off before changing
     541            // bypass state, then gate clock back on. FogBugz #63778
     542            temp  = alt_read_word(ALT_CLKMGR_MAINPLL_L4SRC_ADDR);
     543            temp1 = alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR);
     544
     545            if ((temp1 & ALT_CLKMGR_MAINPLL_EN_L4MPCLK_SET_MSK) && (!(temp & ALT_CLKMGR_MAINPLL_L4SRC_L4MP_SET_MSK)))
     546            {
     547                restore_0 = true;
     548            }
     549            if ((temp1 & ALT_CLKMGR_MAINPLL_EN_L4SPCLK_SET_MSK) && (!(temp & ALT_CLKMGR_MAINPLL_L4SRC_L4SP_SET_MSK)))
     550            {
     551                restore_1 = true;
     552            }
     553            temp = temp1;
     554            if (restore_0) { temp &= ALT_CLKMGR_MAINPLL_EN_L4MPCLK_CLR_MSK; }
     555            if (restore_1) { temp &= ALT_CLKMGR_MAINPLL_EN_L4SPCLK_CLR_MSK; }
     556            if (restore_0 || restore_1) { alt_write_word(ALT_CLKMGR_MAINPLL_EN_ADDR, temp); }
     557#endif
     558
     559            // assert outresetall of main PLL
     560            temp = alt_read_word(ALT_CLKMGR_MAINPLL_VCO_ADDR);
     561            alt_write_word(ALT_CLKMGR_MAINPLL_VCO_ADDR, temp | ALT_CLKMGR_MAINPLL_VCO_OUTRSTALL_SET_MSK);
     562
     563            // deassert outresetall of main PLL
     564            alt_write_word(ALT_CLKMGR_MAINPLL_VCO_ADDR, temp & ALT_CLKMGR_MAINPLL_VCO_OUTRSTALL_CLR_MSK);
     565
     566            alt_clk_plls_settle_wait();
     567
     568            // remove bypass
     569            alt_clrbits_word(ALT_CLKMGR_BYPASS_ADDR, ALT_CLKMGR_BYPASS_MAINPLL_SET_MSK);
     570            status = alt_clk_plls_settle_wait();
     571
     572#if  ALT_PREVENT_GLITCH_BYP
     573            if (restore_0 || restore_1)
     574            {
     575                alt_clk_mgr_wait(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV);
     576                            // wait a bit more before reenabling the L4MP and L4SP clocks
     577                alt_write_word(ALT_CLKMGR_MAINPLL_EN_ADDR, temp1);
     578            }
     579#endif
     580        }
     581
     582        else if (pll == ALT_CLK_PERIPHERAL_PLL)
    478583        {
    479584#if  ALT_PREVENT_GLITCH_BYP
     
    483588            temp1 = alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR);
    484589
    485             if ((temp1 & ALT_CLKMGR_MAINPLL_EN_L4MPCLK_SET_MSK) && (!(temp & ALT_CLKMGR_MAINPLL_L4SRC_L4MP_SET_MSK)))
     590            if ((temp1 & ALT_CLKMGR_MAINPLL_EN_L4MPCLK_SET_MSK) && (temp & ALT_CLKMGR_MAINPLL_L4SRC_L4MP_SET_MSK))
    486591            {
    487592                    restore_0 = true;
    488593            }
    489             if ((temp1 & ALT_CLKMGR_MAINPLL_EN_L4SPCLK_SET_MSK) && (!(temp & ALT_CLKMGR_MAINPLL_L4SRC_L4SP_SET_MSK)))
     594            if ((temp1 & ALT_CLKMGR_MAINPLL_EN_L4SPCLK_SET_MSK) && (temp & ALT_CLKMGR_MAINPLL_L4SRC_L4SP_SET_MSK))
    490595            {
    491596                    restore_1 = true;
     
    497602#endif
    498603
    499             // assert outresetall of main PLL
    500             temp = alt_read_word(ALT_CLKMGR_MAINPLL_VCO_ADDR);
    501             alt_write_word(ALT_CLKMGR_MAINPLL_VCO_ADDR, temp | ALT_CLKMGR_MAINPLL_VCO_OUTRSTALL_SET_MSK);
    502 
    503             // deassert outresetall of main PLL
    504             alt_write_word(ALT_CLKMGR_MAINPLL_VCO_ADDR, temp & ALT_CLKMGR_MAINPLL_VCO_OUTRSTALL_CLR_MSK);
    505 
    506             alt_clk_plls_settle_wait();
    507 
    508             // remove bypass
    509             alt_clrbits_word(ALT_CLKMGR_BYPASS_ADDR, ALT_CLKMGR_BYPASS_MAINPLL_SET_MSK);
    510             ret = alt_clk_plls_settle_wait();
    511 
    512 #if  ALT_PREVENT_GLITCH_BYP
    513             if (restore_0 || restore_1)
    514             {
    515                 alt_clk_mgr_wait(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_SW_MANAGED_CLK_WAIT_CTRDIV);
    516                             // wait a bit more before reenabling the L4MP and L4SP clocks
    517                 alt_write_word(ALT_CLKMGR_MAINPLL_EN_ADDR, temp1);
    518             }
    519 #endif
    520         }
    521 
    522         else if (pll == ALT_CLK_PERIPHERAL_PLL)
    523         {
    524 #if  ALT_PREVENT_GLITCH_BYP
    525             // if L4MP or L4SP source is set to Main PLL C1, gate it off before changing
    526             // bypass state, then gate clock back on. FogBugz #63778
    527             temp = alt_read_word(ALT_CLKMGR_MAINPLL_L4SRC_ADDR);
    528             temp1 = alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR);
    529 
    530             if ((temp1 & ALT_CLKMGR_MAINPLL_EN_L4MPCLK_SET_MSK) && (temp & ALT_CLKMGR_MAINPLL_L4SRC_L4MP_SET_MSK))
    531             {
    532                     restore_0 = true;
    533             }
    534             if ((temp1 & ALT_CLKMGR_MAINPLL_EN_L4SPCLK_SET_MSK) && (temp & ALT_CLKMGR_MAINPLL_L4SRC_L4SP_SET_MSK))
    535             {
    536                     restore_1 = true;
    537             }
    538             temp = temp1;
    539             if (restore_0)  { temp &= ALT_CLKMGR_MAINPLL_EN_L4MPCLK_CLR_MSK; }
    540             if (restore_1)  { temp &= ALT_CLKMGR_MAINPLL_EN_L4SPCLK_CLR_MSK; }
    541             if (restore_0 || restore_1) { alt_write_word(ALT_CLKMGR_MAINPLL_EN_ADDR, temp); }
    542 #endif
    543 
    544604            // assert outresetall of Peripheral PLL
    545605            temp = alt_read_word(ALT_CLKMGR_PERPLL_VCO_ADDR);
     
    552612            // remove bypass - don't think that there's any need to touch the bypass clock source
    553613            alt_clrbits_word(ALT_CLKMGR_BYPASS_ADDR, ALT_CLKMGR_BYPASS_PERPLL_SET_MSK);
    554             ret = alt_clk_plls_settle_wait();
     614            status = alt_clk_plls_settle_wait();
    555615
    556616#if  ALT_PREVENT_GLITCH_BYP
     
    576636            // remove bypass - don't think that there's any need to touch the bypass clock source
    577637            alt_clrbits_word(ALT_CLKMGR_BYPASS_ADDR, ALT_CLKMGR_BYPASS_SDRPLLSRC_SET_MSK);
    578             ret = alt_clk_plls_settle_wait();
    579         }
    580     }
    581     else { ret = ALT_E_ERROR; }
    582 
    583     return ret;
     638            status = alt_clk_plls_settle_wait();
     639        }
     640    }
     641    else
     642    {
     643        status = ALT_E_ERROR;
     644    }
     645
     646    return status;
    584647}
    585648
     
    591654ALT_STATUS_CODE alt_clk_pll_bypass_enable(ALT_CLK_t pll, bool use_input_mux)
    592655{
    593     ALT_STATUS_CODE     ret = ALT_E_BAD_ARG;
    594     uint32_t            temp;
     656    ALT_STATUS_CODE status = ALT_E_BAD_ARG;
     657    uint32_t        temp;
    595658#ifdef  ALT_PREVENT_GLITCH_BYP
    596     uint32_t            temp1;
    597     bool                restore_0 = false;
    598     bool                restore_1 = false;
     659    uint32_t        temp1;
     660    bool            restore_0 = false;
     661    bool            restore_1 = false;
    599662#endif
    600663
     
    606669            // if L4MP or L4SP source is set to Main PLL C1, gate it off before changing
    607670            // bypass state, then gate clock back on. FogBugz #63778
    608             temp = alt_read_word(ALT_CLKMGR_MAINPLL_L4SRC_ADDR);
     671            temp  = alt_read_word(ALT_CLKMGR_MAINPLL_L4SRC_ADDR);
    609672            temp1 = alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR);
    610673
    611674            if ((temp1 & ALT_CLKMGR_MAINPLL_EN_L4MPCLK_SET_MSK) && (!(temp & ALT_CLKMGR_MAINPLL_L4SRC_L4MP_SET_MSK)))
    612675            {
    613                     restore_0 = true;
     676                restore_0 = true;
    614677            }
    615678            if ((temp1 & ALT_CLKMGR_MAINPLL_EN_L4SPCLK_SET_MSK) && (!(temp & ALT_CLKMGR_MAINPLL_L4SRC_L4SP_SET_MSK)))
    616679            {
    617                     restore_1 = true;
     680                restore_1 = true;
    618681            }
    619682            temp = temp1;
    620             if (restore_0)  { temp &= ALT_CLKMGR_MAINPLL_EN_L4MPCLK_CLR_MSK; }
    621             if (restore_1)  { temp &= ALT_CLKMGR_MAINPLL_EN_L4SPCLK_CLR_MSK; }
     683            if (restore_0) { temp &= ALT_CLKMGR_MAINPLL_EN_L4MPCLK_CLR_MSK; }
     684            if (restore_1) { temp &= ALT_CLKMGR_MAINPLL_EN_L4SPCLK_CLR_MSK; }
    622685            if (restore_0 || restore_1) { alt_write_word(ALT_CLKMGR_MAINPLL_EN_ADDR, temp); }
    623686
     
    625688                        // no input mux select on main PLL
    626689
    627             ret = alt_clk_plls_settle_wait();
     690            status = alt_clk_plls_settle_wait();
    628691                        // wait before reenabling the L4MP and L4SP clocks
    629692            if (restore_0 || restore_1) { alt_write_word(ALT_CLKMGR_MAINPLL_EN_ADDR, temp1); }
     
    632695            alt_setbits_word(ALT_CLKMGR_BYPASS_ADDR, ALT_CLKMGR_BYPASS_MAINPLL_SET_MSK);
    633696                        // no input mux select on main PLL
    634             ret = alt_clk_plls_settle_wait();
     697            status = alt_clk_plls_settle_wait();
    635698
    636699#endif
    637             ret = ALT_E_SUCCESS;
    638         }
    639         else { ret =  ALT_E_BAD_ARG; }
    640     }
    641 
     700            status = ALT_E_SUCCESS;
     701        }
     702        else
     703        {
     704            status =  ALT_E_BAD_ARG;
     705        }
     706    }
    642707    else if (pll == ALT_CLK_PERIPHERAL_PLL)
    643708    {
     
    645710        // if L4MP or L4SP source is set to Peripheral PLL C1, gate it off before changing
    646711        // bypass state, then gate clock back on. FogBugz #63778
    647         temp = alt_read_word(ALT_CLKMGR_MAINPLL_L4SRC_ADDR);
     712        temp  = alt_read_word(ALT_CLKMGR_MAINPLL_L4SRC_ADDR);
    648713        temp1 = alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR);
    649714
    650715        if ((temp1 & ALT_CLKMGR_MAINPLL_EN_L4MPCLK_SET_MSK) && (temp & ALT_CLKMGR_MAINPLL_L4SRC_L4MP_SET_MSK))
    651716        {
    652                 restore_0 = true;
     717            restore_0 = true;
    653718        }
    654719        if ((temp1 & ALT_CLKMGR_MAINPLL_EN_L4SPCLK_SET_MSK) && (temp & ALT_CLKMGR_MAINPLL_L4SRC_L4SP_SET_MSK))
    655720        {
    656                 restore_1 = true;
     721            restore_1 = true;
    657722        }
    658723        temp = temp1;
    659         if (restore_0)  { temp &= ALT_CLKMGR_MAINPLL_EN_L4MPCLK_CLR_MSK; }
    660         if (restore_1)  { temp &= ALT_CLKMGR_MAINPLL_EN_L4SPCLK_CLR_MSK; }
     724        if (restore_0) { temp &= ALT_CLKMGR_MAINPLL_EN_L4MPCLK_CLR_MSK; }
     725        if (restore_1) { temp &= ALT_CLKMGR_MAINPLL_EN_L4SPCLK_CLR_MSK; }
    661726        if (restore_0 || restore_1) { alt_write_word(ALT_CLKMGR_MAINPLL_EN_ADDR, temp); }
    662727
     
    679744                    // set bypass bit and optionally the source select bit
    680745#endif
    681         ret = ALT_E_SUCCESS;
     746        status = ALT_E_SUCCESS;
    682747    }
    683748
     
    690755                    // set bypass bit and optionally the source select bit
    691756        alt_write_word(ALT_CLKMGR_BYPASS_ADDR, temp);
    692         ret = ALT_E_SUCCESS;
    693     }
    694     return ret;
     757        status = ALT_E_SUCCESS;
     758    }
     759    return status;
    695760}
    696761
     
    707772ALT_STATUS_CODE alt_clk_pll_is_bypassed(ALT_CLK_t pll)
    708773{
    709     ALT_STATUS_CODE     ret = ALT_E_BAD_ARG;
     774    ALT_STATUS_CODE status = ALT_E_BAD_ARG;
    710775
    711776    if (pll == ALT_CLK_MAIN_PLL)
    712777    {
    713         ret = (ALT_CLKMGR_CTL_SAFEMOD_GET(alt_read_word(ALT_CLKMGR_CTL_ADDR))
     778        status = (ALT_CLKMGR_CTL_SAFEMOD_GET(alt_read_word(ALT_CLKMGR_CTL_ADDR))
    714779                || ALT_CLKMGR_BYPASS_MAINPLL_GET(alt_read_word(ALT_CLKMGR_BYPASS_ADDR)))
    715780                ? ALT_E_TRUE : ALT_E_FALSE;
     
    717782    else if (pll == ALT_CLK_PERIPHERAL_PLL)
    718783    {
    719         ret = (ALT_CLKMGR_CTL_SAFEMOD_GET(alt_read_word(ALT_CLKMGR_CTL_ADDR))
     784        status = (ALT_CLKMGR_CTL_SAFEMOD_GET(alt_read_word(ALT_CLKMGR_CTL_ADDR))
    720785                || ALT_CLKMGR_BYPASS_PERPLL_GET(alt_read_word(ALT_CLKMGR_BYPASS_ADDR)))
    721786                ? ALT_E_TRUE : ALT_E_FALSE;
     
    723788    else if (pll == ALT_CLK_SDRAM_PLL)
    724789    {
    725         ret = (ALT_CLKMGR_CTL_SAFEMOD_GET(alt_read_word(ALT_CLKMGR_CTL_ADDR))
     790        status = (ALT_CLKMGR_CTL_SAFEMOD_GET(alt_read_word(ALT_CLKMGR_CTL_ADDR))
    726791                || ALT_CLKMGR_BYPASS_SDRPLL_GET(alt_read_word(ALT_CLKMGR_BYPASS_ADDR)))
    727792                ? ALT_E_TRUE : ALT_E_FALSE;
    728793    }
    729     return ret;
     794    return status;
    730795}
    731796
     
    735800/****************************************************************************************/
    736801
    737 static ALT_CLK_t alt_clk_pll_source_get(ALT_CLK_t pll)
     802ALT_CLK_t alt_clk_pll_source_get(ALT_CLK_t pll)
    738803{
    739     ALT_CLK_t       ret = ALT_CLK_UNKNOWN;
     804    ALT_CLK_t      ret = ALT_CLK_UNKNOWN;
    740805    uint32_t       temp;
    741806
     
    778843            ret = ALT_CLK_F2H_SDRAM_REF;
    779844        }
    780         }
     845    }
    781846    return ret;
    782847}
    783848
    784 
    785 /****************************************************************************************/
    786 /* alt_clk_clock_disable() disables the specified clock. Once the clock is disabled,    */
    787 /* its clock signal does not propagate to its clocked elements.                         */
    788 /****************************************************************************************/
    789 
     849//
     850// alt_clk_clock_disable() disables the specified clock. Once the clock is disabled,
     851// its clock signal does not propagate to its clocked elements.
     852//
    790853ALT_STATUS_CODE alt_clk_clock_disable(ALT_CLK_t clk)
    791854{
    792     ALT_STATUS_CODE     ret = ALT_E_BAD_ARG;
     855    ALT_STATUS_CODE status = ALT_E_SUCCESS;
    793856
    794857    switch (clk)
    795858    {
    796             /* For PLLs, put them in bypass mode */
    797         case (ALT_CLK_MAIN_PLL):
    798         case (ALT_CLK_PERIPHERAL_PLL):
    799         case (ALT_CLK_SDRAM_PLL):
    800             ret = alt_clk_pll_bypass_enable(clk, false);
    801             break;
    802 
    803         /* Clocks that originate at the Main PLL */
    804         case (ALT_CLK_L4_MAIN):
    805             alt_clrbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_L4MAINCLK_SET_MSK);
    806             ret = ALT_E_SUCCESS;
    807             break;
    808         case (ALT_CLK_L3_MP):
    809             alt_clrbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_L3MPCLK_SET_MSK);
    810             ret = ALT_E_SUCCESS;
    811             break;
    812         case (ALT_CLK_L4_MP):
    813             alt_clrbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_L4MPCLK_SET_MSK);
    814             ret = ALT_E_SUCCESS;
    815             break;
    816         case (ALT_CLK_L4_SP):
    817             alt_clrbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_L4SPCLK_SET_MSK);
    818             ret = ALT_E_SUCCESS;
    819             break;
    820         case (ALT_CLK_DBG_AT):
    821             alt_clrbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_DBGATCLK_SET_MSK);
    822             ret = ALT_E_SUCCESS;
    823             break;
    824         case (ALT_CLK_DBG):
    825             alt_clrbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_DBGCLK_SET_MSK);
    826             ret = ALT_E_SUCCESS;
    827             break;
    828         case (ALT_CLK_DBG_TRACE):
    829             alt_clrbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK_SET_MSK);
    830             ret = ALT_E_SUCCESS;
    831             break;
    832         case (ALT_CLK_DBG_TIMER):
    833             alt_clrbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK_SET_MSK);
    834             ret = ALT_E_SUCCESS;
    835             break;
    836         case (ALT_CLK_CFG):
    837             alt_clrbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_CFGCLK_SET_MSK);
    838             ret = ALT_E_SUCCESS;
    839             break;
    840         case (ALT_CLK_H2F_USER0):
    841             alt_clrbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK_SET_MSK);
    842             ret = ALT_E_SUCCESS;
    843             break;
    844 
    845             /* Clocks that originate at the Peripheral PLL */
    846         case (ALT_CLK_EMAC0):
    847             alt_clrbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_EMAC0CLK_SET_MSK);
    848             ret = ALT_E_SUCCESS;
    849             break;
    850         case (ALT_CLK_EMAC1):
    851             alt_clrbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_EMAC1CLK_SET_MSK);
    852             ret = ALT_E_SUCCESS;
    853             break;
    854         case (ALT_CLK_USB_MP):
    855             alt_clrbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_USBCLK_SET_MSK);
    856             ret = ALT_E_SUCCESS;
    857             break;
    858         case (ALT_CLK_SPI_M):
    859             alt_clrbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_SPIMCLK_SET_MSK);
    860             ret = ALT_E_SUCCESS;
    861             break;
    862         case (ALT_CLK_CAN0):
    863             alt_clrbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_CAN0CLK_SET_MSK);
    864             ret = ALT_E_SUCCESS;
    865             break;
    866         case (ALT_CLK_CAN1):
    867             alt_clrbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_CAN1CLK_SET_MSK);
    868             ret = ALT_E_SUCCESS;
    869             break;
    870         case (ALT_CLK_GPIO_DB):
    871             alt_clrbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_GPIOCLK_SET_MSK);
    872             ret = ALT_E_SUCCESS;
    873             break;
    874         case (ALT_CLK_H2F_USER1):
    875             alt_clrbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK_SET_MSK);
    876             ret = ALT_E_SUCCESS;
    877             break;
    878         case (ALT_CLK_SDMMC):
    879             alt_clrbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_SDMMCCLK_SET_MSK);
    880             ret = ALT_E_SUCCESS;
    881             break;
    882         case (ALT_CLK_NAND_X):
    883             alt_clrbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_NANDCLK_SET_MSK);
    884             alt_clk_mgr_wait(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_SW_MANAGED_CLK_WAIT_NANDCLK);
    885                 // gate nand_clk off before nand_x_clk
    886             alt_clrbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_NANDXCLK_SET_MSK);
    887             ret = ALT_E_SUCCESS;
    888             break;
    889         case (ALT_CLK_NAND):
    890             alt_clrbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_NANDCLK_SET_MSK);
    891             ret = ALT_E_SUCCESS;
    892         break;
    893         case (ALT_CLK_QSPI):
    894             alt_clrbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_QSPICLK_SET_MSK);
    895             ret = ALT_E_SUCCESS;
    896             break;
    897 
    898         /* Clocks that originate at the SDRAM PLL */
    899         case (ALT_CLK_DDR_DQS):
    900             alt_clrbits_word(ALT_CLKMGR_SDRPLL_EN_ADDR, ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK_SET_MSK);
    901             ret = ALT_E_SUCCESS;
    902             break;
    903 
    904         case (ALT_CLK_DDR_2X_DQS):
    905             alt_clrbits_word(ALT_CLKMGR_SDRPLL_EN_ADDR, ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK_SET_MSK);
    906             ret = ALT_E_SUCCESS;
    907             break;
    908 
    909         case (ALT_CLK_DDR_DQ):
    910             alt_clrbits_word(ALT_CLKMGR_SDRPLL_EN_ADDR, ALT_CLKMGR_SDRPLL_EN_DDRDQCLK_SET_MSK);
    911             ret = ALT_E_SUCCESS;
    912             break;
    913 
    914         case (ALT_CLK_H2F_USER2):
    915             alt_clrbits_word(ALT_CLKMGR_SDRPLL_EN_ADDR, ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK_SET_MSK);
    916             ret = ALT_E_SUCCESS;
    917             break;
    918 
    919         default:
    920             break;
    921 
    922     }
     859        // For PLLs, put them in bypass mode.
     860    case ALT_CLK_MAIN_PLL:
     861    case ALT_CLK_PERIPHERAL_PLL:
     862    case ALT_CLK_SDRAM_PLL:
     863        status = alt_clk_pll_bypass_enable(clk, false);
     864        break;
     865
     866        // Clocks that originate at the Main PLL.
     867    case ALT_CLK_L4_MAIN:
     868        alt_clrbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_L4MAINCLK_SET_MSK);
     869        break;
     870    case ALT_CLK_L3_MP:
     871        alt_clrbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_L3MPCLK_SET_MSK);
     872        break;
     873    case ALT_CLK_L4_MP:
     874        alt_clrbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_L4MPCLK_SET_MSK);
     875        break;
     876    case ALT_CLK_L4_SP:
     877        alt_clrbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_L4SPCLK_SET_MSK);
     878        break;
     879    case ALT_CLK_DBG_AT:
     880        alt_clrbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_DBGATCLK_SET_MSK);
     881        break;
     882    case ALT_CLK_DBG:
     883        alt_clrbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_DBGCLK_SET_MSK);
     884        break;
     885    case ALT_CLK_DBG_TRACE:
     886        alt_clrbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK_SET_MSK);
     887        break;
     888    case ALT_CLK_DBG_TIMER:
     889        alt_clrbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK_SET_MSK);
     890        break;
     891    case ALT_CLK_CFG:
     892        alt_clrbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_CFGCLK_SET_MSK);
     893        break;
     894    case ALT_CLK_H2F_USER0:
     895        alt_clrbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK_SET_MSK);
     896        break;
     897
     898        // Clocks that originate at the Peripheral PLL.
     899    case ALT_CLK_EMAC0:
     900        alt_clrbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_EMAC0CLK_SET_MSK);
     901        break;
     902    case ALT_CLK_EMAC1:
     903        alt_clrbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_EMAC1CLK_SET_MSK);
     904        break;
     905    case ALT_CLK_USB_MP:
     906        alt_clrbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_USBCLK_SET_MSK);
     907        break;
     908    case ALT_CLK_SPI_M:
     909        alt_clrbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_SPIMCLK_SET_MSK);
     910        break;
     911    case ALT_CLK_CAN0:
     912        alt_clrbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_CAN0CLK_SET_MSK);
     913        break;
     914    case ALT_CLK_CAN1:
     915        alt_clrbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_CAN1CLK_SET_MSK);
     916        break;
     917    case ALT_CLK_GPIO_DB:
     918        alt_clrbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_GPIOCLK_SET_MSK);
     919        break;
     920    case ALT_CLK_H2F_USER1:
     921        alt_clrbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK_SET_MSK);
     922        break;
     923    case ALT_CLK_SDMMC:
     924        alt_clrbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_SDMMCCLK_SET_MSK);
     925        break;
     926    case ALT_CLK_NAND_X:
     927        alt_clrbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_NANDCLK_SET_MSK);
     928        alt_clk_mgr_wait(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_SW_MANAGED_CLK_WAIT_NANDCLK);
     929        // gate nand_clk off before nand_x_clk.
     930        alt_clrbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_NANDXCLK_SET_MSK);
     931        break;
     932    case ALT_CLK_NAND:
     933        alt_clrbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_NANDCLK_SET_MSK);
     934        break;
     935    case ALT_CLK_QSPI:
     936        alt_clrbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_QSPICLK_SET_MSK);
     937        break;
     938
     939        // Clocks that originate at the SDRAM PLL.
     940    case ALT_CLK_DDR_DQS:
     941        alt_clrbits_word(ALT_CLKMGR_SDRPLL_EN_ADDR, ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK_SET_MSK);
     942        break;
     943    case ALT_CLK_DDR_2X_DQS:
     944        alt_clrbits_word(ALT_CLKMGR_SDRPLL_EN_ADDR, ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK_SET_MSK);
     945        break;
     946    case ALT_CLK_DDR_DQ:
     947        alt_clrbits_word(ALT_CLKMGR_SDRPLL_EN_ADDR, ALT_CLKMGR_SDRPLL_EN_DDRDQCLK_SET_MSK);
     948        break;
     949    case ALT_CLK_H2F_USER2:
     950        alt_clrbits_word(ALT_CLKMGR_SDRPLL_EN_ADDR, ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK_SET_MSK);
     951        break;
     952
     953    default:
     954        status = ALT_E_BAD_ARG;
     955        break;
     956    }
     957
     958    return status;
     959}
     960
     961
     962//
     963// alt_clk_clock_enable() enables the specified clock. Once the clock is enabled, its
     964// clock signal propagates to its elements.
     965//
     966ALT_STATUS_CODE alt_clk_clock_enable(ALT_CLK_t clk)
     967{
     968    ALT_STATUS_CODE status = ALT_E_SUCCESS;
     969
     970    switch (clk)
     971    {
     972        // For PLLs, take them out of bypass mode.
     973    case ALT_CLK_MAIN_PLL:
     974    case ALT_CLK_PERIPHERAL_PLL:
     975    case ALT_CLK_SDRAM_PLL:
     976        status = alt_clk_pll_bypass_disable(clk);
     977        break;
     978
     979        // Clocks that originate at the Main PLL.
     980    case ALT_CLK_L4_MAIN:
     981        alt_setbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_L4MAINCLK_SET_MSK);
     982        break;
     983    case ALT_CLK_L3_MP:
     984        alt_setbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_L3MPCLK_SET_MSK);
     985        break;
     986    case ALT_CLK_L4_MP:
     987        alt_setbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_L4MPCLK_SET_MSK);
     988        break;
     989    case ALT_CLK_L4_SP:
     990        alt_setbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_L4SPCLK_SET_MSK);
     991        break;
     992    case ALT_CLK_DBG_AT:
     993        alt_setbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_DBGATCLK_SET_MSK);
     994        break;
     995    case ALT_CLK_DBG:
     996        alt_setbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_DBGCLK_SET_MSK);
     997        break;
     998    case ALT_CLK_DBG_TRACE:
     999        alt_setbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK_SET_MSK);
     1000        break;
     1001    case ALT_CLK_DBG_TIMER:
     1002        alt_setbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK_SET_MSK);
     1003        break;
     1004    case ALT_CLK_CFG:
     1005        alt_setbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_CFGCLK_SET_MSK);
     1006        break;
     1007    case ALT_CLK_H2F_USER0:
     1008        alt_setbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK_SET_MSK);
     1009        break;
     1010
     1011        // Clocks that originate at the Peripheral PLL.
     1012    case ALT_CLK_EMAC0:
     1013        alt_setbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_EMAC0CLK_SET_MSK);
     1014        break;
     1015    case ALT_CLK_EMAC1:
     1016        alt_setbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_EMAC1CLK_SET_MSK);
     1017        break;
     1018    case ALT_CLK_USB_MP:
     1019        alt_setbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_USBCLK_SET_MSK);
     1020        break;
     1021    case ALT_CLK_SPI_M:
     1022        alt_setbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_SPIMCLK_SET_MSK);
     1023        break;
     1024    case ALT_CLK_CAN0:
     1025        alt_setbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_CAN0CLK_SET_MSK);
     1026        break;
     1027    case ALT_CLK_CAN1:
     1028        alt_setbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_CAN1CLK_SET_MSK);
     1029        break;
     1030    case ALT_CLK_GPIO_DB:
     1031        alt_setbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_GPIOCLK_SET_MSK);
     1032        break;
     1033    case ALT_CLK_H2F_USER1:
     1034        alt_setbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK_SET_MSK);
     1035        break;
     1036    case ALT_CLK_SDMMC:
     1037        alt_setbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_SDMMCCLK_SET_MSK);
     1038        break;
     1039    case ALT_CLK_NAND_X:
     1040        // implementation detail - should ALK_CLK_NAND be gated off here before enabling ALT_CLK_NAND_X?
     1041        alt_setbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_NANDXCLK_SET_MSK);
     1042        // implementation detail - should this wait be enforced here?
     1043        alt_clk_mgr_wait(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_SW_MANAGED_CLK_WAIT_NANDCLK);
     1044        break;
     1045    case ALT_CLK_NAND:
     1046        // enabling ALT_CLK_NAND always implies enabling ALT_CLK_NAND_X first
     1047        alt_setbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_NANDXCLK_SET_MSK);
     1048        alt_clk_mgr_wait(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_SW_MANAGED_CLK_WAIT_NANDCLK);
     1049        // gate nand_x_clk on at least 8 MCU clocks before nand_clk
     1050        alt_setbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_NANDCLK_SET_MSK);
     1051        break;
     1052    case ALT_CLK_QSPI:
     1053        alt_setbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_QSPICLK_SET_MSK);
     1054        break;
     1055
     1056        // Clocks that originate at the SDRAM PLL.
     1057    case ALT_CLK_DDR_DQS:
     1058        alt_setbits_word(ALT_CLKMGR_SDRPLL_EN_ADDR, ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK_SET_MSK);
     1059        break;
     1060    case ALT_CLK_DDR_2X_DQS:
     1061        alt_setbits_word(ALT_CLKMGR_SDRPLL_EN_ADDR, ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK_SET_MSK);
     1062        break;
     1063    case ALT_CLK_DDR_DQ:
     1064        alt_setbits_word(ALT_CLKMGR_SDRPLL_EN_ADDR, ALT_CLKMGR_SDRPLL_EN_DDRDQCLK_SET_MSK);
     1065        break;
     1066    case ALT_CLK_H2F_USER2:
     1067        alt_setbits_word(ALT_CLKMGR_SDRPLL_EN_ADDR, ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK_SET_MSK);
     1068        break;
     1069
     1070    default:
     1071        status = ALT_E_BAD_ARG;
     1072        break;
     1073    }
     1074
     1075    return status;
     1076}
     1077
     1078//
     1079// alt_clk_is_enabled() returns whether the specified clock is enabled or not.
     1080//
     1081ALT_STATUS_CODE alt_clk_is_enabled(ALT_CLK_t clk)
     1082{
     1083    ALT_STATUS_CODE status = ALT_E_BAD_ARG;
     1084
     1085    switch (clk)
     1086    {
     1087        // For PLLs, this function checks if the PLL is bypassed or not.
     1088    case ALT_CLK_MAIN_PLL:
     1089    case ALT_CLK_PERIPHERAL_PLL:
     1090    case ALT_CLK_SDRAM_PLL:
     1091        status = (alt_clk_pll_is_bypassed(clk) != ALT_E_TRUE);
     1092        break;
     1093
     1094        // These clocks are not gated, so must return a ALT_E_BAD_ARG type error.
     1095    case ALT_CLK_MAIN_PLL_C0:
     1096    case ALT_CLK_MAIN_PLL_C1:
     1097    case ALT_CLK_MAIN_PLL_C2:
     1098    case ALT_CLK_MAIN_PLL_C3:
     1099    case ALT_CLK_MAIN_PLL_C4:
     1100    case ALT_CLK_MAIN_PLL_C5:
     1101    case ALT_CLK_MPU:
     1102    case ALT_CLK_MPU_L2_RAM:
     1103    case ALT_CLK_MPU_PERIPH:
     1104    case ALT_CLK_L3_MAIN:
     1105    case ALT_CLK_L3_SP:
     1106    case ALT_CLK_DBG_BASE:
     1107    case ALT_CLK_MAIN_QSPI:
     1108    case ALT_CLK_MAIN_NAND_SDMMC:
     1109    case ALT_CLK_PERIPHERAL_PLL_C0:
     1110    case ALT_CLK_PERIPHERAL_PLL_C1:
     1111    case ALT_CLK_PERIPHERAL_PLL_C2:
     1112    case ALT_CLK_PERIPHERAL_PLL_C3:
     1113    case ALT_CLK_PERIPHERAL_PLL_C4:
     1114    case ALT_CLK_PERIPHERAL_PLL_C5:
     1115    case ALT_CLK_SDRAM_PLL_C0:
     1116    case ALT_CLK_SDRAM_PLL_C1:
     1117    case ALT_CLK_SDRAM_PLL_C2:
     1118    case ALT_CLK_SDRAM_PLL_C5:
     1119        status = ALT_E_BAD_ARG;
     1120        break;
     1121
     1122        // Clocks that originate at the Main PLL.
     1123    case ALT_CLK_L4_MAIN:
     1124        status = (ALT_CLKMGR_MAINPLL_EN_L4MAINCLK_GET(alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR)))
     1125            ? ALT_E_TRUE : ALT_E_FALSE;
     1126        break;
     1127    case ALT_CLK_L3_MP:
     1128        status = (ALT_CLKMGR_MAINPLL_EN_L3MPCLK_GET(alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR)))
     1129            ? ALT_E_TRUE : ALT_E_FALSE;
     1130        break;
     1131    case ALT_CLK_L4_MP:
     1132        status = (ALT_CLKMGR_MAINPLL_EN_L4MPCLK_GET(alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR)))
     1133            ? ALT_E_TRUE : ALT_E_FALSE;
     1134        break;
     1135    case ALT_CLK_L4_SP:
     1136        status = (ALT_CLKMGR_MAINPLL_EN_L4SPCLK_GET(alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR)))
     1137            ? ALT_E_TRUE : ALT_E_FALSE;
     1138        break;
     1139    case ALT_CLK_DBG_AT:
     1140        status = (ALT_CLKMGR_MAINPLL_EN_DBGATCLK_GET(alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR)))
     1141            ? ALT_E_TRUE : ALT_E_FALSE;
     1142        break;
     1143    case ALT_CLK_DBG:
     1144        status = (ALT_CLKMGR_MAINPLL_EN_DBGCLK_GET(alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR)))
     1145            ? ALT_E_TRUE : ALT_E_FALSE;
     1146        break;
     1147    case ALT_CLK_DBG_TRACE:
     1148        status = (ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK_GET(alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR)))
     1149            ? ALT_E_TRUE : ALT_E_FALSE;
     1150        break;
     1151    case ALT_CLK_DBG_TIMER:
     1152        status = (ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK_GET(alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR)))
     1153            ? ALT_E_TRUE : ALT_E_FALSE;
     1154        break;
     1155    case ALT_CLK_CFG:
     1156        status = (ALT_CLKMGR_MAINPLL_EN_CFGCLK_GET(alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR)))
     1157            ? ALT_E_TRUE : ALT_E_FALSE;
     1158        break;
     1159    case ALT_CLK_H2F_USER0:
     1160        status = (ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK_GET(alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR)))
     1161            ? ALT_E_TRUE : ALT_E_FALSE;
     1162        break;
     1163
     1164        // Clocks that originate at the Peripheral PLL.
     1165    case ALT_CLK_EMAC0:
     1166        status = (ALT_CLKMGR_PERPLL_EN_EMAC0CLK_GET(alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR)))
     1167            ? ALT_E_TRUE : ALT_E_FALSE;
     1168        break;
     1169    case ALT_CLK_EMAC1:
     1170        status = (ALT_CLKMGR_PERPLL_EN_EMAC1CLK_GET(alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR)))
     1171            ? ALT_E_TRUE : ALT_E_FALSE;
     1172        break;
     1173    case ALT_CLK_USB_MP:
     1174        status = (ALT_CLKMGR_PERPLL_EN_USBCLK_GET(alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR)))
     1175            ? ALT_E_TRUE : ALT_E_FALSE;
     1176        break;
     1177    case ALT_CLK_SPI_M:
     1178        status = (ALT_CLKMGR_PERPLL_EN_SPIMCLK_GET(alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR)))
     1179            ? ALT_E_TRUE : ALT_E_FALSE;
     1180        break;
     1181    case ALT_CLK_CAN0:
     1182        status = (ALT_CLKMGR_PERPLL_EN_CAN0CLK_GET(alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR)))
     1183            ? ALT_E_TRUE : ALT_E_FALSE;
     1184        break;
     1185    case ALT_CLK_CAN1:
     1186        status = (ALT_CLKMGR_PERPLL_EN_CAN1CLK_GET(alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR)))
     1187            ? ALT_E_TRUE : ALT_E_FALSE;
     1188        break;
     1189    case ALT_CLK_GPIO_DB:
     1190        status = (ALT_CLKMGR_PERPLL_EN_GPIOCLK_GET(alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR)))
     1191            ? ALT_E_TRUE : ALT_E_FALSE;
     1192        break;
     1193    case ALT_CLK_H2F_USER1:
     1194        status = (ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK_GET(alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR)))
     1195            ? ALT_E_TRUE : ALT_E_FALSE;
     1196        break;
     1197
     1198        // Clocks that may originate at the Main PLL, the Peripheral PLL, or the FPGA.
     1199    case ALT_CLK_SDMMC:
     1200        status = (ALT_CLKMGR_PERPLL_EN_SDMMCCLK_GET(alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR)))
     1201            ? ALT_E_TRUE : ALT_E_FALSE;
     1202        break;
     1203    case ALT_CLK_NAND_X:
     1204        status = (ALT_CLKMGR_PERPLL_EN_NANDXCLK_GET(alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR)))
     1205            ? ALT_E_TRUE : ALT_E_FALSE;
     1206        break;
     1207    case ALT_CLK_NAND:
     1208        status = (ALT_CLKMGR_PERPLL_EN_NANDCLK_GET(alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR)))
     1209            ? ALT_E_TRUE : ALT_E_FALSE;
     1210        break;
     1211    case ALT_CLK_QSPI:
     1212        status = (ALT_CLKMGR_PERPLL_EN_QSPICLK_GET(alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR)))
     1213            ? ALT_E_TRUE : ALT_E_FALSE;
     1214        break;
     1215
     1216        // Clocks that originate at the SDRAM PLL.
     1217    case ALT_CLK_DDR_DQS:
     1218        status = (ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK_GET(alt_read_word(ALT_CLKMGR_SDRPLL_EN_ADDR)))
     1219            ? ALT_E_TRUE : ALT_E_FALSE;
     1220        break;
     1221    case ALT_CLK_DDR_2X_DQS:
     1222        status = (ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK_GET(alt_read_word(ALT_CLKMGR_SDRPLL_EN_ADDR)))
     1223            ? ALT_E_TRUE : ALT_E_FALSE;
     1224        break;
     1225    case ALT_CLK_DDR_DQ:
     1226        status = (ALT_CLKMGR_SDRPLL_EN_DDRDQCLK_GET(alt_read_word(ALT_CLKMGR_SDRPLL_EN_ADDR)))
     1227            ? ALT_E_TRUE : ALT_E_FALSE;
     1228        break;
     1229    case ALT_CLK_H2F_USER2:
     1230        status = (ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK_GET(alt_read_word(ALT_CLKMGR_SDRPLL_EN_ADDR)))
     1231            ? ALT_E_TRUE : ALT_E_FALSE;
     1232        break;
     1233
     1234    default:
     1235        status = ALT_E_BAD_ARG;
     1236        break;
     1237
     1238    }
     1239
     1240    return status;
     1241}
     1242
     1243//
     1244// alt_clk_source_get() gets the input reference clock source selection value for the
     1245// specified clock or PLL.
     1246//
     1247ALT_CLK_t alt_clk_source_get(ALT_CLK_t clk)
     1248{
     1249    ALT_CLK_t ret = ALT_CLK_UNKNOWN;
     1250    uint32_t  temp;
     1251
     1252    switch (clk)
     1253    {
     1254        // Potential external clock sources.
     1255        // these clock entities are their own source
     1256    case ALT_CLK_IN_PIN_OSC1:
     1257    case ALT_CLK_IN_PIN_OSC2:
     1258    case ALT_CLK_F2H_PERIPH_REF:
     1259    case ALT_CLK_F2H_SDRAM_REF:
     1260    case ALT_CLK_IN_PIN_JTAG:
     1261    case ALT_CLK_IN_PIN_ULPI0:
     1262    case ALT_CLK_IN_PIN_ULPI1:
     1263    case ALT_CLK_IN_PIN_EMAC0_RX:
     1264    case ALT_CLK_IN_PIN_EMAC1_RX:
     1265        ret = clk;
     1266        break;
     1267
     1268        // Phase-Locked Loops.
     1269    case ALT_CLK_MAIN_PLL:
     1270    case ALT_CLK_OSC1:
     1271        ret = ALT_CLK_IN_PIN_OSC1;
     1272        break;
     1273    case ALT_CLK_PERIPHERAL_PLL:
     1274        ret = alt_clk_pll_source_get(ALT_CLK_PERIPHERAL_PLL);
     1275        break;
     1276    case ALT_CLK_SDRAM_PLL:
     1277        ret = alt_clk_pll_source_get(ALT_CLK_SDRAM_PLL);
     1278        break;
     1279
     1280        // Main Clock Group.
     1281    case ALT_CLK_MAIN_PLL_C0:
     1282    case ALT_CLK_MAIN_PLL_C1:
     1283    case ALT_CLK_MAIN_PLL_C2:
     1284    case ALT_CLK_MAIN_PLL_C3:
     1285    case ALT_CLK_MAIN_PLL_C4:
     1286    case ALT_CLK_MAIN_PLL_C5:
     1287        // check bypass, return either osc1 or PLL ID
     1288        ret = (alt_clk_pll_is_bypassed(ALT_CLK_MAIN_PLL) == ALT_E_TRUE) ?
     1289            ALT_CLK_IN_PIN_OSC1 : ALT_CLK_MAIN_PLL;
     1290        break;
     1291
     1292    case ALT_CLK_MPU_PERIPH:
     1293    case ALT_CLK_MPU_L2_RAM:
     1294    case ALT_CLK_MPU:
     1295        ret = (alt_clk_pll_is_bypassed(ALT_CLK_MAIN_PLL) == ALT_E_TRUE) ?
     1296            ALT_CLK_IN_PIN_OSC1 : ALT_CLK_MAIN_PLL_C0;
     1297        break;
     1298
     1299    case ALT_CLK_L4_MAIN:
     1300    case ALT_CLK_L3_MAIN:
     1301    case ALT_CLK_L3_MP:
     1302    case ALT_CLK_L3_SP:
     1303        ret = (alt_clk_pll_is_bypassed(ALT_CLK_MAIN_PLL) == ALT_E_TRUE) ?
     1304            ALT_CLK_IN_PIN_OSC1 : ALT_CLK_MAIN_PLL_C1;
     1305        break;
     1306
     1307    case ALT_CLK_L4_MP:
     1308        // read the state of the L4_mp source bit
     1309        if ((ALT_CLKMGR_MAINPLL_L4SRC_L4MP_GET(alt_read_word(ALT_CLKMGR_MAINPLL_L4SRC_ADDR)))
     1310            == ALT_CLKMGR_MAINPLL_L4SRC_L4MP_E_MAINPLL)
     1311        {
     1312            ret = (alt_clk_pll_is_bypassed(ALT_CLK_MAIN_PLL) == ALT_E_TRUE) ?
     1313                ALT_CLK_IN_PIN_OSC1 : ALT_CLK_MAIN_PLL_C1;
     1314        }
     1315        else
     1316        {
     1317            // if the clock comes from periph_base_clk
     1318            ret = (alt_clk_pll_is_bypassed(ALT_CLK_PERIPHERAL_PLL) == ALT_E_TRUE) ?
     1319                alt_clk_pll_source_get(ALT_CLK_PERIPHERAL_PLL) : ALT_CLK_PERIPHERAL_PLL_C4;
     1320        }
     1321        break;
     1322
     1323    case ALT_CLK_L4_SP:
     1324        // read the state of the source bit
     1325        if ((ALT_CLKMGR_MAINPLL_L4SRC_L4SP_GET(alt_read_word(ALT_CLKMGR_MAINPLL_L4SRC_ADDR)))
     1326            == ALT_CLKMGR_MAINPLL_L4SRC_L4SP_E_MAINPLL)
     1327        {
     1328            ret = (alt_clk_pll_is_bypassed(ALT_CLK_MAIN_PLL) == ALT_E_TRUE) ?
     1329                ALT_CLK_IN_PIN_OSC1 : ALT_CLK_MAIN_PLL_C1;
     1330        }
     1331        else
     1332        {
     1333            // if the clock comes from periph_base_clk
     1334            ret = (alt_clk_pll_is_bypassed(ALT_CLK_PERIPHERAL_PLL) == ALT_E_TRUE) ?
     1335                alt_clk_pll_source_get(ALT_CLK_PERIPHERAL_PLL) : ALT_CLK_PERIPHERAL_PLL_C4;
     1336        }
     1337        break;
     1338
     1339    case ALT_CLK_DBG_BASE:
     1340    case ALT_CLK_DBG_AT:
     1341    case ALT_CLK_DBG_TRACE:
     1342    case ALT_CLK_DBG_TIMER:
     1343    case ALT_CLK_DBG:
     1344        ret = (alt_clk_pll_is_bypassed(ALT_CLK_MAIN_PLL) == ALT_E_TRUE) ?
     1345            ALT_CLK_OSC1 : ALT_CLK_MAIN_PLL_C2;
     1346        break;
     1347    case ALT_CLK_MAIN_QSPI:
     1348        ret = (alt_clk_pll_is_bypassed(ALT_CLK_MAIN_PLL) == ALT_E_TRUE) ?
     1349            ALT_CLK_OSC1 : ALT_CLK_MAIN_PLL_C3;
     1350        break;
     1351    case ALT_CLK_MAIN_NAND_SDMMC:
     1352        ret = (alt_clk_pll_is_bypassed(ALT_CLK_MAIN_PLL) == ALT_E_TRUE) ?
     1353            ALT_CLK_OSC1 : ALT_CLK_MAIN_PLL_C4;
     1354        break;
     1355    case ALT_CLK_CFG:
     1356    case ALT_CLK_H2F_USER0:
     1357        ret = (alt_clk_pll_is_bypassed(ALT_CLK_MAIN_PLL) == ALT_E_TRUE) ?
     1358            ALT_CLK_OSC1 : ALT_CLK_MAIN_PLL_C5;
     1359        break;
     1360
     1361        // Peripherals Clock Group
     1362    case ALT_CLK_PERIPHERAL_PLL_C0:
     1363    case ALT_CLK_PERIPHERAL_PLL_C1:
     1364    case ALT_CLK_PERIPHERAL_PLL_C2:
     1365    case ALT_CLK_PERIPHERAL_PLL_C3:
     1366    case ALT_CLK_PERIPHERAL_PLL_C4:
     1367    case ALT_CLK_PERIPHERAL_PLL_C5:
     1368        // if the clock comes from periph_base_clk
     1369        ret = (alt_clk_pll_is_bypassed(ALT_CLK_PERIPHERAL_PLL) == ALT_E_TRUE) ?
     1370            alt_clk_pll_source_get(ALT_CLK_PERIPHERAL_PLL) : ALT_CLK_PERIPHERAL_PLL;
     1371        break;
     1372
     1373    case ALT_CLK_EMAC0:
     1374        ret = (alt_clk_pll_is_bypassed(ALT_CLK_PERIPHERAL_PLL) == ALT_E_TRUE) ?
     1375            alt_clk_pll_source_get(ALT_CLK_PERIPHERAL_PLL) :  ALT_CLK_PERIPHERAL_PLL_C0;
     1376        break;
     1377
     1378    case ALT_CLK_EMAC1:
     1379        ret = (alt_clk_pll_is_bypassed(ALT_CLK_PERIPHERAL_PLL) == ALT_E_TRUE) ?
     1380            alt_clk_pll_source_get(ALT_CLK_PERIPHERAL_PLL) :  ALT_CLK_PERIPHERAL_PLL_C1;
     1381        break;
     1382
     1383    case ALT_CLK_USB_MP:
     1384    case ALT_CLK_SPI_M:
     1385    case ALT_CLK_CAN0:
     1386    case ALT_CLK_CAN1:
     1387    case ALT_CLK_GPIO_DB:
     1388        ret = (alt_clk_pll_is_bypassed(ALT_CLK_PERIPHERAL_PLL) == ALT_E_TRUE) ?
     1389            alt_clk_pll_source_get(ALT_CLK_PERIPHERAL_PLL) :  ALT_CLK_PERIPHERAL_PLL_C4;
     1390        break;
     1391
     1392    case ALT_CLK_H2F_USER1:
     1393        ret = (alt_clk_pll_is_bypassed(ALT_CLK_PERIPHERAL_PLL) == ALT_E_TRUE) ?
     1394            alt_clk_pll_source_get(ALT_CLK_PERIPHERAL_PLL) :  ALT_CLK_PERIPHERAL_PLL_C5;
     1395        break;
     1396
     1397    case ALT_CLK_SDMMC:
     1398        temp = ALT_CLKMGR_PERPLL_SRC_SDMMC_GET(alt_read_word(ALT_CLKMGR_PERPLL_SRC_ADDR));
     1399        if (temp == ALT_CLKMGR_PERPLL_SRC_SDMMC_E_F2S_PERIPH_REF_CLK)
     1400        {
     1401            ret = ALT_CLK_F2H_PERIPH_REF;
     1402        }
     1403        else if (temp == ALT_CLKMGR_PERPLL_SRC_SDMMC_E_MAIN_NAND_CLK)
     1404        {
     1405            ret = (alt_clk_pll_is_bypassed(ALT_CLK_MAIN_PLL) == ALT_E_TRUE) ?
     1406                ALT_CLK_IN_PIN_OSC1 : ALT_CLK_MAIN_PLL_C4;
     1407        }
     1408        else if (temp == ALT_CLKMGR_PERPLL_SRC_SDMMC_E_PERIPH_NAND_CLK)
     1409        {
     1410            ret = (alt_clk_pll_is_bypassed(ALT_CLK_PERIPHERAL_PLL) == ALT_E_TRUE) ?
     1411                alt_clk_pll_source_get(ALT_CLK_PERIPHERAL_PLL) :  ALT_CLK_PERIPHERAL_PLL_C3;
     1412        }
     1413        break;
     1414
     1415    case ALT_CLK_NAND_X:
     1416    case ALT_CLK_NAND:
     1417        temp = ALT_CLKMGR_PERPLL_SRC_NAND_GET(alt_read_word(ALT_CLKMGR_PERPLL_SRC_ADDR));
     1418        if (temp == ALT_CLKMGR_PERPLL_SRC_NAND_E_F2S_PERIPH_REF_CLK)
     1419        {
     1420            ret = ALT_CLK_F2H_PERIPH_REF;
     1421        }
     1422        else if (temp == ALT_CLKMGR_PERPLL_SRC_NAND_E_MAIN_NAND_CLK)
     1423        {
     1424            ret = (alt_clk_pll_is_bypassed(ALT_CLK_MAIN_PLL) == ALT_E_TRUE) ?
     1425                ALT_CLK_IN_PIN_OSC1 : ALT_CLK_MAIN_PLL_C4;
     1426        }
     1427        else if (temp == ALT_CLKMGR_PERPLL_SRC_NAND_E_PERIPH_NAND_CLK)
     1428        {
     1429            ret = (alt_clk_pll_is_bypassed(ALT_CLK_PERIPHERAL_PLL) == ALT_E_TRUE) ?
     1430                alt_clk_pll_source_get(ALT_CLK_PERIPHERAL_PLL) :  ALT_CLK_PERIPHERAL_PLL_C3;
     1431        }
     1432        break;
     1433
     1434    case ALT_CLK_QSPI:
     1435        temp = ALT_CLKMGR_PERPLL_SRC_QSPI_GET(alt_read_word(ALT_CLKMGR_PERPLL_SRC_ADDR));
     1436        if (temp == ALT_CLKMGR_PERPLL_SRC_QSPI_E_F2S_PERIPH_REF_CLK)
     1437        {
     1438            ret = ALT_CLK_F2H_PERIPH_REF;
     1439        }
     1440        else if (temp == ALT_CLKMGR_PERPLL_SRC_QSPI_E_MAIN_QSPI_CLK)
     1441        {
     1442            ret = (alt_clk_pll_is_bypassed(ALT_CLK_MAIN_PLL) == ALT_E_TRUE) ?
     1443                ALT_CLK_IN_PIN_OSC1 : ALT_CLK_MAIN_PLL_C3;
     1444        }
     1445        else if (temp == ALT_CLKMGR_PERPLL_SRC_QSPI_E_PERIPH_QSPI_CLK)
     1446        {
     1447            ret = (alt_clk_pll_is_bypassed(ALT_CLK_PERIPHERAL_PLL) == ALT_E_TRUE) ?
     1448                alt_clk_pll_source_get(ALT_CLK_PERIPHERAL_PLL) :  ALT_CLK_PERIPHERAL_PLL_C2;
     1449        }
     1450        break;
     1451
     1452        // SDRAM Clock Group
     1453    case ALT_CLK_SDRAM_PLL_C0:
     1454    case ALT_CLK_SDRAM_PLL_C1:
     1455    case ALT_CLK_SDRAM_PLL_C2:
     1456    case ALT_CLK_SDRAM_PLL_C3:
     1457    case ALT_CLK_SDRAM_PLL_C4:
     1458    case ALT_CLK_SDRAM_PLL_C5:
     1459        ret = (alt_clk_pll_is_bypassed(ALT_CLK_SDRAM_PLL) == ALT_E_TRUE) ?
     1460            alt_clk_pll_source_get(ALT_CLK_SDRAM_PLL) :  ALT_CLK_SDRAM_PLL;
     1461        break;
     1462    case ALT_CLK_DDR_DQS:
     1463        ret = (alt_clk_pll_is_bypassed(ALT_CLK_SDRAM_PLL) == ALT_E_TRUE) ?
     1464            alt_clk_pll_source_get(ALT_CLK_SDRAM_PLL) :  ALT_CLK_SDRAM_PLL_C0;
     1465        break;
     1466    case ALT_CLK_DDR_2X_DQS:
     1467        ret = (alt_clk_pll_is_bypassed(ALT_CLK_SDRAM_PLL) == ALT_E_TRUE) ?
     1468            alt_clk_pll_source_get(ALT_CLK_SDRAM_PLL) :  ALT_CLK_SDRAM_PLL_C1;
     1469        break;
     1470    case ALT_CLK_DDR_DQ:
     1471        ret = (alt_clk_pll_is_bypassed(ALT_CLK_SDRAM_PLL) == ALT_E_TRUE) ?
     1472            alt_clk_pll_source_get(ALT_CLK_SDRAM_PLL) :  ALT_CLK_SDRAM_PLL_C2;
     1473        break;
     1474    case ALT_CLK_H2F_USER2:
     1475        ret = (alt_clk_pll_is_bypassed(ALT_CLK_SDRAM_PLL) == ALT_E_TRUE) ?
     1476            alt_clk_pll_source_get(ALT_CLK_SDRAM_PLL) :  ALT_CLK_SDRAM_PLL_C5;
     1477        break;
     1478
     1479        // Clock Output Pins
     1480    case ALT_CLK_OUT_PIN_EMAC0_TX:
     1481    case ALT_CLK_OUT_PIN_EMAC1_TX:
     1482    case ALT_CLK_OUT_PIN_SDMMC:
     1483    case ALT_CLK_OUT_PIN_I2C0_SCL:
     1484    case ALT_CLK_OUT_PIN_I2C1_SCL:
     1485    case ALT_CLK_OUT_PIN_I2C2_SCL:
     1486    case ALT_CLK_OUT_PIN_I2C3_SCL:
     1487    case ALT_CLK_OUT_PIN_SPIM0:
     1488    case ALT_CLK_OUT_PIN_SPIM1:
     1489    case ALT_CLK_OUT_PIN_QSPI:
     1490        ret = ALT_CLK_UNKNOWN;
     1491        break;
     1492
     1493    default:
     1494        ret = ALT_CLK_UNKNOWN;
     1495        break;
     1496    }
     1497
    9231498    return ret;
    9241499}
    9251500
    926 
    927 /****************************************************************************************/
    928 /* alt_clk_clock_enable() enables the specified clock. Once the clock is enabled, its   */
    929 /* clock signal propagates to its elements.                                             */
    930 /****************************************************************************************/
    931 
    932 
    933 ALT_STATUS_CODE alt_clk_clock_enable(ALT_CLK_t clk)
     1501//
     1502// alt_clk_source_set() sets the specified clock's input reference clock source
     1503// selection to the specified input. It does not handle gating the specified clock
     1504// off and back on, those are covered in other functions in this API, but it does
     1505// verify that the clock is off before changing the divider or PLL. Note that the PLL
     1506// must have regained phase-lock before being the bypass is disabled.
     1507//
     1508ALT_STATUS_CODE alt_clk_source_set(ALT_CLK_t clk, ALT_CLK_t ref_clk)
    9341509{
    935     ALT_STATUS_CODE     ret = ALT_E_BAD_ARG;
    936 
    937     switch (clk)
    938     {
    939             /* For PLLs, take them out of bypass mode */
    940         case (ALT_CLK_MAIN_PLL):
    941         case (ALT_CLK_PERIPHERAL_PLL):
    942         case (ALT_CLK_SDRAM_PLL):
    943             ret = alt_clk_pll_bypass_disable(clk);
    944             break;
    945 
    946 
    947         /* Clocks that originate at the Main PLL */
    948         case (ALT_CLK_L4_MAIN):
    949             alt_setbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_L4MAINCLK_SET_MSK);
    950             ret = ALT_E_SUCCESS;
    951             break;
    952         case (ALT_CLK_L3_MP):
    953             alt_setbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_L3MPCLK_SET_MSK);
    954             ret = ALT_E_SUCCESS;
    955             break;
    956         case (ALT_CLK_L4_MP):
    957             alt_setbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_L4MPCLK_SET_MSK);
    958             ret = ALT_E_SUCCESS;
    959             break;
    960         case (ALT_CLK_L4_SP):
    961             alt_setbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_L4SPCLK_SET_MSK);
    962             ret = ALT_E_SUCCESS;
    963             break;
    964         case (ALT_CLK_DBG_AT):
    965             alt_setbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_DBGATCLK_SET_MSK);
    966             ret = ALT_E_SUCCESS;
    967             break;
    968         case (ALT_CLK_DBG):
    969             alt_setbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_DBGCLK_SET_MSK);
    970             ret = ALT_E_SUCCESS;
    971             break;
    972         case (ALT_CLK_DBG_TRACE):
    973             alt_setbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK_SET_MSK);
    974             ret = ALT_E_SUCCESS;
    975             break;
    976         case (ALT_CLK_DBG_TIMER):
    977             alt_setbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK_SET_MSK);
    978             ret = ALT_E_SUCCESS;
    979             break;
    980         case (ALT_CLK_CFG):
    981             alt_setbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_CFGCLK_SET_MSK);
    982             ret = ALT_E_SUCCESS;
    983             break;
    984         case (ALT_CLK_H2F_USER0):
    985             alt_setbits_word(ALT_CLKMGR_MAINPLL_EN_ADDR, ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK_SET_MSK);
    986             ret = ALT_E_SUCCESS;
    987             break;
    988 
    989             /* Clocks that originate at the Peripheral PLL */
    990         case (ALT_CLK_EMAC0):
    991             alt_setbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_EMAC0CLK_SET_MSK);
    992             ret = ALT_E_SUCCESS;
    993             break;
    994         case (ALT_CLK_EMAC1):
    995             alt_setbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_EMAC1CLK_SET_MSK);
    996             ret = ALT_E_SUCCESS;
    997             break;
    998         case (ALT_CLK_USB_MP):
    999             alt_setbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_USBCLK_SET_MSK);
    1000             ret = ALT_E_SUCCESS;
    1001             break;
    1002         case (ALT_CLK_SPI_M):
    1003             alt_setbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_SPIMCLK_SET_MSK);
    1004             ret = ALT_E_SUCCESS;
    1005             break;
    1006         case (ALT_CLK_CAN0):
    1007             alt_setbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_CAN0CLK_SET_MSK);
    1008             ret = ALT_E_SUCCESS;
    1009             break;
    1010         case (ALT_CLK_CAN1):
    1011             alt_setbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_CAN1CLK_SET_MSK);
    1012             ret = ALT_E_SUCCESS;
    1013             break;
    1014         case (ALT_CLK_GPIO_DB):
    1015             alt_setbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_GPIOCLK_SET_MSK);
    1016             ret = ALT_E_SUCCESS;
    1017             break;
    1018         case (ALT_CLK_H2F_USER1):
    1019             alt_setbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK_SET_MSK);
    1020             ret = ALT_E_SUCCESS;
    1021             break;
    1022         case (ALT_CLK_SDMMC):
    1023             alt_setbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_SDMMCCLK_SET_MSK);
    1024             ret = ALT_E_SUCCESS;
    1025             break;
    1026         case (ALT_CLK_NAND_X):
    1027                 // implementation detail - should ALK_CLK_NAND be gated off here before enabling ALT_CLK_NAND_X?
    1028             alt_setbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_NANDXCLK_SET_MSK);
    1029                 // implementation detail - should this wait be enforced here?
    1030             alt_clk_mgr_wait(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_SW_MANAGED_CLK_WAIT_NANDCLK);
    1031             ret = ALT_E_SUCCESS;
    1032             break;
    1033         case (ALT_CLK_NAND):
    1034                 // enabling ALT_CLK_NAND always implies enabling ALT_CLK_NAND_X first
    1035             alt_setbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_NANDXCLK_SET_MSK);
    1036             alt_clk_mgr_wait(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_SW_MANAGED_CLK_WAIT_NANDCLK);
    1037                 // gate nand_x_clk on at least 8 MCU clocks before nand_clk
    1038             alt_setbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_NANDCLK_SET_MSK);
    1039             ret = ALT_E_SUCCESS;
    1040             break;
    1041         case (ALT_CLK_QSPI):
    1042             alt_setbits_word(ALT_CLKMGR_PERPLL_EN_ADDR, ALT_CLKMGR_PERPLL_EN_QSPICLK_SET_MSK);
    1043             ret = ALT_E_SUCCESS;
    1044             break;
    1045 
    1046         /* Clocks that originate at the SDRAM PLL */
    1047         case (ALT_CLK_DDR_DQS):
    1048             alt_setbits_word(ALT_CLKMGR_SDRPLL_EN_ADDR, ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK_SET_MSK);
    1049             ret = ALT_E_SUCCESS;
    1050             break;
    1051 
    1052         case (ALT_CLK_DDR_2X_DQS):
    1053             alt_setbits_word(ALT_CLKMGR_SDRPLL_EN_ADDR, ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK_SET_MSK);
    1054             ret = ALT_E_SUCCESS;
    1055             break;
    1056 
    1057         case (ALT_CLK_DDR_DQ):
    1058             alt_setbits_word(ALT_CLKMGR_SDRPLL_EN_ADDR, ALT_CLKMGR_SDRPLL_EN_DDRDQCLK_SET_MSK);
    1059             ret = ALT_E_SUCCESS;
    1060             break;
    1061 
    1062         case (ALT_CLK_H2F_USER2):
    1063             alt_setbits_word(ALT_CLKMGR_SDRPLL_EN_ADDR, ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK_SET_MSK);
    1064             ret = ALT_E_SUCCESS;
    1065             break;
    1066 
    1067         default: break;
    1068    }
     1510    ALT_STATUS_CODE status = ALT_E_SUCCESS;
     1511    uint32_t        temp;
     1512
     1513    if (ALT_CLK_MAIN_PLL == clk)
     1514    {
     1515        if ((ref_clk == ALT_CLK_IN_PIN_OSC1) || (ref_clk == ALT_CLK_OSC1))
     1516        {
     1517            // ret = ALT_E_SUCCESS;
     1518        }
     1519        else
     1520        {
     1521            status = ALT_E_BAD_ARG;
     1522        }
     1523    }
     1524    else if (ALT_CLK_PERIPHERAL_PLL == clk)
     1525    {
     1526        // the PLL must be bypassed before getting here
     1527        temp  = alt_read_word(ALT_CLKMGR_PERPLL_VCO_ADDR);
     1528        temp &= ALT_CLKMGR_PERPLL_VCO_PSRC_CLR_MSK;
     1529
     1530        if ((ref_clk == ALT_CLK_IN_PIN_OSC1) || (ref_clk == ALT_CLK_OSC1))
     1531        {
     1532            temp |= ALT_CLKMGR_PERPLL_VCO_PSRC_SET(ALT_CLKMGR_PERPLL_VCO_PSRC_E_EOSC1);
     1533            alt_write_word(ALT_CLKMGR_PERPLL_VCO_ADDR, temp);
     1534        }
     1535        else if (ref_clk == ALT_CLK_IN_PIN_OSC2)
     1536        {
     1537            temp |= ALT_CLKMGR_PERPLL_VCO_PSRC_SET(ALT_CLKMGR_PERPLL_VCO_PSRC_E_EOSC2);
     1538            alt_write_word(ALT_CLKMGR_PERPLL_VCO_ADDR, temp);
     1539        }
     1540        else if (ref_clk == ALT_CLK_F2H_PERIPH_REF)
     1541        {
     1542            temp |= ALT_CLKMGR_PERPLL_VCO_PSRC_SET(ALT_CLKMGR_PERPLL_VCO_PSRC_E_F2S_PERIPH_REF);
     1543            alt_write_word(ALT_CLKMGR_PERPLL_VCO_ADDR, temp);
     1544        }
     1545        else
     1546        {
     1547            status = ALT_E_INV_OPTION;
     1548        }
     1549    }
     1550    else if (ALT_CLK_SDRAM_PLL == clk)
     1551    {
     1552        temp  = alt_read_word(ALT_CLKMGR_SDRPLL_VCO_ADDR);
     1553        temp &= ALT_CLKMGR_SDRPLL_VCO_SSRC_CLR_MSK;
     1554
     1555        if ((ref_clk == ALT_CLK_IN_PIN_OSC1) || (ref_clk == ALT_CLK_OSC1))
     1556        {
     1557            temp |= ALT_CLKMGR_SDRPLL_VCO_SSRC_SET(ALT_CLKMGR_SDRPLL_VCO_SSRC_E_EOSC1);
     1558            alt_write_word(ALT_CLKMGR_SDRPLL_VCO_ADDR, temp);
     1559        }
     1560        else if (ref_clk == ALT_CLK_IN_PIN_OSC2)
     1561        {
     1562            temp |= ALT_CLKMGR_SDRPLL_VCO_SSRC_SET(ALT_CLKMGR_SDRPLL_VCO_SSRC_E_EOSC2);
     1563            alt_write_word(ALT_CLKMGR_SDRPLL_VCO_ADDR, temp);
     1564        }
     1565        else if (ref_clk == ALT_CLK_F2H_SDRAM_REF)
     1566        {
     1567            temp |= ALT_CLKMGR_SDRPLL_VCO_SSRC_SET(ALT_CLKMGR_SDRPLL_VCO_SSRC_E_F2S_SDRAM_REF);
     1568            alt_write_word(ALT_CLKMGR_SDRPLL_VCO_ADDR, temp);
     1569        }
     1570        else
     1571        {
     1572            status = ALT_E_INV_OPTION;
     1573        }
     1574    }
     1575    else if ( ALT_CLK_L4_MP == clk)
     1576    {
     1577        // clock is gated off
     1578        if (ref_clk == ALT_CLK_MAIN_PLL_C1)
     1579        {
     1580            alt_clrbits_word(ALT_CLKMGR_MAINPLL_L4SRC_ADDR, ALT_CLKMGR_MAINPLL_L4SRC_L4MP_SET_MSK);
     1581        }
     1582        else if (ref_clk == ALT_CLK_PERIPHERAL_PLL_C4)
     1583        {
     1584            alt_setbits_word(ALT_CLKMGR_MAINPLL_L4SRC_ADDR, ALT_CLKMGR_MAINPLL_L4SRC_L4MP_SET_MSK);
     1585        }
     1586        else
     1587        {
     1588            status = ALT_E_INV_OPTION;
     1589        }
     1590    }
     1591    else if ( ALT_CLK_L4_SP == clk)
     1592    {
     1593        if (ref_clk == ALT_CLK_MAIN_PLL_C1)
     1594        {
     1595            alt_clrbits_word(ALT_CLKMGR_MAINPLL_L4SRC_ADDR, ALT_CLKMGR_MAINPLL_L4SRC_L4SP_SET_MSK);
     1596        }
     1597        else if (ref_clk == ALT_CLK_PERIPHERAL_PLL_C4)
     1598        {
     1599            alt_setbits_word(ALT_CLKMGR_MAINPLL_L4SRC_ADDR, ALT_CLKMGR_MAINPLL_L4SRC_L4SP_SET_MSK);
     1600        }
     1601        else
     1602        {
     1603            status = ALT_E_INV_OPTION;
     1604        }
     1605    }
     1606    else if (ALT_CLK_SDMMC == clk)
     1607    {
     1608        temp  = alt_read_word(ALT_CLKMGR_PERPLL_SRC_ADDR);
     1609        temp &= ALT_CLKMGR_PERPLL_SRC_SDMMC_CLR_MSK;
     1610
     1611        if (ref_clk == ALT_CLK_F2H_PERIPH_REF)
     1612        {
     1613            temp |= ALT_CLKMGR_PERPLL_SRC_SDMMC_SET(ALT_CLKMGR_PERPLL_SRC_SDMMC_E_F2S_PERIPH_REF_CLK);
     1614            alt_write_word(ALT_CLKMGR_PERPLL_SRC_ADDR, temp);
     1615        }
     1616        else if ((ref_clk == ALT_CLK_MAIN_PLL_C4) || (ref_clk == ALT_CLK_MAIN_NAND_SDMMC))
     1617        {
     1618            temp |= ALT_CLKMGR_PERPLL_SRC_SDMMC_SET(ALT_CLKMGR_PERPLL_SRC_SDMMC_E_MAIN_NAND_CLK);
     1619            alt_write_word(ALT_CLKMGR_PERPLL_SRC_ADDR, temp);
     1620        }
     1621        else if (ref_clk == ALT_CLK_PERIPHERAL_PLL_C3)
     1622        {
     1623            temp |= ALT_CLKMGR_PERPLL_SRC_SDMMC_SET(ALT_CLKMGR_PERPLL_SRC_SDMMC_E_PERIPH_NAND_CLK);
     1624            alt_write_word(ALT_CLKMGR_PERPLL_SRC_ADDR, temp);
     1625        }
     1626        else
     1627        {
     1628            status = ALT_E_INV_OPTION;
     1629        }
     1630    }
     1631    else if ((ALT_CLK_NAND_X == clk) || ( ALT_CLK_NAND == clk))
     1632    {
     1633        temp = alt_read_word(ALT_CLKMGR_PERPLL_SRC_ADDR);
     1634        temp &= ALT_CLKMGR_PERPLL_SRC_NAND_CLR_MSK;
     1635
     1636        if (ref_clk == ALT_CLK_F2H_PERIPH_REF)
     1637        {
     1638            temp |= ALT_CLKMGR_PERPLL_SRC_NAND_SET(ALT_CLKMGR_PERPLL_SRC_NAND_E_F2S_PERIPH_REF_CLK);
     1639            alt_write_word(ALT_CLKMGR_PERPLL_SRC_ADDR, temp);
     1640        }
     1641        else if ((ref_clk == ALT_CLK_MAIN_PLL_C4) || (ref_clk == ALT_CLK_MAIN_NAND_SDMMC))
     1642        {
     1643            temp |= ALT_CLKMGR_PERPLL_SRC_NAND_SET(ALT_CLKMGR_PERPLL_SRC_NAND_E_MAIN_NAND_CLK);
     1644            alt_write_word(ALT_CLKMGR_PERPLL_SRC_ADDR, temp);
     1645        }
     1646        else if (ref_clk == ALT_CLK_PERIPHERAL_PLL_C3)
     1647        {
     1648            temp |= ALT_CLKMGR_PERPLL_SRC_NAND_SET(ALT_CLKMGR_PERPLL_SRC_NAND_E_PERIPH_NAND_CLK);
     1649            alt_write_word(ALT_CLKMGR_PERPLL_SRC_ADDR, temp);
     1650        }
     1651        else
     1652        {
     1653            status = ALT_E_INV_OPTION;
     1654        }
     1655    }
     1656    else if (ALT_CLK_QSPI == clk)
     1657    {
     1658        temp  = alt_read_word(ALT_CLKMGR_PERPLL_SRC_ADDR);
     1659        temp &= ALT_CLKMGR_PERPLL_SRC_QSPI_CLR_MSK;
     1660
     1661        if (ref_clk == ALT_CLK_F2H_PERIPH_REF)
     1662        {
     1663            temp |= ALT_CLKMGR_PERPLL_SRC_QSPI_SET(ALT_CLKMGR_PERPLL_SRC_QSPI_E_F2S_PERIPH_REF_CLK);
     1664            alt_write_word(ALT_CLKMGR_PERPLL_SRC_ADDR, temp);
     1665        }
     1666        else if ((ref_clk == ALT_CLK_MAIN_PLL_C3) || (ref_clk == ALT_CLK_MAIN_QSPI))
     1667        {
     1668            temp |= ALT_CLKMGR_PERPLL_SRC_QSPI_SET(ALT_CLKMGR_PERPLL_SRC_QSPI_E_MAIN_QSPI_CLK);
     1669            alt_write_word(ALT_CLKMGR_PERPLL_SRC_ADDR, temp);
     1670        }
     1671        else if (ref_clk == ALT_CLK_PERIPHERAL_PLL_C2)
     1672        {
     1673            temp |= ALT_CLKMGR_PERPLL_SRC_QSPI_SET(ALT_CLKMGR_PERPLL_SRC_QSPI_E_PERIPH_QSPI_CLK);
     1674            alt_write_word(ALT_CLKMGR_PERPLL_SRC_ADDR, temp);
     1675        }
     1676        else
     1677        {
     1678            status = ALT_E_INV_OPTION;
     1679        }
     1680    }
     1681
     1682    return status;
     1683}
     1684
     1685//
     1686// alt_clk_ext_clk_freq_set() specifies the frequency of the external clock source as
     1687// a measure of Hz. This value is stored in a static array and used for calculations.
     1688// The supplied frequency should be within the Fmin and Fmax values allowed for the
     1689// external clock source.
     1690//
     1691ALT_STATUS_CODE alt_clk_ext_clk_freq_set(ALT_CLK_t clk, alt_freq_t freq)
     1692{
     1693    ALT_STATUS_CODE status = ALT_E_BAD_ARG;
     1694
     1695    if ((clk == ALT_CLK_IN_PIN_OSC1) || (clk == ALT_CLK_OSC1))      // two names for one input
     1696    {
     1697        if ((freq >= alt_ext_clk_paramblok.clkosc1.freqmin) && (freq <= alt_ext_clk_paramblok.clkosc1.freqmax))
     1698        {
     1699            alt_ext_clk_paramblok.clkosc1.freqcur = freq;
     1700            status = ALT_E_SUCCESS;
     1701        }
     1702        else
     1703        {
     1704            status = ALT_E_ARG_RANGE;
     1705        }
     1706    }
     1707    else if (clk == ALT_CLK_IN_PIN_OSC2)                            // the other clock input pin
     1708    {
     1709        if ((freq >= alt_ext_clk_paramblok.clkosc2.freqmin) && (freq <= alt_ext_clk_paramblok.clkosc2.freqmax))
     1710        {
     1711            alt_ext_clk_paramblok.clkosc2.freqcur = freq;
     1712            status = ALT_E_SUCCESS;
     1713        }
     1714        else
     1715        {
     1716            status = ALT_E_ARG_RANGE;
     1717        }
     1718    }
     1719    else if (clk == ALT_CLK_F2H_PERIPH_REF)                         // clock from the FPGA
     1720    {
     1721        if ((freq >= alt_ext_clk_paramblok.periph.freqmin) && (freq <= alt_ext_clk_paramblok.periph.freqmax))
     1722        {
     1723            alt_ext_clk_paramblok.periph.freqcur = freq;
     1724            status = ALT_E_SUCCESS;
     1725        }
     1726        else
     1727        {
     1728            status = ALT_E_ARG_RANGE;
     1729        }
     1730    }
     1731    else if (clk == ALT_CLK_F2H_SDRAM_REF)                          // clock from the FPGA SDRAM
     1732    {
     1733        if ((freq >= alt_ext_clk_paramblok.sdram.freqmin) && (freq <= alt_ext_clk_paramblok.sdram.freqmax))
     1734        {
     1735            alt_ext_clk_paramblok.sdram.freqcur = freq;
     1736            status = ALT_E_SUCCESS;
     1737        }
     1738        else
     1739        {
     1740            status = ALT_E_ARG_RANGE;
     1741        }
     1742    }
     1743    else
     1744    {
     1745        status = ALT_E_BAD_ARG;
     1746    }
     1747
     1748    return status;
     1749}
     1750
     1751
     1752//
     1753// alt_clk_ext_clk_freq_get returns the frequency of the external clock source as
     1754// a measure of Hz. This value is stored in a static array.
     1755//
     1756alt_freq_t alt_clk_ext_clk_freq_get(ALT_CLK_t clk)
     1757{
     1758    uint32_t ret = 0;
     1759
     1760    if ((clk == ALT_CLK_IN_PIN_OSC1) || (clk == ALT_CLK_OSC1))      // two names for one input
     1761    {
     1762        ret = alt_ext_clk_paramblok.clkosc1.freqcur;
     1763    }
     1764    else if (clk == ALT_CLK_IN_PIN_OSC2)
     1765    {
     1766        ret = alt_ext_clk_paramblok.clkosc2.freqcur;
     1767    }
     1768    else if (clk == ALT_CLK_F2H_PERIPH_REF)                         // clock from the FPGA
     1769    {
     1770        ret = alt_ext_clk_paramblok.periph.freqcur;
     1771    }
     1772    else if (clk == ALT_CLK_F2H_SDRAM_REF)                         // clock from the FPGA
     1773    {
     1774        ret = alt_ext_clk_paramblok.sdram.freqcur;
     1775    }
    10691776    return ret;
    10701777}
    10711778
    10721779
    1073 /****************************************************************************************/
    1074 /* alt_clk_is_enabled() returns whether the specified clock is enabled or not.          */
    1075 /****************************************************************************************/
    1076 
    1077 ALT_STATUS_CODE alt_clk_is_enabled(ALT_CLK_t clk)
     1780//
     1781// alt_clk_pll_cfg_get() returns the current PLL configuration.
     1782//
     1783ALT_STATUS_CODE alt_clk_pll_cfg_get(ALT_CLK_t pll, ALT_CLK_PLL_CFG_t * pll_cfg)
    10781784{
    1079     ALT_STATUS_CODE     ret = ALT_E_BAD_ARG;
    1080 
    1081     switch (clk)            // this should be more than enough cases to cause
    1082     {                       // the compiler to use a jump table implementation
    1083 
    1084         /* For PLLs, this function checks if the PLL is bypassed or not */
    1085         case (ALT_CLK_MAIN_PLL):
    1086         case (ALT_CLK_PERIPHERAL_PLL):
    1087         case (ALT_CLK_SDRAM_PLL):
    1088             ret = (alt_clk_pll_is_bypassed(clk) != ALT_E_TRUE);
    1089             break;
    1090 
    1091         /* These clocks are not gated, so must return a ALT_E_BAD_ARG type error */
    1092         case (ALT_CLK_MAIN_PLL_C0):
    1093         case (ALT_CLK_MAIN_PLL_C1):
    1094         case (ALT_CLK_MAIN_PLL_C2):
    1095         case (ALT_CLK_MAIN_PLL_C3):
    1096         case (ALT_CLK_MAIN_PLL_C4):
    1097         case (ALT_CLK_MAIN_PLL_C5):
    1098         case (ALT_CLK_MPU):
    1099         case (ALT_CLK_MPU_L2_RAM):
    1100         case (ALT_CLK_MPU_PERIPH):
    1101         case (ALT_CLK_L3_MAIN):
    1102         case (ALT_CLK_L3_SP):
    1103         case (ALT_CLK_DBG_BASE):
    1104         case (ALT_CLK_MAIN_QSPI):
    1105         case (ALT_CLK_MAIN_NAND_SDMMC):
    1106         case (ALT_CLK_PERIPHERAL_PLL_C0):
    1107         case (ALT_CLK_PERIPHERAL_PLL_C1):
    1108         case (ALT_CLK_PERIPHERAL_PLL_C2):
    1109         case (ALT_CLK_PERIPHERAL_PLL_C3):
    1110         case (ALT_CLK_PERIPHERAL_PLL_C4):
    1111         case (ALT_CLK_PERIPHERAL_PLL_C5):
    1112         case (ALT_CLK_SDRAM_PLL_C0):
    1113         case (ALT_CLK_SDRAM_PLL_C1):
    1114         case (ALT_CLK_SDRAM_PLL_C2):
    1115         case (ALT_CLK_SDRAM_PLL_C5):
    1116             ret = ALT_E_BAD_ARG;
    1117             break;
    1118 
    1119         /* Clocks that originate at the Main PLL */
    1120         case (ALT_CLK_L4_MAIN):
    1121             ret = (ALT_CLKMGR_MAINPLL_EN_L4MAINCLK_GET(alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR)))
    1122                         ? ALT_E_TRUE : ALT_E_FALSE;
    1123             break;
    1124         case (ALT_CLK_L3_MP):
    1125             ret = (ALT_CLKMGR_MAINPLL_EN_L3MPCLK_GET(alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR)))
    1126                         ? ALT_E_TRUE : ALT_E_FALSE;
    1127             break;
    1128         case (ALT_CLK_L4_MP):
    1129             ret = (ALT_CLKMGR_MAINPLL_EN_L4MPCLK_GET(alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR)))
    1130                         ? ALT_E_TRUE : ALT_E_FALSE;
    1131             break;
    1132         case (ALT_CLK_L4_SP):
    1133             ret = (ALT_CLKMGR_MAINPLL_EN_L4SPCLK_GET(alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR)))
    1134                         ? ALT_E_TRUE : ALT_E_FALSE;
    1135             break;
    1136         case (ALT_CLK_DBG_AT):
    1137             ret = (ALT_CLKMGR_MAINPLL_EN_DBGATCLK_GET(alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR)))
    1138                         ? ALT_E_TRUE : ALT_E_FALSE;
    1139             break;
    1140         case (ALT_CLK_DBG):
    1141             ret = (ALT_CLKMGR_MAINPLL_EN_DBGCLK_GET(alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR)))
    1142                         ? ALT_E_TRUE : ALT_E_FALSE;
    1143             break;
    1144         case (ALT_CLK_DBG_TRACE):
    1145             ret = (ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK_GET(alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR)))
    1146                         ? ALT_E_TRUE : ALT_E_FALSE;
    1147             break;
    1148         case (ALT_CLK_DBG_TIMER):
    1149             ret = (ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK_GET(alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR)))
    1150                         ? ALT_E_TRUE : ALT_E_FALSE;
    1151             break;
    1152         case (ALT_CLK_CFG):
    1153             ret = (ALT_CLKMGR_MAINPLL_EN_CFGCLK_GET(alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR)))
    1154                         ? ALT_E_TRUE : ALT_E_FALSE;
    1155             break;
    1156         case (ALT_CLK_H2F_USER0):
    1157             ret = (ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK_GET(alt_read_word(ALT_CLKMGR_MAINPLL_EN_ADDR)))
    1158                         ? ALT_E_TRUE : ALT_E_FALSE;
    1159             break;
    1160 
    1161             /* Clocks that originate at the Peripheral PLL */
    1162         case (ALT_CLK_EMAC0):
    1163             ret = (ALT_CLKMGR_PERPLL_EN_EMAC0CLK_GET(alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR)))
    1164                         ? ALT_E_TRUE : ALT_E_FALSE;
    1165             break;
    1166         case (ALT_CLK_EMAC1):
    1167             ret = (ALT_CLKMGR_PERPLL_EN_EMAC1CLK_GET(alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR)))
    1168                         ? ALT_E_TRUE : ALT_E_FALSE;
    1169             break;
    1170         case (ALT_CLK_USB_MP):
    1171             ret = (ALT_CLKMGR_PERPLL_EN_USBCLK_GET(alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR)))
    1172                         ? ALT_E_TRUE : ALT_E_FALSE;
    1173             break;
    1174         case (ALT_CLK_SPI_M):
    1175             ret = (ALT_CLKMGR_PERPLL_EN_SPIMCLK_GET(alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR)))
    1176                         ? ALT_E_TRUE : ALT_E_FALSE;
    1177             break;
    1178         case (ALT_CLK_CAN0):
    1179             ret = (ALT_CLKMGR_PERPLL_EN_CAN0CLK_GET(alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR)))
    1180                         ? ALT_E_TRUE : ALT_E_FALSE;
    1181             break;
    1182         case (ALT_CLK_CAN1):
    1183             ret = (ALT_CLKMGR_PERPLL_EN_CAN1CLK_GET(alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR)))
    1184                         ? ALT_E_TRUE : ALT_E_FALSE;
    1185             break;
    1186         case (ALT_CLK_GPIO_DB):
    1187             ret = (ALT_CLKMGR_PERPLL_EN_GPIOCLK_GET(alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR)))
    1188                         ? ALT_E_TRUE : ALT_E_FALSE;
    1189             break;
    1190         case (ALT_CLK_H2F_USER1):
    1191             ret = (ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK_GET(alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR)))
    1192                         ? ALT_E_TRUE : ALT_E_FALSE;
    1193             break;
    1194 
    1195             /* Clocks that may originate at the Main PLL, the Peripheral PLL, or the FPGA */
    1196         case (ALT_CLK_SDMMC):
    1197             ret = (ALT_CLKMGR_PERPLL_EN_SDMMCCLK_GET(alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR)))
    1198                         ? ALT_E_TRUE : ALT_E_FALSE;
    1199             break;
    1200         case (ALT_CLK_NAND_X):
    1201             ret = (ALT_CLKMGR_PERPLL_EN_NANDXCLK_GET(alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR)))
    1202                         ? ALT_E_TRUE : ALT_E_FALSE;
    1203             break;
    1204         case (ALT_CLK_NAND):
    1205             ret = (ALT_CLKMGR_PERPLL_EN_NANDCLK_GET(alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR)))
    1206                         ? ALT_E_TRUE : ALT_E_FALSE;
    1207             break;
    1208         case (ALT_CLK_QSPI):
    1209             ret = (ALT_CLKMGR_PERPLL_EN_QSPICLK_GET(alt_read_word(ALT_CLKMGR_PERPLL_EN_ADDR)))
    1210                         ? ALT_E_TRUE : ALT_E_FALSE;
    1211             break;
    1212 
    1213         /* Clocks that originate at the SDRAM PLL */
    1214         case (ALT_CLK_DDR_DQS):
    1215             ret = (ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK_GET(alt_read_word(ALT_CLKMGR_SDRPLL_EN_ADDR)))
    1216                     ? ALT_E_TRUE : ALT_E_FALSE;
    1217             break;
    1218         case (ALT_CLK_DDR_2X_DQS):
    1219             ret = (ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK_GET(alt_read_word(ALT_CLKMGR_SDRPLL_EN_ADDR)))
    1220                     ? ALT_E_TRUE : ALT_E_FALSE;
    1221             break;
    1222         case (ALT_CLK_DDR_DQ):
    1223             ret = (ALT_CLKMGR_SDRPLL_EN_DDRDQCLK_GET(alt_read_word(ALT_CLKMGR_SDRPLL_EN_ADDR)))
    1224                     ? ALT_E_TRUE : ALT_E_FALSE;
    1225             break;
    1226         case (ALT_CLK_H2F_USER2):
    1227             ret = (ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK_GET(alt_read_word(ALT_CLKMGR_SDRPLL_EN_ADDR)))
    1228                     ? ALT_E_TRUE : ALT_E_FALSE;
    1229             break;
    1230 
    1231         default:
    1232             break;
    1233 
    1234     }
     1785    ALT_STATUS_CODE        ret = ALT_E_ERROR;                  // return value
     1786    uint32_t               temp;                               // temp variable
     1787 
     1788    if (pll_cfg == NULL)
     1789    {
     1790                ret = ALT_E_BAD_ARG;
     1791                return ret;
     1792    }
     1793
     1794    if (pll == ALT_CLK_MAIN_PLL)
     1795    {
     1796        temp = alt_read_word(ALT_CLKMGR_MAINPLL_VCO_ADDR);
     1797        pll_cfg->ref_clk = ALT_CLK_IN_PIN_OSC1;
     1798        pll_cfg->mult = ALT_CLKMGR_MAINPLL_VCO_NUMER_GET(temp);
     1799        pll_cfg->div = ALT_CLKMGR_MAINPLL_VCO_DENOM_GET(temp);
     1800
     1801        // Get the C0-C5 divider values:
     1802        pll_cfg->cntrs[0] = ALT_CLKMGR_MAINPLL_MPUCLK_CNT_GET(alt_read_word(ALT_CLKMGR_ALTERA_MPUCLK_ADDR));
     1803        // C0 - mpu_clk
     1804
     1805        pll_cfg->cntrs[1] = ALT_CLKMGR_MAINPLL_MAINCLK_CNT_GET(alt_read_word(ALT_CLKMGR_ALTERA_MAINCLK_ADDR));
     1806        // C1 - main_clk
     1807
     1808        pll_cfg->cntrs[2] = ALT_CLKMGR_MAINPLL_DBGATCLK_CNT_GET(alt_read_word(ALT_CLKMGR_MAINPLL_DBGATCLK_ADDR));
     1809        // C2 - dbg_base_clk
     1810
     1811        pll_cfg->cntrs[3] = ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT_GET(alt_read_word(ALT_CLKMGR_MAINPLL_MAINQSPICLK_ADDR));
     1812        // C3 - main_qspi_clk
     1813
     1814        pll_cfg->cntrs[4] = ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT_GET(alt_read_word(ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_ADDR));
     1815        // C4 - main_nand_sdmmc_clk
     1816
     1817        pll_cfg->cntrs[5] = ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT_GET(alt_read_word(ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_ADDR));
     1818        // C5 - cfg_s2f_user0_clk aka cfg_h2f_user0_clk
     1819
     1820        // The Main PLL C0-C5 outputs have no phase shift capabilities :
     1821        pll_cfg->pshift[0] = pll_cfg->pshift[1] = pll_cfg->pshift[2] =
     1822            pll_cfg->pshift[3] = pll_cfg->pshift[4] = pll_cfg->pshift[5] = 0;
     1823        ret = ALT_E_SUCCESS;
     1824    }
     1825    else if (pll == ALT_CLK_PERIPHERAL_PLL)
     1826    {
     1827        temp = ALT_CLKMGR_PERPLL_VCO_PSRC_GET(alt_read_word(ALT_CLKMGR_PERPLL_VCO_ADDR));
     1828        if (temp <= 2)
     1829        {
     1830            if (temp == ALT_CLKMGR_PERPLL_VCO_PSRC_E_EOSC1)
     1831            {
     1832                pll_cfg->ref_clk = ALT_CLK_IN_PIN_OSC1;
     1833            }
     1834            else if (temp == ALT_CLKMGR_PERPLL_VCO_PSRC_E_EOSC2)
     1835            {
     1836                pll_cfg->ref_clk = ALT_CLK_IN_PIN_OSC2;
     1837            }
     1838            else if (temp == ALT_CLKMGR_PERPLL_VCO_PSRC_E_F2S_PERIPH_REF)
     1839            {
     1840                pll_cfg->ref_clk = ALT_CLK_F2H_PERIPH_REF;
     1841            }
     1842
     1843            temp = alt_read_word(ALT_CLKMGR_PERPLL_VCO_ADDR);
     1844            pll_cfg->mult = ALT_CLKMGR_PERPLL_VCO_NUMER_GET(temp);
     1845            pll_cfg->div = ALT_CLKMGR_PERPLL_VCO_DENOM_GET(temp);
     1846
     1847            // Get the C0-C5 divider values:
     1848            pll_cfg->cntrs[0] = ALT_CLKMGR_PERPLL_EMAC0CLK_CNT_GET(alt_read_word(ALT_CLKMGR_PERPLL_EMAC0CLK_ADDR));
     1849            // C0 - emac0_clk
     1850
     1851            pll_cfg->cntrs[1] = ALT_CLKMGR_PERPLL_EMAC1CLK_CNT_GET(alt_read_word(ALT_CLKMGR_PERPLL_EMAC1CLK_ADDR));
     1852            // C1 - emac1_clk
     1853
     1854            pll_cfg->cntrs[2] = ALT_CLKMGR_PERPLL_PERQSPICLK_CNT_GET(alt_read_word(ALT_CLKMGR_PERPLL_PERQSPICLK_ADDR));
     1855            // C2 - periph_qspi_clk
     1856
     1857            pll_cfg->cntrs[3] = ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT_GET(alt_read_word(ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_ADDR));
     1858            // C3 - periph_nand_sdmmc_clk
     1859
     1860            pll_cfg->cntrs[4] = ALT_CLKMGR_PERPLL_PERBASECLK_CNT_GET(alt_read_word(ALT_CLKMGR_PERPLL_PERBASECLK_ADDR));
     1861            // C4 - periph_base_clk
     1862
     1863            pll_cfg->cntrs[5] = ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT_GET(alt_read_word(ALT_CLKMGR_PERPLL_S2FUSER1CLK_ADDR));
     1864            // C5 - s2f_user1_clk
     1865
     1866            // The Peripheral PLL C0-C5 outputs have no phase shift capabilities :
     1867            pll_cfg->pshift[0] = pll_cfg->pshift[1] = pll_cfg->pshift[2] =
     1868                pll_cfg->pshift[3] = pll_cfg->pshift[4] = pll_cfg->pshift[5] = 0;
     1869            ret = ALT_E_SUCCESS;
     1870        }
     1871    }
     1872    else if (pll == ALT_CLK_SDRAM_PLL)
     1873    {
     1874        temp = ALT_CLKMGR_SDRPLL_VCO_SSRC_GET(alt_read_word(ALT_CLKMGR_SDRPLL_VCO_ADDR));
     1875        if (temp <= 2)
     1876        {
     1877            if (temp == ALT_CLKMGR_SDRPLL_VCO_SSRC_E_EOSC1)
     1878            {
     1879                pll_cfg->ref_clk = ALT_CLK_IN_PIN_OSC1;
     1880            }
     1881            else if (temp == ALT_CLKMGR_SDRPLL_VCO_SSRC_E_EOSC2)
     1882            {
     1883                pll_cfg->ref_clk = ALT_CLK_IN_PIN_OSC2;
     1884            }
     1885            else if (temp == ALT_CLKMGR_SDRPLL_VCO_SSRC_E_F2S_SDRAM_REF)
     1886            {
     1887                pll_cfg->ref_clk = ALT_CLK_F2H_SDRAM_REF;
     1888            }
     1889
     1890            pll_cfg->mult = ALT_CLKMGR_SDRPLL_VCO_NUMER_GET(alt_read_word(ALT_CLKMGR_SDRPLL_VCO_ADDR));
     1891            pll_cfg->div = ALT_CLKMGR_SDRPLL_VCO_DENOM_GET(alt_read_word(ALT_CLKMGR_SDRPLL_VCO_ADDR));
     1892
     1893            // Get the C0-C5 divider values:
     1894            pll_cfg->cntrs[0]  = ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT_GET(alt_read_word(ALT_CLKMGR_SDRPLL_DDRDQSCLK_ADDR));
     1895            pll_cfg->pshift[0] = ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE_GET(alt_read_word(ALT_CLKMGR_SDRPLL_DDRDQSCLK_ADDR));
     1896            // C0  - ddr_dqs_clk
     1897
     1898            pll_cfg->cntrs[1]  = ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT_GET(alt_read_word(ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_ADDR));
     1899            pll_cfg->pshift[1] = ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE_GET(alt_read_word(ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_ADDR));
     1900            // C1  - ddr_2x_dqs_clk
     1901
     1902            pll_cfg->cntrs[2]  = ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT_GET(alt_read_word(ALT_CLKMGR_SDRPLL_DDRDQCLK_ADDR));
     1903            pll_cfg->pshift[2] = ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE_GET(alt_read_word(ALT_CLKMGR_SDRPLL_DDRDQCLK_ADDR));
     1904            // C2  - ddr_dq_clk
     1905
     1906            pll_cfg->cntrs[3]  = pll_cfg->cntrs[4] = pll_cfg->pshift[3] = pll_cfg->pshift[4] = 0;
     1907            // C3  & C4 outputs don't exist on the SDRAM PLL
     1908
     1909            pll_cfg->cntrs[5]  = ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT_GET(alt_read_word(ALT_CLKMGR_SDRPLL_S2FUSER2CLK_ADDR));
     1910            pll_cfg->pshift[5] = ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE_GET(alt_read_word(ALT_CLKMGR_SDRPLL_S2FUSER2CLK_ADDR));
     1911            // C5  - s2f_user2_clk or h2f_user2_clk
     1912
     1913            ret = ALT_E_SUCCESS;
     1914        }
     1915    }
     1916
    12351917    return ret;
    12361918}
    12371919
    12381920
    1239 /****************************************************************************************/
    1240 /* alt_clk_source_get() gets the input reference clock source selection value for the   */
    1241 /* specified clock or PLL.                                                              */
    1242 /****************************************************************************************/
    1243 
    1244 ALT_CLK_t alt_clk_source_get(ALT_CLK_t clk)
     1921//
     1922// alt_clk_pll_cfg_set() sets the PLL configuration using the configuration parameters
     1923// specified in pll_cfg.
     1924//
     1925ALT_STATUS_CODE alt_clk_pll_cfg_set(ALT_CLK_t pll, const ALT_CLK_PLL_CFG_t * pll_cfg)
    12451926{
    1246     ALT_CLK_t       ret = ALT_CLK_UNKNOWN;
     1927    if (pll_cfg == NULL)
     1928    {
     1929                return ALT_E_BAD_ARG;
     1930    }
     1931
     1932    if (alt_clk_pll_is_bypassed(pll) != ALT_E_TRUE)         // safe to write the PLL registers?
     1933    {
     1934        return ALT_E_ERROR;
     1935    }
     1936
     1937    ALT_STATUS_CODE ret = ALT_E_ERROR;
    12471938    uint32_t        temp;
    12481939
    1249     switch (clk)
    1250     {
    1251             /* Potential external clock sources */
    1252         case ALT_CLK_IN_PIN_OSC1:
    1253         case ALT_CLK_IN_PIN_OSC2:
    1254         case ALT_CLK_F2H_PERIPH_REF:
    1255         case ALT_CLK_F2H_SDRAM_REF:
    1256         case ALT_CLK_IN_PIN_JTAG:
    1257         case ALT_CLK_IN_PIN_ULPI0:
    1258         case ALT_CLK_IN_PIN_ULPI1:
    1259         case ALT_CLK_IN_PIN_EMAC0_RX:
    1260         case ALT_CLK_IN_PIN_EMAC1_RX:
    1261             ret = clk;
    1262             break;                          // these clock entities are their own source
    1263 
    1264             /* Phase-Locked Loops */
    1265         case ALT_CLK_MAIN_PLL:
    1266         case ALT_CLK_OSC1:
    1267             ret = ALT_CLK_IN_PIN_OSC1;
    1268             break;
    1269         case ALT_CLK_PERIPHERAL_PLL:
    1270             ret = alt_clk_pll_source_get(ALT_CLK_PERIPHERAL_PLL);
    1271             break;
    1272         case ALT_CLK_SDRAM_PLL:
    1273             ret = alt_clk_pll_source_get(ALT_CLK_SDRAM_PLL);
    1274             break;
    1275 
    1276             /* Main Clock Group */
    1277         case ALT_CLK_MAIN_PLL_C0:
    1278         case ALT_CLK_MAIN_PLL_C1:
    1279         case ALT_CLK_MAIN_PLL_C2:
    1280         case ALT_CLK_MAIN_PLL_C3:
    1281         case ALT_CLK_MAIN_PLL_C4:
    1282         case ALT_CLK_MAIN_PLL_C5:
    1283             // check bypass, return either osc1 or PLL ID
    1284             ret = (alt_clk_pll_is_bypassed(ALT_CLK_MAIN_PLL) == ALT_E_TRUE) ?
    1285                     ALT_CLK_IN_PIN_OSC1 : ALT_CLK_MAIN_PLL;
    1286             break;
    1287 
    1288         case ALT_CLK_MPU_PERIPH:
    1289         case ALT_CLK_MPU_L2_RAM:
    1290         case ALT_CLK_MPU:
    1291             ret = (alt_clk_pll_is_bypassed(ALT_CLK_MAIN_PLL) == ALT_E_TRUE) ?
    1292                     ALT_CLK_IN_PIN_OSC1 : ALT_CLK_MAIN_PLL_C0;
    1293             break;
    1294 
    1295         case ALT_CLK_L4_MAIN:
    1296         case ALT_CLK_L3_MAIN:
    1297         case ALT_CLK_L3_MP:
    1298         case ALT_CLK_L3_SP:
    1299             ret = (alt_clk_pll_is_bypassed(ALT_CLK_MAIN_PLL) == ALT_E_TRUE) ?
    1300                     ALT_CLK_IN_PIN_OSC1 : ALT_CLK_MAIN_PLL_C1;
    1301             break;
    1302 
    1303         case ALT_CLK_L4_MP:
    1304             // read the state of the L4_mp source bit
    1305             if ((ALT_CLKMGR_MAINPLL_L4SRC_L4MP_GET(alt_read_word(ALT_CLKMGR_MAINPLL_L4SRC_ADDR)))
    1306                     == ALT_CLKMGR_MAINPLL_L4SRC_L4MP_E_MAINPLL)
    1307             {
    1308                 ret = (alt_clk_pll_is_bypassed(ALT_CLK_MAIN_PLL) == ALT_E_TRUE) ?
    1309                         ALT_CLK_IN_PIN_OSC1 : ALT_CLK_MAIN_PLL_C1;
    1310             }
    1311             else
    1312             {
    1313                 // if the clock comes from periph_base_clk
    1314                  ret = (alt_clk_pll_is_bypassed(ALT_CLK_PERIPHERAL_PLL) == ALT_E_TRUE) ?
    1315                         alt_clk_pll_source_get(ALT_CLK_PERIPHERAL_PLL) : ALT_CLK_PERIPHERAL_PLL_C4;
    1316             }
    1317             break;
    1318 
    1319         case ALT_CLK_L4_SP:
    1320             // read the state of the source bit
    1321             if ((ALT_CLKMGR_MAINPLL_L4SRC_L4SP_GET(alt_read_word(ALT_CLKMGR_MAINPLL_L4SRC_ADDR)))
    1322                     == ALT_CLKMGR_MAINPLL_L4SRC_L4SP_E_MAINPLL)
    1323             {
    1324                 ret = (alt_clk_pll_is_bypassed(ALT_CLK_MAIN_PLL) == ALT_E_TRUE) ?
    1325                         ALT_CLK_IN_PIN_OSC1 : ALT_CLK_MAIN_PLL_C1;
    1326             }
    1327             else
    1328             {
    1329                 // if the clock comes from periph_base_clk
    1330                  ret = (alt_clk_pll_is_bypassed(ALT_CLK_PERIPHERAL_PLL) == ALT_E_TRUE) ?
    1331                         alt_clk_pll_source_get(ALT_CLK_PERIPHERAL_PLL) : ALT_CLK_PERIPHERAL_PLL_C4;
    1332             }
    1333             break;
    1334 
    1335         case ALT_CLK_DBG_BASE:
    1336         case ALT_CLK_DBG_AT:
    1337         case ALT_CLK_DBG_TRACE:
    1338         case ALT_CLK_DBG_TIMER:
    1339         case ALT_CLK_DBG:
    1340             ret = (alt_clk_pll_is_bypassed(ALT_CLK_MAIN_PLL) == ALT_E_TRUE) ?
    1341                     ALT_CLK_OSC1 : ALT_CLK_MAIN_PLL_C2;
    1342             break;
    1343         case ALT_CLK_MAIN_QSPI:
    1344             ret = (alt_clk_pll_is_bypassed(ALT_CLK_MAIN_PLL) == ALT_E_TRUE) ?
    1345                     ALT_CLK_OSC1 : ALT_CLK_MAIN_PLL_C3;
    1346             break;
    1347         case ALT_CLK_MAIN_NAND_SDMMC:
    1348             ret = (alt_clk_pll_is_bypassed(ALT_CLK_MAIN_PLL) == ALT_E_TRUE) ?
    1349                     ALT_CLK_OSC1 : ALT_CLK_MAIN_PLL_C4;
    1350             break;
    1351         case ALT_CLK_CFG:
    1352         case ALT_CLK_H2F_USER0:
    1353             ret = (alt_clk_pll_is_bypassed(ALT_CLK_MAIN_PLL) == ALT_E_TRUE) ?
    1354                     ALT_CLK_OSC1 : ALT_CLK_MAIN_PLL_C5;
    1355             break;
    1356 
    1357         /* Peripherals Clock Group */
    1358         case ALT_CLK_PERIPHERAL_PLL_C0:
    1359         case ALT_CLK_PERIPHERAL_PLL_C1:
    1360         case ALT_CLK_PERIPHERAL_PLL_C2:
    1361         case ALT_CLK_PERIPHERAL_PLL_C3:
    1362         case ALT_CLK_PERIPHERAL_PLL_C4:
    1363         case ALT_CLK_PERIPHERAL_PLL_C5:
    1364             // if the clock comes from periph_base_clk
    1365              ret = (alt_clk_pll_is_bypassed(ALT_CLK_PERIPHERAL_PLL) == ALT_E_TRUE) ?
    1366                     alt_clk_pll_source_get(ALT_CLK_PERIPHERAL_PLL) : ALT_CLK_PERIPHERAL_PLL;
    1367             break;
    1368 
    1369         case ALT_CLK_EMAC0:
    1370             ret = (alt_clk_pll_is_bypassed(ALT_CLK_PERIPHERAL_PLL) == ALT_E_TRUE) ?
    1371                    alt_clk_pll_source_get(ALT_CLK_PERIPHERAL_PLL) :  ALT_CLK_PERIPHERAL_PLL_C0;
    1372             break;
    1373 
    1374         case ALT_CLK_EMAC1:
    1375             ret = (alt_clk_pll_is_bypassed(ALT_CLK_PERIPHERAL_PLL) == ALT_E_TRUE) ?
    1376                    alt_clk_pll_source_get(ALT_CLK_PERIPHERAL_PLL) :  ALT_CLK_PERIPHERAL_PLL_C1;
    1377             break;
    1378 
    1379         case ALT_CLK_USB_MP:
    1380         case ALT_CLK_SPI_M:
    1381         case ALT_CLK_CAN0:
    1382         case ALT_CLK_CAN1:
    1383         case ALT_CLK_GPIO_DB:
    1384             ret = (alt_clk_pll_is_bypassed(ALT_CLK_PERIPHERAL_PLL) == ALT_E_TRUE) ?
    1385                    alt_clk_pll_source_get(ALT_CLK_PERIPHERAL_PLL) :  ALT_CLK_PERIPHERAL_PLL_C4;
    1386             break;
    1387 
    1388         case ALT_CLK_H2F_USER1:
    1389             ret = (alt_clk_pll_is_bypassed(ALT_CLK_PERIPHERAL_PLL) == ALT_E_TRUE) ?
    1390                    alt_clk_pll_source_get(ALT_CLK_PERIPHERAL_PLL) :  ALT_CLK_PERIPHERAL_PLL_C5;
    1391             break;
    1392 
    1393         case ALT_CLK_SDMMC:
    1394             temp = ALT_CLKMGR_PERPLL_SRC_SDMMC_GET(alt_read_word(ALT_CLKMGR_PERPLL_SRC_ADDR));
    1395             if (temp == ALT_CLKMGR_PERPLL_SRC_SDMMC_E_F2S_PERIPH_REF_CLK)
    1396             {
    1397                 ret = ALT_CLK_F2H_PERIPH_REF;
    1398             }
    1399             else if (temp == ALT_CLKMGR_PERPLL_SRC_SDMMC_E_MAIN_NAND_CLK)
    1400             {
    1401                 ret = (alt_clk_pll_is_bypassed(ALT_CLK_MAIN_PLL) == ALT_E_TRUE) ?
    1402                         ALT_CLK_IN_PIN_OSC1 : ALT_CLK_MAIN_PLL_C4;
    1403             }
    1404             else if (temp == ALT_CLKMGR_PERPLL_SRC_SDMMC_E_PERIPH_NAND_CLK)
    1405             {
    1406                 ret = (alt_clk_pll_is_bypassed(ALT_CLK_PERIPHERAL_PLL) == ALT_E_TRUE) ?
    1407                        alt_clk_pll_source_get(ALT_CLK_PERIPHERAL_PLL) :  ALT_CLK_PERIPHERAL_PLL_C3;
    1408             }
    1409             break;
    1410 
    1411         case ALT_CLK_NAND_X:
    1412         case ALT_CLK_NAND:
    1413             temp = ALT_CLKMGR_PERPLL_SRC_NAND_GET(alt_read_word(ALT_CLKMGR_PERPLL_SRC_ADDR));
    1414             if (temp == ALT_CLKMGR_PERPLL_SRC_NAND_E_F2S_PERIPH_REF_CLK)
    1415             {
    1416                 ret = ALT_CLK_F2H_PERIPH_REF;
    1417             }
    1418             else if (temp == ALT_CLKMGR_PERPLL_SRC_NAND_E_MAIN_NAND_CLK)
    1419             {
    1420                 ret = (alt_clk_pll_is_bypassed(ALT_CLK_MAIN_PLL) == ALT_E_TRUE) ?
    1421                         ALT_CLK_IN_PIN_OSC1 : ALT_CLK_MAIN_PLL_C4;
    1422             }
    1423             else if (temp == ALT_CLKMGR_PERPLL_SRC_NAND_E_PERIPH_NAND_CLK)
    1424             {
    1425                 ret = (alt_clk_pll_is_bypassed(ALT_CLK_PERIPHERAL_PLL) == ALT_E_TRUE) ?
    1426                        alt_clk_pll_source_get(ALT_CLK_PERIPHERAL_PLL) :  ALT_CLK_PERIPHERAL_PLL_C3;
    1427             }
    1428             break;
    1429 
    1430         case ALT_CLK_QSPI:
    1431             temp = ALT_CLKMGR_PERPLL_SRC_QSPI_GET(alt_read_word(ALT_CLKMGR_PERPLL_SRC_ADDR));
    1432             if (temp == ALT_CLKMGR_PERPLL_SRC_QSPI_E_F2S_PERIPH_REF_CLK)
    1433             {
    1434                 ret = ALT_CLK_F2H_PERIPH_REF;
    1435             }
    1436             else if (temp == ALT_CLKMGR_PERPLL_SRC_QSPI_E_MAIN_QSPI_CLK)
    1437             {
    1438                 ret = (alt_clk_pll_is_bypassed(ALT_CLK_MAIN_PLL) == ALT_E_TRUE) ?
    1439                         ALT_CLK_IN_PIN_OSC1 : ALT_CLK_MAIN_PLL_C3;
    1440             }
    1441             else if (temp == ALT_CLKMGR_PERPLL_SRC_QSPI_E_PERIPH_QSPI_CLK)
    1442             {
    1443                 ret = (alt_clk_pll_is_bypassed(ALT_CLK_PERIPHERAL_PLL) == ALT_E_TRUE) ?
    1444                    alt_clk_pll_source_get(ALT_CLK_PERIPHERAL_PLL) :  ALT_CLK_PERIPHERAL_PLL_C2;
    1445             }
    1446             break;
    1447 
    1448         /* SDRAM Clock Group */
    1449         case ALT_CLK_SDRAM_PLL_C0:
    1450         case ALT_CLK_SDRAM_PLL_C1:
    1451         case ALT_CLK_SDRAM_PLL_C2:
    1452         case ALT_CLK_SDRAM_PLL_C3:
    1453         case ALT_CLK_SDRAM_PLL_C4:
    1454         case ALT_CLK_SDRAM_PLL_C5:
    1455             ret = (alt_clk_pll_is_bypassed(ALT_CLK_SDRAM_PLL) == ALT_E_TRUE) ?
    1456                    alt_clk_pll_source_get(ALT_CLK_SDRAM_PLL) :  ALT_CLK_SDRAM_PLL;
    1457             break;
    1458         case ALT_CLK_DDR_DQS:
    1459             ret = (alt_clk_pll_is_bypassed(ALT_CLK_SDRAM_PLL) == ALT_E_TRUE) ?
    1460                    alt_clk_pll_source_get(ALT_CLK_SDRAM_PLL) :  ALT_CLK_SDRAM_PLL_C0;
    1461             break;
    1462         case ALT_CLK_DDR_2X_DQS:
    1463             ret = (alt_clk_pll_is_bypassed(ALT_CLK_SDRAM_PLL) == ALT_E_TRUE) ?
    1464                    alt_clk_pll_source_get(ALT_CLK_SDRAM_PLL) :  ALT_CLK_SDRAM_PLL_C1;
    1465             break;
    1466         case ALT_CLK_DDR_DQ:
    1467             ret = (alt_clk_pll_is_bypassed(ALT_CLK_SDRAM_PLL) == ALT_E_TRUE) ?
    1468                    alt_clk_pll_source_get(ALT_CLK_SDRAM_PLL) :  ALT_CLK_SDRAM_PLL_C2;
    1469             break;
    1470         case ALT_CLK_H2F_USER2:
    1471             ret = (alt_clk_pll_is_bypassed(ALT_CLK_SDRAM_PLL) == ALT_E_TRUE) ?
    1472                    alt_clk_pll_source_get(ALT_CLK_SDRAM_PLL) :  ALT_CLK_SDRAM_PLL_C5;
    1473             break;
    1474 
    1475         /* Clock Output Pins */
    1476         case ALT_CLK_OUT_PIN_EMAC0_TX:
    1477         case ALT_CLK_OUT_PIN_EMAC1_TX:
    1478         case ALT_CLK_OUT_PIN_SDMMC:
    1479         case ALT_CLK_OUT_PIN_I2C0_SCL:
    1480         case ALT_CLK_OUT_PIN_I2C1_SCL:
    1481         case ALT_CLK_OUT_PIN_I2C2_SCL:
    1482         case ALT_CLK_OUT_PIN_I2C3_SCL:
    1483         case ALT_CLK_OUT_PIN_SPIM0:
    1484         case ALT_CLK_OUT_PIN_SPIM1:
    1485         case ALT_CLK_OUT_PIN_QSPI:
    1486             ret = ALT_CLK_UNKNOWN;
    1487             break;
    1488 
    1489         default:
    1490             break;
    1491     }       /* end big switch/case construct */
     1940    if (pll == ALT_CLK_MAIN_PLL)
     1941    {
     1942        temp  = (ALT_CLKMGR_MAINPLL_VCO_NUMER_CLR_MSK & ALT_CLKMGR_MAINPLL_VCO_DENOM_CLR_MSK)
     1943            & alt_read_word(ALT_CLKMGR_MAINPLL_VCO_ADDR);
     1944        temp |= ALT_CLKMGR_MAINPLL_VCO_NUMER_SET(pll_cfg->mult) |
     1945            ALT_CLKMGR_MAINPLL_VCO_DENOM_SET(pll_cfg->div);
     1946
     1947        alt_write_word(ALT_CLKMGR_MAINPLL_VCO_ADDR, temp);
     1948        alt_write_word(ALT_CLKMGR_ALTERA_MPUCLK_ADDR,           pll_cfg->cntrs[0]);
     1949        alt_write_word(ALT_CLKMGR_ALTERA_MAINCLK_ADDR,          pll_cfg->cntrs[1]);
     1950        alt_write_word(ALT_CLKMGR_MAINPLL_DBGATCLK_ADDR,         pll_cfg->cntrs[2]);
     1951        alt_write_word(ALT_CLKMGR_MAINPLL_MAINQSPICLK_ADDR,      pll_cfg->cntrs[3]);
     1952        alt_write_word(ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_ADDR, pll_cfg->cntrs[4]);
     1953        alt_write_word(ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_ADDR,   pll_cfg->cntrs[5]);
     1954        ret = ALT_E_SUCCESS;
     1955    }
     1956    else if (pll == ALT_CLK_PERIPHERAL_PLL)
     1957    {
     1958        temp =  ALT_CLKMGR_PERPLL_VCO_NUMER_CLR_MSK & ALT_CLKMGR_PERPLL_VCO_DENOM_CLR_MSK
     1959            & ALT_CLKMGR_PERPLL_VCO_PSRC_CLR_MSK;
     1960        temp &= alt_read_word(ALT_CLKMGR_PERPLL_VCO_ADDR);
     1961        temp |= ALT_CLKMGR_PERPLL_VCO_NUMER_SET(pll_cfg->mult)
     1962            | ALT_CLKMGR_PERPLL_VCO_DENOM_SET(pll_cfg->div);
     1963
     1964        if ((pll_cfg->ref_clk == ALT_CLK_IN_PIN_OSC1) || (pll_cfg->ref_clk == ALT_CLK_OSC1))
     1965        {
     1966            temp |= ALT_CLKMGR_PERPLL_VCO_PSRC_SET(ALT_CLKMGR_PERPLL_VCO_PSRC_E_EOSC1);
     1967        }
     1968        else if (pll_cfg->ref_clk == ALT_CLK_IN_PIN_OSC2)
     1969        {
     1970            temp |= ALT_CLKMGR_PERPLL_VCO_PSRC_SET(ALT_CLKMGR_PERPLL_VCO_PSRC_E_EOSC2);
     1971        }
     1972        else if (pll_cfg->ref_clk == ALT_CLK_F2H_PERIPH_REF)
     1973        {
     1974            temp |= ALT_CLKMGR_PERPLL_VCO_PSRC_SET(ALT_CLKMGR_PERPLL_VCO_PSRC_E_F2S_PERIPH_REF);
     1975        }
     1976        else
     1977        {
     1978            return ret;
     1979        }
     1980
     1981        alt_write_word(ALT_CLKMGR_PERPLL_VCO_ADDR, temp);
     1982        alt_write_word(ALT_CLKMGR_PERPLL_EMAC0CLK_ADDR,        pll_cfg->cntrs[0]);
     1983        alt_write_word(ALT_CLKMGR_PERPLL_EMAC1CLK_ADDR,        pll_cfg->cntrs[1]);
     1984        alt_write_word(ALT_CLKMGR_PERPLL_PERQSPICLK_ADDR,      pll_cfg->cntrs[2]);
     1985        alt_write_word(ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_ADDR, pll_cfg->cntrs[3]);
     1986        alt_write_word(ALT_CLKMGR_PERPLL_PERBASECLK_ADDR,      pll_cfg->cntrs[4]);
     1987        alt_write_word(ALT_CLKMGR_PERPLL_S2FUSER1CLK_ADDR,     pll_cfg->cntrs[5]);
     1988        ret = ALT_E_SUCCESS;
     1989    }
     1990    else if (pll == ALT_CLK_SDRAM_PLL)
     1991    {
     1992        // write the SDRAM PLL VCO Counter -----------------------------
     1993        temp =  ALT_CLKMGR_SDRPLL_VCO_NUMER_CLR_MSK & ALT_CLKMGR_SDRPLL_VCO_DENOM_CLR_MSK
     1994            & ALT_CLKMGR_SDRPLL_VCO_SSRC_CLR_MSK;           // make a mask
     1995        temp &= alt_read_word(ALT_CLKMGR_SDRPLL_VCO_ADDR);
     1996        temp |= ALT_CLKMGR_SDRPLL_VCO_NUMER_SET(pll_cfg->mult)
     1997            | ALT_CLKMGR_SDRPLL_VCO_DENOM_SET(pll_cfg->div)
     1998            | ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL_SET_MSK;
     1999        // setting this bit aligns the output phase of the counters and prevents
     2000        // glitches and too-short clock periods when restarting.
     2001        // this bit is cleared at the end of this routine
     2002
     2003        if ((pll_cfg->ref_clk == ALT_CLK_IN_PIN_OSC1) || (pll_cfg->ref_clk == ALT_CLK_OSC1))
     2004        {
     2005            temp |= ALT_CLKMGR_SDRPLL_VCO_SSRC_SET(ALT_CLKMGR_SDRPLL_VCO_SSRC_E_EOSC1);
     2006        }
     2007        else if (pll_cfg->ref_clk == ALT_CLK_IN_PIN_OSC2)
     2008        {
     2009            temp |= ALT_CLKMGR_SDRPLL_VCO_SSRC_SET(ALT_CLKMGR_SDRPLL_VCO_SSRC_E_EOSC2);
     2010        }
     2011        else if (pll_cfg->ref_clk == ALT_CLK_F2H_PERIPH_REF)
     2012        {
     2013            temp |= ALT_CLKMGR_SDRPLL_VCO_SSRC_SET(ALT_CLKMGR_SDRPLL_VCO_SSRC_E_F2S_SDRAM_REF);
     2014        }
     2015        else
     2016        {
     2017            return ret;
     2018        }
     2019
     2020        alt_write_word(ALT_CLKMGR_SDRPLL_VCO_ADDR, temp);
     2021
     2022        // write the SDRAM PLL C0 Divide Counter -----------------------------
     2023        temp =  ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT_SET(pll_cfg->cntrs[0])
     2024            | ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE_SET(pll_cfg->pshift[0]);
     2025
     2026        alt_clk_pllcounter_write(ALT_CLKMGR_SDRPLL_VCO_ADDR, ALT_CLKMGR_STAT_ADDR,
     2027                                 ALT_CLKMGR_SDRPLL_DDRDQSCLK_ADDR, temp,
     2028                                 ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT_SET_MSK | ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE_SET_MSK,
     2029                                 ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT_LSB);
     2030
     2031        // write the SDRAM PLL C1 Divide Counter -----------------------------
     2032        if (ret == ALT_E_SUCCESS)
     2033        {
     2034            temp =  ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT_SET(pll_cfg->cntrs[1])
     2035                | ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE_SET(pll_cfg->pshift[1]);
     2036            alt_clk_pllcounter_write(ALT_CLKMGR_SDRPLL_VCO_ADDR, ALT_CLKMGR_STAT_ADDR,
     2037                                     ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_ADDR, temp,
     2038                                     ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT_SET_MSK | ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE_SET_MSK,
     2039                                     ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT_LSB);
     2040        }
     2041
     2042        // write the SDRAM PLL C2 Divide Counter -----------------------------
     2043        if (ret == ALT_E_SUCCESS)
     2044        {
     2045            temp =  ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT_SET(pll_cfg->cntrs[2])
     2046                | ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE_SET(pll_cfg->pshift[2]);
     2047            alt_clk_pllcounter_write(ALT_CLKMGR_SDRPLL_VCO_ADDR, ALT_CLKMGR_STAT_ADDR,
     2048                                     ALT_CLKMGR_SDRPLL_DDRDQCLK_ADDR, temp,
     2049                                     ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT_SET_MSK | ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE_SET_MSK,
     2050                                     ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT_LSB);
     2051        }
     2052
     2053        // write the SDRAM PLL C5 Divide Counter -----------------------------
     2054        if (ret == ALT_E_SUCCESS)
     2055        {
     2056            temp =  ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT_SET(pll_cfg->cntrs[2])
     2057                | ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE_SET(pll_cfg->pshift[2]);
     2058            alt_clk_pllcounter_write(ALT_CLKMGR_SDRPLL_VCO_ADDR, ALT_CLKMGR_STAT_ADDR,
     2059                                     ALT_CLKMGR_SDRPLL_S2FUSER2CLK_ADDR, temp,
     2060                                     ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT_SET_MSK | ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE_SET_MSK,
     2061                                     ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT_LSB);
     2062        }
     2063
     2064        if (ret == ALT_E_SUCCESS)
     2065        {
     2066            alt_clrbits_word(ALT_CLKMGR_SDRPLL_VCO_ADDR, ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL_SET_MSK);
     2067            // allow the phase multiplexer and output counter to leave reset
     2068        }
     2069    }
     2070
    14922071    return ret;
    14932072}
    14942073
    14952074
    1496 /****************************************************************************************/
    1497 /* alt_clk_source_set() sets the specified clock's input reference clock source         */
    1498 /* selection to the specified input. It does not handle gating the specified clock      */
    1499 /* off and back on, those are covered in other functions in this API, but it does       */
    1500 /* verify that the clock is off before changing the divider or PLL. Note that the PLL   */
    1501 /* must have regained phase-lock before being the bypass is disabled.                   */
    1502 /****************************************************************************************/
    1503 
    1504 ALT_STATUS_CODE alt_clk_source_set(ALT_CLK_t clk,  ALT_CLK_t ref_clk)
     2075//
     2076// alt_clk_pll_vco_cfg_get() returns the current PLL VCO frequency configuration.
     2077//
     2078ALT_STATUS_CODE alt_clk_pll_vco_cfg_get(ALT_CLK_t pll, uint32_t * mult, uint32_t * div)
    15052079{
    1506     ALT_STATUS_CODE     ret = ALT_E_BAD_ARG;
    1507     uint32_t            temp;
    1508 
    1509     if (ALT_CLK_MAIN_PLL == clk)
    1510     {
    1511         if ((ref_clk == ALT_CLK_IN_PIN_OSC1)  || (ref_clk == ALT_CLK_OSC1))   { ret = ALT_E_SUCCESS; }
    1512     }
    1513     else if (ALT_CLK_PERIPHERAL_PLL == clk)
    1514     {
    1515             // the PLL must be bypassed before getting here
     2080    ALT_STATUS_CODE status = ALT_E_SUCCESS;
     2081    uint32_t        temp;
     2082
     2083    if ( (mult == NULL) || (div == NULL) )
     2084    {
     2085                return ALT_E_BAD_ARG;
     2086    }
     2087
     2088    if (pll == ALT_CLK_MAIN_PLL)
     2089    {
     2090        temp = alt_read_word(ALT_CLKMGR_MAINPLL_VCO_ADDR);
     2091        *mult = ALT_CLKMGR_MAINPLL_VCO_NUMER_GET(temp) + 1;
     2092        *div  = ALT_CLKMGR_MAINPLL_VCO_DENOM_GET(temp) + 1;
     2093    }
     2094    else if (pll == ALT_CLK_PERIPHERAL_PLL)
     2095    {
    15162096        temp = alt_read_word(ALT_CLKMGR_PERPLL_VCO_ADDR);
    1517         temp &= ALT_CLKMGR_PERPLL_VCO_PSRC_CLR_MSK;
    1518         if ((ref_clk == ALT_CLK_IN_PIN_OSC1) || (ref_clk == ALT_CLK_OSC1))
    1519         {
    1520             temp |= ALT_CLKMGR_PERPLL_VCO_PSRC_SET(ALT_CLKMGR_PERPLL_VCO_PSRC_E_EOSC1);
    1521             alt_write_word(ALT_CLKMGR_PERPLL_VCO_ADDR, temp);
    1522             ret = ALT_E_SUCCESS;
    1523         }
    1524         else if (ref_clk == ALT_CLK_IN_PIN_OSC2)
    1525         {
    1526             temp |= ALT_CLKMGR_PERPLL_VCO_PSRC_SET(ALT_CLKMGR_PERPLL_VCO_PSRC_E_EOSC2);
    1527             alt_write_word(ALT_CLKMGR_PERPLL_VCO_ADDR, temp);
    1528             ret = ALT_E_SUCCESS;
    1529         }
    1530         else if (ref_clk == ALT_CLK_F2H_PERIPH_REF)
    1531         {
    1532             temp |= ALT_CLKMGR_PERPLL_VCO_PSRC_SET(ALT_CLKMGR_PERPLL_VCO_PSRC_E_F2S_PERIPH_REF);
    1533             alt_write_word(ALT_CLKMGR_PERPLL_VCO_ADDR, temp);
    1534             ret = ALT_E_SUCCESS;
    1535         }
    1536         else { ret = ALT_E_INV_OPTION; }
    1537     }
    1538     else if ( ALT_CLK_SDRAM_PLL == clk)
     2097        *mult = ALT_CLKMGR_PERPLL_VCO_NUMER_GET(temp) + 1;
     2098        *div  = ALT_CLKMGR_PERPLL_VCO_DENOM_GET(temp) + 1;
     2099    }
     2100    else if (pll == ALT_CLK_SDRAM_PLL)
    15392101    {
    15402102        temp = alt_read_word(ALT_CLKMGR_SDRPLL_VCO_ADDR);
    1541         temp &= ALT_CLKMGR_SDRPLL_VCO_SSRC_CLR_MSK;
    1542         if ((ref_clk == ALT_CLK_IN_PIN_OSC1) || (ref_clk == ALT_CLK_OSC1))
    1543         {
    1544             temp |= ALT_CLKMGR_SDRPLL_VCO_SSRC_SET(ALT_CLKMGR_SDRPLL_VCO_SSRC_E_EOSC1);
    1545             alt_write_word(ALT_CLKMGR_SDRPLL_VCO_ADDR, temp);
    1546             ret = ALT_E_SUCCESS;
    1547         }
    1548         else if (ref_clk == ALT_CLK_IN_PIN_OSC2)
    1549         {
    1550             temp |= ALT_CLKMGR_SDRPLL_VCO_SSRC_SET(ALT_CLKMGR_SDRPLL_VCO_SSRC_E_EOSC2);
    1551             alt_write_word(ALT_CLKMGR_SDRPLL_VCO_ADDR, temp);
    1552             ret = ALT_E_SUCCESS;
    1553         }
    1554         else if (ref_clk == ALT_CLK_F2H_SDRAM_REF)
    1555         {
    1556             temp |= ALT_CLKMGR_SDRPLL_VCO_SSRC_SET(ALT_CLKMGR_SDRPLL_VCO_SSRC_E_F2S_SDRAM_REF);
    1557             alt_write_word(ALT_CLKMGR_SDRPLL_VCO_ADDR, temp);
    1558             ret = ALT_E_SUCCESS;
    1559         }
    1560         else { ret = ALT_E_INV_OPTION; }
    1561     }
    1562 
    1563     else if ( ALT_CLK_L4_MP == clk)
    1564     {
    1565             // clock is gated off
    1566         if (ref_clk == ALT_CLK_MAIN_PLL_C1)
    1567         {
    1568             alt_clrbits_word(ALT_CLKMGR_MAINPLL_L4SRC_ADDR, ALT_CLKMGR_MAINPLL_L4SRC_L4MP_SET_MSK);
    1569             ret = ALT_E_SUCCESS;
    1570         }
    1571         else if (ref_clk == ALT_CLK_PERIPHERAL_PLL_C4)
    1572         {
    1573             alt_setbits_word(ALT_CLKMGR_MAINPLL_L4SRC_ADDR, ALT_CLKMGR_MAINPLL_L4SRC_L4MP_SET_MSK);
    1574             ret = ALT_E_SUCCESS;
    1575         }
    1576         else { ret = ALT_E_INV_OPTION; }
    1577     }
    1578 
    1579     else if ( ALT_CLK_L4_SP == clk)
    1580     {
    1581         if (ref_clk == ALT_CLK_MAIN_PLL_C1)
    1582         {
    1583             alt_clrbits_word(ALT_CLKMGR_MAINPLL_L4SRC_ADDR, ALT_CLKMGR_MAINPLL_L4SRC_L4SP_SET_MSK);
    1584             ret = ALT_E_SUCCESS;
    1585         }
    1586         else if (ref_clk == ALT_CLK_PERIPHERAL_PLL_C4)
    1587         {
    1588             alt_setbits_word(ALT_CLKMGR_MAINPLL_L4SRC_ADDR, ALT_CLKMGR_MAINPLL_L4SRC_L4SP_SET_MSK);
    1589             ret = ALT_E_SUCCESS;
    1590         }
    1591         else { ret = ALT_E_INV_OPTION; }
    1592     }
    1593 
    1594     else if ( ALT_CLK_SDMMC == clk)
    1595     {
    1596         temp = alt_read_word(ALT_CLKMGR_PERPLL_SRC_ADDR);
    1597         temp &= ALT_CLKMGR_PERPLL_SRC_SDMMC_CLR_MSK;
    1598         if (ref_clk == ALT_CLK_F2H_PERIPH_REF)
    1599         {
    1600             temp |= ALT_CLKMGR_PERPLL_SRC_SDMMC_SET(ALT_CLKMGR_PERPLL_SRC_SDMMC_E_F2S_PERIPH_REF_CLK);
    1601             alt_write_word(ALT_CLKMGR_PERPLL_SRC_ADDR, temp);
    1602             ret = ALT_E_SUCCESS;
    1603         }
    1604         else if ((ref_clk == ALT_CLK_MAIN_PLL_C4) || (ref_clk == ALT_CLK_MAIN_NAND_SDMMC))
    1605         {
    1606             temp |= ALT_CLKMGR_PERPLL_SRC_SDMMC_SET(ALT_CLKMGR_PERPLL_SRC_SDMMC_E_MAIN_NAND_CLK);
    1607             alt_write_word(ALT_CLKMGR_PERPLL_SRC_ADDR, temp);
    1608             ret = ALT_E_SUCCESS;
    1609         }
    1610         else if (ref_clk == ALT_CLK_PERIPHERAL_PLL_C3)
    1611         {
    1612             temp |= ALT_CLKMGR_PERPLL_SRC_SDMMC_SET(ALT_CLKMGR_PERPLL_SRC_SDMMC_E_PERIPH_NAND_CLK);
    1613             alt_write_word(ALT_CLKMGR_PERPLL_SRC_ADDR, temp);
    1614             ret = ALT_E_SUCCESS;
    1615         }
    1616         else { ret = ALT_E_INV_OPTION; }
    1617     }
    1618 
    1619     else if (( ALT_CLK_NAND_X == clk) || ( ALT_CLK_NAND == clk))
    1620     {
    1621         temp = alt_read_word(ALT_CLKMGR_PERPLL_SRC_ADDR);
    1622         temp &= ALT_CLKMGR_PERPLL_SRC_NAND_CLR_MSK;
    1623         if (ref_clk == ALT_CLK_F2H_PERIPH_REF)
    1624         {
    1625             temp |= ALT_CLKMGR_PERPLL_SRC_NAND_SET(ALT_CLKMGR_PERPLL_SRC_NAND_E_F2S_PERIPH_REF_CLK);
    1626             alt_write_word(ALT_CLKMGR_PERPLL_SRC_ADDR, temp);
    1627             ret = ALT_E_SUCCESS;
    1628         }
    1629         else if ((ref_clk == ALT_CLK_MAIN_PLL_C4) || (ref_clk == ALT_CLK_MAIN_NAND_SDMMC))
    1630         {
    1631             temp |= ALT_CLKMGR_PERPLL_SRC_NAND_SET(ALT_CLKMGR_PERPLL_SRC_NAND_E_MAIN_NAND_CLK);
    1632             alt_write_word(ALT_CLKMGR_PERPLL_SRC_ADDR, temp);
    1633             ret = ALT_E_SUCCESS;
    1634         }
    1635         else if (ref_clk == ALT_CLK_PERIPHERAL_PLL_C3)
    1636         {
    1637             temp |= ALT_CLKMGR_PERPLL_SRC_NAND_SET(ALT_CLKMGR_PERPLL_SRC_NAND_E_PERIPH_NAND_CLK);
    1638             alt_write_word(ALT_CLKMGR_PERPLL_SRC_ADDR, temp);
    1639             ret = ALT_E_SUCCESS;
    1640         }
    1641         else { ret = ALT_E_INV_OPTION; }
    1642     }
    1643 
    1644     else if ( ALT_CLK_QSPI == clk)
    1645     {
    1646         temp = alt_read_word(ALT_CLKMGR_PERPLL_SRC_ADDR);
    1647         temp &= ALT_CLKMGR_PERPLL_SRC_QSPI_CLR_MSK;
    1648         if (ref_clk == ALT_CLK_F2H_PERIPH_REF)
    1649         {
    1650             temp |= ALT_CLKMGR_PERPLL_SRC_QSPI_SET(ALT_CLKMGR_PERPLL_SRC_QSPI_E_F2S_PERIPH_REF_CLK);
    1651             alt_write_word(ALT_CLKMGR_PERPLL_SRC_ADDR, temp);
    1652             ret = ALT_E_SUCCESS;
    1653         }
    1654         else if ((ref_clk == ALT_CLK_MAIN_PLL_C3) || (ref_clk == ALT_CLK_MAIN_QSPI))
    1655         {
    1656             temp |= ALT_CLKMGR_PERPLL_SRC_QSPI_SET(ALT_CLKMGR_PERPLL_SRC_QSPI_E_MAIN_QSPI_CLK);
    1657             alt_write_word(ALT_CLKMGR_PERPLL_SRC_ADDR, temp);
    1658             ret = ALT_E_SUCCESS;
    1659         }
    1660         else if (ref_clk == ALT_CLK_PERIPHERAL_PLL_C2)
    1661         {
    1662             temp |= ALT_CLKMGR_PERPLL_SRC_QSPI_SET(ALT_CLKMGR_PERPLL_SRC_QSPI_E_PERIPH_QSPI_CLK);
    1663             alt_write_word(ALT_CLKMGR_PERPLL_SRC_ADDR, temp);
    1664             ret = ALT_E_SUCCESS;
    1665         }
    1666         else { ret = ALT_E_INV_OPTION; }
    1667     }
    1668     return ret;
    1669 }
    1670 
    1671 
    1672 /****************************************************************************************/
    1673 /* alt_clk_ext_clk_freq_set() specifies the frequency of the external clock source as   */
    1674 /* a measure of Hz. This value is stored in a static array and used for calculations.   */
    1675 /* The supplied frequency should be within the Fmin and Fmax values allowed for the     */
    1676 /* external clock source.                                                               */
    1677 /****************************************************************************************/
    1678 
    1679 
    1680 ALT_STATUS_CODE alt_clk_ext_clk_freq_set(ALT_CLK_t clk, alt_freq_t freq)
    1681 {
    1682     ALT_STATUS_CODE     ret = ALT_E_BAD_ARG;
    1683 
    1684     if ((clk == ALT_CLK_IN_PIN_OSC1) || (clk == ALT_CLK_OSC1))      // two names for one input
    1685     {
    1686         if ((freq >= alt_ext_clk_paramblok.clkosc1.freqmin) && (freq <= alt_ext_clk_paramblok.clkosc1.freqmax))
    1687         {
    1688             alt_ext_clk_paramblok.clkosc1.freqcur = freq;
    1689             ret = ALT_E_SUCCESS;
    1690         }
    1691         else { ret = ALT_E_ARG_RANGE; }
    1692     }
    1693 
    1694     else if (clk == ALT_CLK_IN_PIN_OSC2)                            // the other clock input pin
    1695     {
    1696         if ((freq >= alt_ext_clk_paramblok.clkosc2.freqmin) && (freq <= alt_ext_clk_paramblok.clkosc2.freqmax))
    1697         {
    1698             alt_ext_clk_paramblok.clkosc2.freqcur = freq;
    1699             ret = ALT_E_SUCCESS;
    1700         }
    1701         else { ret = ALT_E_ARG_RANGE; }
    1702     }
    1703 
    1704     else if (clk == ALT_CLK_F2H_PERIPH_REF)                         // clock from the FPGA
    1705     {
    1706         if ((freq >= alt_ext_clk_paramblok.periph.freqmin) && (freq <= alt_ext_clk_paramblok.periph.freqmax))
    1707         {
    1708             alt_ext_clk_paramblok.periph.freqcur = freq;
    1709             ret = ALT_E_SUCCESS;
    1710         }
    1711         else { ret = ALT_E_ARG_RANGE; }
    1712     }
    1713 
    1714     else if (clk == ALT_CLK_F2H_SDRAM_REF)                          // clock from the FPGA SDRAM
    1715     {
    1716         if ((freq >= alt_ext_clk_paramblok.sdram.freqmin) && (freq <= alt_ext_clk_paramblok.sdram.freqmax))
    1717         {
    1718             alt_ext_clk_paramblok.sdram.freqcur = freq;
    1719             ret = ALT_E_SUCCESS;
    1720         }
    1721         else { ret = ALT_E_ARG_RANGE; }
    1722     }
    1723     return ret;
    1724 }
    1725 
    1726 
    1727 /****************************************************************************************/
    1728 /* alt_clk_ext_clk_freq_get returns the frequency of the external clock source as       */
    1729 /* a measure of Hz. This value is stored in a static array.                             */
    1730 /****************************************************************************************/
    1731 
    1732 
    1733 alt_freq_t alt_clk_ext_clk_freq_get(ALT_CLK_t clk)
    1734 {
    1735     uint32_t    ret = 0;
    1736 
    1737     if ((clk == ALT_CLK_IN_PIN_OSC1) || (clk == ALT_CLK_OSC1))      // two names for one input
    1738     {
    1739         ret = alt_ext_clk_paramblok.clkosc1.freqcur;
    1740     }
    1741     else if (clk == ALT_CLK_IN_PIN_OSC2)
    1742     {
    1743         ret = alt_ext_clk_paramblok.clkosc2.freqcur;
    1744     }
    1745     else if (clk == ALT_CLK_F2H_PERIPH_REF)                         // clock from the FPGA
    1746     {
    1747         ret = alt_ext_clk_paramblok.periph.freqcur;
    1748     }
    1749     else if (clk == ALT_CLK_F2H_SDRAM_REF)                         // clock from the FPGA
    1750     {
    1751         ret = alt_ext_clk_paramblok.sdram.freqcur;
    1752     }
    1753     return ret;
    1754 }
    1755 
    1756 
    1757 /****************************************************************************************/
    1758 /* alt_clk_pll_cfg_get() returns the current PLL configuration.                         */
    1759 /*****************