Changeset 9855690 in rtems


Ignore:
Timestamp:
Apr 11, 2017, 8:47:39 AM (3 years ago)
Author:
Daniel Hellstrom <daniel@…>
Branches:
master
Children:
91541551
Parents:
3a650d3b
git-author:
Daniel Hellstrom <daniel@…> (04/11/17 08:47:39)
git-committer:
Daniel Hellstrom <daniel@…> (05/14/17 10:31:58)
Message:

leon, grcan: split hw_stop() into hw and sw stop

this is to avoid owning the spin-lock during semaphore operations.

File:
1 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/sparc/shared/can/grcan.c

    r3a650d3b r9855690  
    489489        pDev->regs->rx0ctrl = 0;
    490490        pDev->regs->tx0ctrl = 0;
    491 
     491}
     492
     493static void grcan_sw_stop(struct grcan_priv *pDev)
     494{
    492495        /* Reset semaphores to the initial state and wakeing
    493496         * all threads waiting for an IRQ. The threads that
     
    15781581        struct grcan_priv *pDev = d;
    15791582        SPIN_IRQFLAGS(oldLevel);
     1583        int do_sw_stop;
    15801584
    15811585        FUNCDBG();
     
    15871591        if (pDev->started == STATE_STARTED) {
    15881592                grcan_hw_stop(pDev);
     1593                do_sw_stop = 1;
    15891594                DBGC(DBG_STATE, "STARTED->STOPPED\n");
    15901595        } else {
     
    15941599                 */
    15951600                DBGC(DBG_STATE, "[STOPPED|BUSOFF|AHBERR]->STOPPED\n");
     1601                do_sw_stop = 0;
    15961602        }
    15971603        pDev->started = STATE_STOPPED;
    15981604        SPIN_UNLOCK_IRQ(&pDev->devlock, oldLevel);
     1605
     1606        if (do_sw_stop)
     1607                grcan_sw_stop(pDev);
    15991608
    16001609        /* Disable interrupts */
     
    19331942                 */
    19341943                SPIN_UNLOCK(&pDev->devlock, irqflags);
     1944
     1945                /* flush semaphores to wake blocked threads */
     1946                grcan_sw_stop(pDev);
     1947
    19351948                /*
    19361949                 * NOTE: Another interrupt may be pending now so ISR could be
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