Ignore:
Timestamp:
08/10/99 16:41:44 (23 years ago)
Author:
Joel Sherrill <joel.sherrill@…>
Branches:
4.10, 4.11, 4.8, 4.9, 5, master
Children:
cef2fb5f
Parents:
908436c1
Message:

Patch from Eric Valette <valette@…> and Emmanuel Raguet
<raguet@…>:

  • the dec21140 driver code has been hardened (various bug fixed) Emmanuel,
  • bug in the mcp750 init code have been fixed (interrupt stack/initial stack initialization), BSS correctly cleared (Eric V)
  • remote debugging over TCP/IP is nearly complete (berakpoints, backtrace, variables,...) (Eric V),
  • exception handling code has also been improved in order to fully support RDBG requirements (Eric V),
Location:
c/src/lib/libbsp/powerpc/motorola_powerpc
Files:
11 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/powerpc/motorola_powerpc/dec21140/dec21140.c

    r908436c1 r981b99f  
    118118 * Receive buffer size -- Allow for a full ethernet packet including CRC
    119119 */
    120 #define RBUF_SIZE       1520
     120#define RBUF_SIZE       1536
    121121
    122122#define ET_MINLEN 60            /* minimum message length */
     
    420420  cp = (char *)malloc((NRXBUFS+NTXBUFS)*(sizeof(struct MD)+ RBUF_SIZE) + PPC_CACHE_ALIGNMENT);
    421421  sc->bufferBase = cp;
    422   cp += (PPC_CACHE_ALIGNMENT - (int)cp) & MASK_OFFSET;
     422  if ((unsigned int)cp & (PPC_CACHE_ALIGNMENT-1))
     423    cp = ((unsigned int)cp + PPC_CACHE_ALIGNMENT) & ~(PPC_CACHE_ALIGNMENT-1);
    423424#ifdef PCI_BRIDGE_DOES_NOT_ENSURE_CACHE_COHERENCY_FOR_DMA
    424425  if (_CPU_is_paging_enabled())
  • c/src/lib/libbsp/powerpc/motorola_powerpc/include/bsp.h

    r908436c1 r981b99f  
    1717#include <libcpu/io.h>
    1818#include <clockdrv.h>
     19#include <bsp/vectors.h>
    1920
    2021#ifndef ASM
  • c/src/lib/libbsp/powerpc/motorola_powerpc/irq/i8259.c

    r908436c1 r981b99f  
    2222 * lower byte is interrupt mask on the master PIC.
    2323 * while upper bits are interrupt on the slave PIC.
    24  * This cache is initialized in ldseg.s
    2524 */
    26 volatile rtems_i8259_masks i8259s_cache;
     25volatile rtems_i8259_masks i8259s_cache = 0xfffb;
    2726
    2827/*-------------------------------------------------------------------------+
     
    5453  else
    5554  {
    56     outport_byte(PIC_SLAVE_IMR_IO_PORT, ((i8259s_cache & 0xff00) > 8));
     55    outport_byte(PIC_SLAVE_IMR_IO_PORT, ((i8259s_cache & 0xff00) >> 8));
    5756  }
    5857  _CPU_ISR_Enable (level);
     
    8988  else
    9089  {
    91     outport_byte(PIC_SLAVE_IMR_IO_PORT, ((i8259s_cache & 0xff00) > 8));
     90    outport_byte(PIC_SLAVE_IMR_IO_PORT, ((i8259s_cache & 0xff00) >> 8));
    9291  }
    9392  _CPU_ISR_Enable (level);
     
    120119{
    121120  if (irqLine >= 8) {
    122    outport_byte(PIC_SLAVE_COMMAND_IO_PORT, PIC_EOI);
     121    outport_byte(PIC_MASTER_COMMAND_IO_PORT, SLAVE_PIC_EOSI);
     122    outport_byte(PIC_SLAVE_COMMAND_IO_PORT, (PIC_EOSI | (irqLine - 8)));
    123123  }
    124   outport_byte(PIC_MASTER_COMMAND_IO_PORT, PIC_EOI);
     124  else {
     125    outport_byte(PIC_MASTER_COMMAND_IO_PORT, (PIC_EOSI | irqLine));
     126  }
    125127
    126128  return 0;
     
    147149  outport_byte(PIC_SLAVE_IMR_IO_PORT, 0xFF); /* Mask all */
    148150 
    149   i8259s_cache = 0xFFFB;
    150151}
    151152
  • c/src/lib/libbsp/powerpc/motorola_powerpc/irq/irq.c

    r908436c1 r981b99f  
    379379   
    380380 
    381 void _ThreadProcessSignalsFromIrq (exception_frame* ctx)
     381void _ThreadProcessSignalsFromIrq (BSP_Exception_frame* ctx)
    382382{
    383383  /*
  • c/src/lib/libbsp/powerpc/motorola_powerpc/irq/irq.h

    r908436c1 r981b99f  
    5555    /* Command for specific EOI (End Of Interrupt): Interrupt acknowledge */
    5656#define PIC_EOSI        0x60    /* End of Specific Interrupt (EOSI) */
     57#define SLAVE_PIC_EOSI  0x62    /* End of Specific Interrupt (EOSI) for cascade */
    5758#define PIC_EOI         0x20    /* Generic End of Interrupt (EOI) */
    5859
  • c/src/lib/libbsp/powerpc/motorola_powerpc/irq/irq_asm.S

    r908436c1 r981b99f  
    213213        stmw    r16, GPR16_OFFSET(r1)
    214214        addi    r3, r1, 0x8
     215        /*
     216         * compute SP at exception entry
     217         */
     218        addi    r2, r1, EXCEPTION_FRAME_END
     219        /*
     220         * store it at the right place
     221         */
    215222        bl      _ISR_Signals_to_thread_executing
    216223        /*
  • c/src/lib/libbsp/powerpc/motorola_powerpc/start/start.S

    r908436c1 r981b99f  
    11/*
    2  *  arch/ppc/kernel/head.S
     2 *  start.S :     RTEMS entry point
     3 *
     4 *  Copyright (C) 1999 Eric Valette. valette@crf.canon.fr
     5 *
     6 *  The license and distribution terms for this file may be
     7 *  found in found in the file LICENSE in this distribution or at
     8 *  http://www.OARcorp.com/rtems/license.html.
    39 *
    410 *  $Id$
    511 *
    6  *  PowerPC version
    7  *    Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
    8  *
    9  *  Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
    10  *  Adapted for Power Macintosh by Paul Mackerras.
    11  *  Low-level exception handlers and MMU support
    12  *  rewritten by Paul Mackerras.
    13  *    Copyright (C) 1996 Paul Mackerras.
    14  *  MPC8xx modifications Copyright (C) 1997 Dan Malek (dmalek@jlc.net).
    15  *  Amiga/APUS changes by Jesper Skov (jskov@cygnus.co.uk).
    16  *
    17  *  This file contains the low-level support and setup for the
    18  *  PowerPC platform, including trap and interrupt dispatch.
    19  *  Also included here is low-level thread/task switch support.
    20  *
    21  *  This program is free software; you can redistribute it and/or
    22  *  modify it under the terms of the GNU General Public License
    23  *  as published by the Free Software Foundation; either version
    24  *  2 of the License, or (at your option) any later version.
    25  *     
    2612 */
    2713
     
    2915#include <libcpu/io.h>
    3016#include <rtems/score/targopts.h>
     17#include <rtems/score/cpu.h>
    3118#include "asm.h"
    32        
     19
    3320#define SYNC \
    3421        sync; \
     
    9279         * stack = &__rtems_end + 4096
    9380         */
    94         addis   r9,r0, __rtems_end+4096@ha
    95         addi    r9,r9, __rtems_end+4096@l
     81        addis   r9,r0, __rtems_end+(4096-CPU_MINIMUM_STACK_FRAME_SIZE)@ha
     82        addi    r9,r9, __rtems_end+(4096-CPU_MINIMUM_STACK_FRAME_SIZE)@l
    9683        mr      r1, r9
    9784        bl      zero_bss
     
    143130        mtctr   r30
    144131        bctr   
    145        
    146        
    147 
    148 
    149 
  • c/src/lib/libbsp/powerpc/motorola_powerpc/startup/bspstart.c

    r908436c1 r981b99f  
    132132    heap_size = (BSP_mem_size - heap_start) - BSP_Configuration.work_space_size;
    133133
     134#ifdef SHOW_MORE_INIT_SETTINGS
    134135    printk(" HEAP start %x  size %x\n", heap_start, heap_size);
     136#endif   
    135137    bsp_libc_init((void *) heap_start, heap_size, 0);
    136138
     
    142144void zero_bss()
    143145{
    144   memset(&__bss_start, 0, &__rtems_end - &__bss_start);
     146  memset(&__bss_start, 0, ((unsigned) (&__rtems_end)) - ((unsigned) &__bss_start));
    145147}
    146148
     
    185187   * so there is no need to set it in r1 again...
    186188   */
    187   stack = ((unsigned char*) &__rtems_end) + INIT_STACK_SIZE;
     189  stack = ((unsigned char*) &__rtems_end) + INIT_STACK_SIZE - CPU_MINIMUM_STACK_FRAME_SIZE;
    188190  /*
    189191   * Initialize the interrupt related settings
     
    194196   * some settings below...
    195197   */
    196   intrStack = ((unsigned char*) &__rtems_end) + INIT_STACK_SIZE + INTR_STACK_SIZE;
     198  intrStack = ((unsigned char*) &__rtems_end) + INIT_STACK_SIZE + INTR_STACK_SIZE - CPU_MINIMUM_STACK_FRAME_SIZE;
    197199  asm volatile ("mtspr  273, %0" : "=r" (intrStack) : "0" (intrStack));
    198200  asm volatile ("mtspr  272, %0" : "=r" (intrNestingLevel) : "0" (intrNestingLevel));
     
    287289  Cpu_table.exceptions_in_RAM           = TRUE;
    288290
     291#ifdef SHOW_MORE_INIT_SETTINGS
    289292  printk("BSP_Configuration.work_space_size = %x\n", BSP_Configuration.work_space_size);
     293#endif 
    290294  work_space_start =
    291295    (unsigned char *)BSP_mem_size - BSP_Configuration.work_space_size;
     
    307311   */
    308312  BSP_rtems_irq_mng_init(0);
     313#ifdef SHOW_MORE_INIT_SETTINGS
    309314  printk("Exit from bspstart\n");
    310 }
     315#endif 
     316}
  • c/src/lib/libbsp/powerpc/motorola_powerpc/vectors/vectors.S

    r908436c1 r981b99f  
    8787        mfxer   r28
    8888        stw     r28,  EXC_XER_OFFSET(r1)
     89        /*
     90         * compute SP at exception entry
     91         */
     92        addi    r2, r1, EXCEPTION_FRAME_END
     93        /*
     94         * store it at the right place
     95         */
     96        stw     r2, GPR1_OFFSET(r1)
    8997        /*
    9098         * Enable data and instruction address translation, exception nesting
     
    98106         * Call C exception handler
    99107         */
     108        /*
     109         * store the execption frame address in r3 (first param)
     110         */
    100111        addi    r3, r1, 0x8
    101         bl C_exception_handler
     112        /*
     113         * globalExceptHdl(r3)
     114         */
     115        addis   r4, 0, globalExceptHdl@ha
     116        lwz     r5, globalExceptHdl@l(r4)
     117        mtlr    r5
     118        blrl
    102119        /*
    103120         * Restore registers status
     
    136153        SYNC
    137154        rfi
    138 
    139 
    140 
    141 
    142 
  • c/src/lib/libbsp/powerpc/motorola_powerpc/vectors/vectors.h

    r908436c1 r981b99f  
    129129  unsigned      EXC_MSR;
    130130  unsigned      EXC_DAR;
    131 } exception_frame;
     131}BSP_Exception_frame;
    132132
    133 extern void C_exception_handler(exception_frame* excPtr);
     133
     134typedef void (*exception_handler_t) (BSP_Exception_frame* excPtr);
     135extern exception_handler_t globalExceptHdl;
     136/*
     137 * Compatibility with pc386
     138 */
     139typedef BSP_Exception_frame CPU_Exception_frame;
     140typedef exception_handler_t cpuExcHandlerType;
    134141
    135142#endif /* ASM */
  • c/src/lib/libbsp/powerpc/motorola_powerpc/vectors/vectors_init.c

    r908436c1 r981b99f  
    2020static rtems_raw_except_connect_data    exception_table[LAST_VALID_EXC + 1];
    2121
    22 void C_exception_handler(exception_frame* excPtr)
     22exception_handler_t globalExceptHdl;
     23
     24void C_exception_handler(BSP_Exception_frame* excPtr)
    2325{
    2426  int recoverable = 0;
     
    8284{
    8385  int i;
    84  
    85   exception_config.exceptSize           = LAST_VALID_EXC + 1;
    86   exception_config.rawExceptHdlTbl      = &exception_table[0];
     86
     87  /*
     88   * Initialize pointer used by low level execption handling
     89   */
     90  globalExceptHdl                               = C_exception_handler;
     91  /*
     92   * Put  default_exception_vector_code_prolog at relevant exception
     93   * code entry addresses
     94   */
     95  exception_config.exceptSize                   = LAST_VALID_EXC + 1;
     96  exception_config.rawExceptHdlTbl              = &exception_table[0];
    8797  exception_config.defaultRawEntry.exceptIndex  = 0;
    8898  exception_config.defaultRawEntry.hdl.vector   = 0;
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