Changeset 981b99f in rtems


Ignore:
Timestamp:
Aug 10, 1999, 4:41:44 PM (20 years ago)
Author:
Joel Sherrill <joel.sherrill@…>
Branches:
4.10, 4.11, 4.8, 4.9, master
Children:
cef2fb5f
Parents:
908436c1
Message:

Patch from Eric Valette <valette@…> and Emmanuel Raguet
<raguet@…>:

  • the dec21140 driver code has been hardened (various bug fixed) Emmanuel,
  • bug in the mcp750 init code have been fixed (interrupt stack/initial stack initialization), BSS correctly cleared (Eric V)
  • remote debugging over TCP/IP is nearly complete (berakpoints, backtrace, variables,...) (Eric V),
  • exception handling code has also been improved in order to fully support RDBG requirements (Eric V),
Files:
21 added
68 edited

Legend:

Unmodified
Added
Removed
  • c/src/exec/score/cpu/powerpc/Makefile.in

    r908436c1 r981b99f  
    2525
    2626ifeq ($(RTEMS_CPU_MODEL),mpc750)
    27 CPUDIR = other_cpu
     27CPUDIR = mpc750
    2828else
    2929CPUDIR = other_cpu
  • c/src/exec/score/cpu/powerpc/mpc750/cpu.c

    r908436c1 r981b99f  
    5959 */
    6060
    61 #define CPU_MINIMUM_STACK_FRAME_SIZE 8
    62 
    6361void _CPU_Context_Initialize(
    6462  Context_Control  *the_context,
  • c/src/exec/score/cpu/powerpc/mpc750/cpu.h

    r908436c1 r981b99f  
    344344 *  a debugger such as gdb.  But that is another problem.
    345345 */
     346
     347#ifndef ASM
    346348
    347349typedef struct {
     
    466468SCORE_EXTERN void               *_CPU_Interrupt_stack_high;
    467469
     470#endif /* ndef ASM */
     471
    468472/*
    469473 *  This defines the number of levels and the mask used to pick those
     
    490494 */
    491495
    492 
     496#ifndef ASM
     497 
    493498SCORE_EXTERN struct {
    494499  unsigned32 *Disable_level;
     
    498503
    499504} _CPU_IRQ_info CPU_STRUCTURE_ALIGNMENT;
     505
     506#endif /* ndef ASM */
    500507
    501508/*
     
    585592#define CPU_STACK_ALIGNMENT        (PPC_STACK_ALIGNMENT)
    586593
     594/*
     595 * Needed for Interrupt stack
     596 */
     597#define CPU_MINIMUM_STACK_FRAME_SIZE 8
     598
     599
    587600/* ISR handler macros */
    588601
     
    594607#define loc_string(a,b) a " (" #b ")\n"
    595608
     609#ifndef ASM
    596610 
    597611static inline unsigned32 _CPU_ISR_Get_level( void )
     
    942956}
    943957
     958#endif /* ndef ASM */
     959
    944960#ifdef __cplusplus
    945961}
  • c/src/lib/include/rdbg/i386/rdbg_f.h

    r908436c1 r981b99f  
    66 *
    77 * Synopsis = Machine-dependent header file
     8 *
     9 * $Id$
    810 *
    911 **************************************************************************
     
    1820#define EFLAGS_TF 0x00100
    1921
    20 typedef struct Exception_context_struct {
    21   struct Exception_context_struct *next;
    22   struct Exception_context_struct *previous;
    23   Objects_Id id;
    24   Objects_Id semaphoreId;
    25   CPU_Exception_frame *ctx;
    26 } Exception_context;
     22static inline int isRdbgException(Exception_context *ctx)
     23{
     24  if (
     25      ctx->ctx->idtIndex != I386_EXCEPTION_DEBUG &&
     26      ctx->ctx->idtIndex != I386_EXCEPTION_BREAKPOINT &&
     27      ctx->ctx->idtIndex != I386_EXCEPTION_ENTER_RDBG
     28      ) return 0;
     29  else return 1;
     30}
     31static inline int getExcNum(Exception_context *ctx)
     32{
     33  return ctx->ctx->idtIndex;
     34}
    2735
    28 extern int      PushExceptCtx           (Objects_Id Id,
    29                                          Objects_Id semId,
    30                                          CPU_Exception_frame *ctx);
    31 extern int      PopExceptCtx            (Objects_Id Id);
    32 extern Exception_context *GetExceptCtx  (Objects_Id Id);
    33 extern int      Single_Step             (CPU_Exception_frame* ctx);
    34 extern int      CheckForSingleStep      (CPU_Exception_frame* ctx);
    35 extern void     BreakPointExcHdl        (CPU_Exception_frame *ctx);
    36 extern void     CtxToRegs               (const CPU_Exception_frame*,xdr_regs*);
    37 extern void     RegsToCtx               (const xdr_regs*,CPU_Exception_frame*);
    38 
    39 extern void     enterRdbg               ();
    40 extern void     get_ctx_thread          (Thread_Control *thread,
    41                                          CPU_Exception_frame* ctx);
    42 extern void     set_ctx_thread          (Thread_Control *thread,
    43                                          CPU_Exception_frame* ctx);
    44 
    45 void copyback_data_cache_and_invalidate_instr_cache();
    46 
    47 extern int      ExitForSingleStep;
    48 
     36extern void connect_rdbg_exception();
    4937
    5038#endif
  • c/src/lib/include/rdbg/i386/reg.h

    r908436c1 r981b99f  
    1 
     1/*
     2 * Registers Offset in frame definition
     3 *
     4 * $Id$
     5 */
    26
    37#define NBREGS  19
  • c/src/lib/include/rdbg/rdbg.h

    r908436c1 r981b99f  
    55 *
    66 * Synopsis  =   rdbg.h
     7 *
     8 * $Id$
    79 *
    810 **************************************************************************
     
    1517#include <sys/socket.h>
    1618#include <netinet/in.h>
    17 #include <rdbg/rdbg_f.h>
    1819#include <stdlib.h>             /* For malloc() and free() prototypes */
    1920#include <bsp.h>               
     21#include <rtems.h>
    2022
    2123#define Malloc(size)            malloc (size)
     
    5052int       svcudp_enablecache    (SVCXPRT *transp, u_long size);
    5153
     54typedef struct Exception_context_struct {
     55  struct Exception_context_struct *next;
     56  struct Exception_context_struct *previous;
     57  Objects_Id id;
     58  Objects_Id semaphoreId;
     59  CPU_Exception_frame *ctx;
     60} Exception_context;
     61
     62struct          xdr_regs;
     63
     64extern int      PushExceptCtx           (Objects_Id Id,
     65                                         Objects_Id semId,
     66                                         CPU_Exception_frame *ctx);
     67extern int      PopExceptCtx            (Objects_Id Id);
     68extern Exception_context *GetExceptCtx  (Objects_Id Id);
     69extern int      Single_Step             (CPU_Exception_frame* ctx);
     70extern int      CheckForSingleStep      (CPU_Exception_frame* ctx);
     71extern void     BreakPointExcHdl        (CPU_Exception_frame *ctx);
     72extern void     CtxToRegs               (const CPU_Exception_frame*,struct xdr_regs*);
     73extern void     RegsToCtx               (const struct xdr_regs*,CPU_Exception_frame*);
     74
     75extern void     enterRdbg               ();
     76extern void     get_ctx_thread          (Thread_Control *thread,
     77                                         CPU_Exception_frame* ctx);
     78extern void     set_ctx_thread          (Thread_Control *thread,
     79                                         CPU_Exception_frame* ctx);
     80extern int      PushSavedExceptCtx      ( Objects_Id Id,
     81                                          CPU_Exception_frame *ctx );
     82extern int      ExcepToSig              (Exception_context *ctx);
     83
     84extern int      ExitForSingleStep;
     85
     86extern rtems_id serializeSemId;
     87extern rtems_id wakeupEventSemId;
     88extern volatile unsigned int NbSerializedCtx;
     89
     90void copyback_data_cache_and_invalidate_instr_cache(unsigned char* addr, int size);
     91
     92#include <rdbg/rdbg_f.h>
     93
    5294#endif /* !RDBG_H */
    5395
  • c/src/lib/include/rdbg/servrpc.h

    r908436c1 r981b99f  
     1/*
     2 * $Id$
     3 */
    14
    25#ifndef SERVRPC_H
     
    3033extern const char* BmsgNames[]; /* list of BMSG_xxx names */
    3134extern const char* PtraceName(int req);
     35
     36#ifdef i386                     /* low-high machine such as 386 */
     37#define HL_W(w)         (((UINT16)(w)>>8)+((((w)&0xFF)<<8)))
     38#define HL_D(d)         (((UINT32)(d)>>24)+(((d)&0x00FF0000)>>8) \
     39                       +(((d)&0xFF00)<<8)+(((d)&0xFF)<<24))
     40#else
     41#define HL_W(w)         w
     42#define HL_D(d)         d
     43#endif
    3244
    3345# define DPRINTF(a)     (rdb_debug ? printk ("%d >>> ", getId()), printk a : 0)
  • c/src/lib/libbsp/powerpc/mcp750/dec21140/dec21140.c

    r908436c1 r981b99f  
    118118 * Receive buffer size -- Allow for a full ethernet packet including CRC
    119119 */
    120 #define RBUF_SIZE       1520
     120#define RBUF_SIZE       1536
    121121
    122122#define ET_MINLEN 60            /* minimum message length */
     
    420420  cp = (char *)malloc((NRXBUFS+NTXBUFS)*(sizeof(struct MD)+ RBUF_SIZE) + PPC_CACHE_ALIGNMENT);
    421421  sc->bufferBase = cp;
    422   cp += (PPC_CACHE_ALIGNMENT - (int)cp) & MASK_OFFSET;
     422  if ((unsigned int)cp & (PPC_CACHE_ALIGNMENT-1))
     423    cp = ((unsigned int)cp + PPC_CACHE_ALIGNMENT) & ~(PPC_CACHE_ALIGNMENT-1);
    423424#ifdef PCI_BRIDGE_DOES_NOT_ENSURE_CACHE_COHERENCY_FOR_DMA
    424425  if (_CPU_is_paging_enabled())
  • c/src/lib/libbsp/powerpc/mcp750/include/bsp.h

    r908436c1 r981b99f  
    1717#include <libcpu/io.h>
    1818#include <clockdrv.h>
     19#include <bsp/vectors.h>
    1920
    2021#ifndef ASM
  • c/src/lib/libbsp/powerpc/mcp750/irq/i8259.c

    r908436c1 r981b99f  
    2222 * lower byte is interrupt mask on the master PIC.
    2323 * while upper bits are interrupt on the slave PIC.
    24  * This cache is initialized in ldseg.s
    2524 */
    26 volatile rtems_i8259_masks i8259s_cache;
     25volatile rtems_i8259_masks i8259s_cache = 0xfffb;
    2726
    2827/*-------------------------------------------------------------------------+
     
    5453  else
    5554  {
    56     outport_byte(PIC_SLAVE_IMR_IO_PORT, ((i8259s_cache & 0xff00) > 8));
     55    outport_byte(PIC_SLAVE_IMR_IO_PORT, ((i8259s_cache & 0xff00) >> 8));
    5756  }
    5857  _CPU_ISR_Enable (level);
     
    8988  else
    9089  {
    91     outport_byte(PIC_SLAVE_IMR_IO_PORT, ((i8259s_cache & 0xff00) > 8));
     90    outport_byte(PIC_SLAVE_IMR_IO_PORT, ((i8259s_cache & 0xff00) >> 8));
    9291  }
    9392  _CPU_ISR_Enable (level);
     
    120119{
    121120  if (irqLine >= 8) {
    122    outport_byte(PIC_SLAVE_COMMAND_IO_PORT, PIC_EOI);
     121    outport_byte(PIC_MASTER_COMMAND_IO_PORT, SLAVE_PIC_EOSI);
     122    outport_byte(PIC_SLAVE_COMMAND_IO_PORT, (PIC_EOSI | (irqLine - 8)));
    123123  }
    124   outport_byte(PIC_MASTER_COMMAND_IO_PORT, PIC_EOI);
     124  else {
     125    outport_byte(PIC_MASTER_COMMAND_IO_PORT, (PIC_EOSI | irqLine));
     126  }
    125127
    126128  return 0;
     
    147149  outport_byte(PIC_SLAVE_IMR_IO_PORT, 0xFF); /* Mask all */
    148150 
    149   i8259s_cache = 0xFFFB;
    150151}
    151152
  • c/src/lib/libbsp/powerpc/mcp750/irq/irq.c

    r908436c1 r981b99f  
    379379   
    380380 
    381 void _ThreadProcessSignalsFromIrq (exception_frame* ctx)
     381void _ThreadProcessSignalsFromIrq (BSP_Exception_frame* ctx)
    382382{
    383383  /*
  • c/src/lib/libbsp/powerpc/mcp750/irq/irq.h

    r908436c1 r981b99f  
    5555    /* Command for specific EOI (End Of Interrupt): Interrupt acknowledge */
    5656#define PIC_EOSI        0x60    /* End of Specific Interrupt (EOSI) */
     57#define SLAVE_PIC_EOSI  0x62    /* End of Specific Interrupt (EOSI) for cascade */
    5758#define PIC_EOI         0x20    /* Generic End of Interrupt (EOI) */
    5859
  • c/src/lib/libbsp/powerpc/mcp750/irq/irq_asm.S

    r908436c1 r981b99f  
    213213        stmw    r16, GPR16_OFFSET(r1)
    214214        addi    r3, r1, 0x8
     215        /*
     216         * compute SP at exception entry
     217         */
     218        addi    r2, r1, EXCEPTION_FRAME_END
     219        /*
     220         * store it at the right place
     221         */
    215222        bl      _ISR_Signals_to_thread_executing
    216223        /*
  • c/src/lib/libbsp/powerpc/mcp750/start/start.S

    r908436c1 r981b99f  
    11/*
    2  *  arch/ppc/kernel/head.S
     2 *  start.S :     RTEMS entry point
     3 *
     4 *  Copyright (C) 1999 Eric Valette. valette@crf.canon.fr
     5 *
     6 *  The license and distribution terms for this file may be
     7 *  found in found in the file LICENSE in this distribution or at
     8 *  http://www.OARcorp.com/rtems/license.html.
    39 *
    410 *  $Id$
    511 *
    6  *  PowerPC version
    7  *    Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
    8  *
    9  *  Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
    10  *  Adapted for Power Macintosh by Paul Mackerras.
    11  *  Low-level exception handlers and MMU support
    12  *  rewritten by Paul Mackerras.
    13  *    Copyright (C) 1996 Paul Mackerras.
    14  *  MPC8xx modifications Copyright (C) 1997 Dan Malek (dmalek@jlc.net).
    15  *  Amiga/APUS changes by Jesper Skov (jskov@cygnus.co.uk).
    16  *
    17  *  This file contains the low-level support and setup for the
    18  *  PowerPC platform, including trap and interrupt dispatch.
    19  *  Also included here is low-level thread/task switch support.
    20  *
    21  *  This program is free software; you can redistribute it and/or
    22  *  modify it under the terms of the GNU General Public License
    23  *  as published by the Free Software Foundation; either version
    24  *  2 of the License, or (at your option) any later version.
    25  *     
    2612 */
    2713
     
    2915#include <libcpu/io.h>
    3016#include <rtems/score/targopts.h>
     17#include <rtems/score/cpu.h>
    3118#include "asm.h"
    32        
     19
    3320#define SYNC \
    3421        sync; \
     
    9279         * stack = &__rtems_end + 4096
    9380         */
    94         addis   r9,r0, __rtems_end+4096@ha
    95         addi    r9,r9, __rtems_end+4096@l
     81        addis   r9,r0, __rtems_end+(4096-CPU_MINIMUM_STACK_FRAME_SIZE)@ha
     82        addi    r9,r9, __rtems_end+(4096-CPU_MINIMUM_STACK_FRAME_SIZE)@l
    9683        mr      r1, r9
    9784        bl      zero_bss
     
    143130        mtctr   r30
    144131        bctr   
    145        
    146        
    147 
    148 
    149 
  • c/src/lib/libbsp/powerpc/mcp750/startup/bspstart.c

    r908436c1 r981b99f  
    132132    heap_size = (BSP_mem_size - heap_start) - BSP_Configuration.work_space_size;
    133133
     134#ifdef SHOW_MORE_INIT_SETTINGS
    134135    printk(" HEAP start %x  size %x\n", heap_start, heap_size);
     136#endif   
    135137    bsp_libc_init((void *) heap_start, heap_size, 0);
    136138
     
    142144void zero_bss()
    143145{
    144   memset(&__bss_start, 0, &__rtems_end - &__bss_start);
     146  memset(&__bss_start, 0, ((unsigned) (&__rtems_end)) - ((unsigned) &__bss_start));
    145147}
    146148
     
    185187   * so there is no need to set it in r1 again...
    186188   */
    187   stack = ((unsigned char*) &__rtems_end) + INIT_STACK_SIZE;
     189  stack = ((unsigned char*) &__rtems_end) + INIT_STACK_SIZE - CPU_MINIMUM_STACK_FRAME_SIZE;
    188190  /*
    189191   * Initialize the interrupt related settings
     
    194196   * some settings below...
    195197   */
    196   intrStack = ((unsigned char*) &__rtems_end) + INIT_STACK_SIZE + INTR_STACK_SIZE;
     198  intrStack = ((unsigned char*) &__rtems_end) + INIT_STACK_SIZE + INTR_STACK_SIZE - CPU_MINIMUM_STACK_FRAME_SIZE;
    197199  asm volatile ("mtspr  273, %0" : "=r" (intrStack) : "0" (intrStack));
    198200  asm volatile ("mtspr  272, %0" : "=r" (intrNestingLevel) : "0" (intrNestingLevel));
     
    287289  Cpu_table.exceptions_in_RAM           = TRUE;
    288290
     291#ifdef SHOW_MORE_INIT_SETTINGS
    289292  printk("BSP_Configuration.work_space_size = %x\n", BSP_Configuration.work_space_size);
     293#endif 
    290294  work_space_start =
    291295    (unsigned char *)BSP_mem_size - BSP_Configuration.work_space_size;
     
    307311   */
    308312  BSP_rtems_irq_mng_init(0);
     313#ifdef SHOW_MORE_INIT_SETTINGS
    309314  printk("Exit from bspstart\n");
    310 }
     315#endif 
     316}
  • c/src/lib/libbsp/powerpc/mcp750/vectors/vectors.S

    r908436c1 r981b99f  
    8787        mfxer   r28
    8888        stw     r28,  EXC_XER_OFFSET(r1)
     89        /*
     90         * compute SP at exception entry
     91         */
     92        addi    r2, r1, EXCEPTION_FRAME_END
     93        /*
     94         * store it at the right place
     95         */
     96        stw     r2, GPR1_OFFSET(r1)
    8997        /*
    9098         * Enable data and instruction address translation, exception nesting
     
    98106         * Call C exception handler
    99107         */
     108        /*
     109         * store the execption frame address in r3 (first param)
     110         */
    100111        addi    r3, r1, 0x8
    101         bl C_exception_handler
     112        /*
     113         * globalExceptHdl(r3)
     114         */
     115        addis   r4, 0, globalExceptHdl@ha
     116        lwz     r5, globalExceptHdl@l(r4)
     117        mtlr    r5
     118        blrl
    102119        /*
    103120         * Restore registers status
     
    136153        SYNC
    137154        rfi
    138 
    139 
    140 
    141 
    142 
  • c/src/lib/libbsp/powerpc/mcp750/vectors/vectors.h

    r908436c1 r981b99f  
    129129  unsigned      EXC_MSR;
    130130  unsigned      EXC_DAR;
    131 } exception_frame;
     131}BSP_Exception_frame;
    132132
    133 extern void C_exception_handler(exception_frame* excPtr);
     133
     134typedef void (*exception_handler_t) (BSP_Exception_frame* excPtr);
     135extern exception_handler_t globalExceptHdl;
     136/*
     137 * Compatibility with pc386
     138 */
     139typedef BSP_Exception_frame CPU_Exception_frame;
     140typedef exception_handler_t cpuExcHandlerType;
    134141
    135142#endif /* ASM */
  • c/src/lib/libbsp/powerpc/mcp750/vectors/vectors_init.c

    r908436c1 r981b99f  
    2020static rtems_raw_except_connect_data    exception_table[LAST_VALID_EXC + 1];
    2121
    22 void C_exception_handler(exception_frame* excPtr)
     22exception_handler_t globalExceptHdl;
     23
     24void C_exception_handler(BSP_Exception_frame* excPtr)
    2325{
    2426  int recoverable = 0;
     
    8284{
    8385  int i;
    84  
    85   exception_config.exceptSize           = LAST_VALID_EXC + 1;
    86   exception_config.rawExceptHdlTbl      = &exception_table[0];
     86
     87  /*
     88   * Initialize pointer used by low level execption handling
     89   */
     90  globalExceptHdl                               = C_exception_handler;
     91  /*
     92   * Put  default_exception_vector_code_prolog at relevant exception
     93   * code entry addresses
     94   */
     95  exception_config.exceptSize                   = LAST_VALID_EXC + 1;
     96  exception_config.rawExceptHdlTbl              = &exception_table[0];
    8797  exception_config.defaultRawEntry.exceptIndex  = 0;
    8898  exception_config.defaultRawEntry.hdl.vector   = 0;
  • c/src/lib/libbsp/powerpc/motorola_powerpc/dec21140/dec21140.c

    r908436c1 r981b99f  
    118118 * Receive buffer size -- Allow for a full ethernet packet including CRC
    119119 */
    120 #define RBUF_SIZE       1520
     120#define RBUF_SIZE       1536
    121121
    122122#define ET_MINLEN 60            /* minimum message length */
     
    420420  cp = (char *)malloc((NRXBUFS+NTXBUFS)*(sizeof(struct MD)+ RBUF_SIZE) + PPC_CACHE_ALIGNMENT);
    421421  sc->bufferBase = cp;
    422   cp += (PPC_CACHE_ALIGNMENT - (int)cp) & MASK_OFFSET;
     422  if ((unsigned int)cp & (PPC_CACHE_ALIGNMENT-1))
     423    cp = ((unsigned int)cp + PPC_CACHE_ALIGNMENT) & ~(PPC_CACHE_ALIGNMENT-1);
    423424#ifdef PCI_BRIDGE_DOES_NOT_ENSURE_CACHE_COHERENCY_FOR_DMA
    424425  if (_CPU_is_paging_enabled())
  • c/src/lib/libbsp/powerpc/motorola_powerpc/include/bsp.h

    r908436c1 r981b99f  
    1717#include <libcpu/io.h>
    1818#include <clockdrv.h>
     19#include <bsp/vectors.h>
    1920
    2021#ifndef ASM
  • c/src/lib/libbsp/powerpc/motorola_powerpc/irq/i8259.c

    r908436c1 r981b99f  
    2222 * lower byte is interrupt mask on the master PIC.
    2323 * while upper bits are interrupt on the slave PIC.
    24  * This cache is initialized in ldseg.s
    2524 */
    26 volatile rtems_i8259_masks i8259s_cache;
     25volatile rtems_i8259_masks i8259s_cache = 0xfffb;
    2726
    2827/*-------------------------------------------------------------------------+
     
    5453  else
    5554  {
    56     outport_byte(PIC_SLAVE_IMR_IO_PORT, ((i8259s_cache & 0xff00) > 8));
     55    outport_byte(PIC_SLAVE_IMR_IO_PORT, ((i8259s_cache & 0xff00) >> 8));
    5756  }
    5857  _CPU_ISR_Enable (level);
     
    8988  else
    9089  {
    91     outport_byte(PIC_SLAVE_IMR_IO_PORT, ((i8259s_cache & 0xff00) > 8));
     90    outport_byte(PIC_SLAVE_IMR_IO_PORT, ((i8259s_cache & 0xff00) >> 8));
    9291  }
    9392  _CPU_ISR_Enable (level);
     
    120119{
    121120  if (irqLine >= 8) {
    122    outport_byte(PIC_SLAVE_COMMAND_IO_PORT, PIC_EOI);
     121    outport_byte(PIC_MASTER_COMMAND_IO_PORT, SLAVE_PIC_EOSI);
     122    outport_byte(PIC_SLAVE_COMMAND_IO_PORT, (PIC_EOSI | (irqLine - 8)));
    123123  }
    124   outport_byte(PIC_MASTER_COMMAND_IO_PORT, PIC_EOI);
     124  else {
     125    outport_byte(PIC_MASTER_COMMAND_IO_PORT, (PIC_EOSI | irqLine));
     126  }
    125127
    126128  return 0;
     
    147149  outport_byte(PIC_SLAVE_IMR_IO_PORT, 0xFF); /* Mask all */
    148150 
    149   i8259s_cache = 0xFFFB;
    150151}
    151152
  • c/src/lib/libbsp/powerpc/motorola_powerpc/irq/irq.c

    r908436c1 r981b99f  
    379379   
    380380 
    381 void _ThreadProcessSignalsFromIrq (exception_frame* ctx)
     381void _ThreadProcessSignalsFromIrq (BSP_Exception_frame* ctx)
    382382{
    383383  /*
  • c/src/lib/libbsp/powerpc/motorola_powerpc/irq/irq.h

    r908436c1 r981b99f  
    5555    /* Command for specific EOI (End Of Interrupt): Interrupt acknowledge */
    5656#define PIC_EOSI        0x60    /* End of Specific Interrupt (EOSI) */
     57#define SLAVE_PIC_EOSI  0x62    /* End of Specific Interrupt (EOSI) for cascade */
    5758#define PIC_EOI         0x20    /* Generic End of Interrupt (EOI) */
    5859
  • c/src/lib/libbsp/powerpc/motorola_powerpc/irq/irq_asm.S

    r908436c1 r981b99f  
    213213        stmw    r16, GPR16_OFFSET(r1)
    214214        addi    r3, r1, 0x8
     215        /*
     216         * compute SP at exception entry
     217         */
     218        addi    r2, r1, EXCEPTION_FRAME_END
     219        /*
     220         * store it at the right place
     221         */
    215222        bl      _ISR_Signals_to_thread_executing
    216223        /*
  • c/src/lib/libbsp/powerpc/motorola_powerpc/start/start.S

    r908436c1 r981b99f  
    11/*
    2  *  arch/ppc/kernel/head.S
     2 *  start.S :     RTEMS entry point
     3 *
     4 *  Copyright (C) 1999 Eric Valette. valette@crf.canon.fr
     5 *
     6 *  The license and distribution terms for this file may be
     7 *  found in found in the file LICENSE in this distribution or at
     8 *  http://www.OARcorp.com/rtems/license.html.
    39 *
    410 *  $Id$
    511 *
    6  *  PowerPC version
    7  *    Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
    8  *
    9  *  Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
    10  *  Adapted for Power Macintosh by Paul Mackerras.
    11  *  Low-level exception handlers and MMU support
    12  *  rewritten by Paul Mackerras.
    13  *    Copyright (C) 1996 Paul Mackerras.
    14  *  MPC8xx modifications Copyright (C) 1997 Dan Malek (dmalek@jlc.net).
    15  *  Amiga/APUS changes by Jesper Skov (jskov@cygnus.co.uk).
    16  *
    17  *  This file contains the low-level support and setup for the
    18  *  PowerPC platform, including trap and interrupt dispatch.
    19  *  Also included here is low-level thread/task switch support.
    20  *
    21  *  This program is free software; you can redistribute it and/or
    22  *  modify it under the terms of the GNU General Public License
    23  *  as published by the Free Software Foundation; either version
    24  *  2 of the License, or (at your option) any later version.
    25  *     
    2612 */
    2713
     
    2915#include <libcpu/io.h>
    3016#include <rtems/score/targopts.h>
     17#include <rtems/score/cpu.h>
    3118#include "asm.h"
    32        
     19
    3320#define SYNC \
    3421        sync; \
     
    9279         * stack = &__rtems_end + 4096
    9380         */
    94         addis   r9,r0, __rtems_end+4096@ha
    95         addi    r9,r9, __rtems_end+4096@l
     81        addis   r9,r0, __rtems_end+(4096-CPU_MINIMUM_STACK_FRAME_SIZE)@ha
     82        addi    r9,r9, __rtems_end+(4096-CPU_MINIMUM_STACK_FRAME_SIZE)@l
    9683        mr      r1, r9
    9784        bl      zero_bss
     
    143130        mtctr   r30
    144131        bctr   
    145        
    146        
    147 
    148 
    149 
  • c/src/lib/libbsp/powerpc/motorola_powerpc/startup/bspstart.c

    r908436c1 r981b99f  
    132132    heap_size = (BSP_mem_size - heap_start) - BSP_Configuration.work_space_size;
    133133
     134#ifdef SHOW_MORE_INIT_SETTINGS
    134135    printk(" HEAP start %x  size %x\n", heap_start, heap_size);
     136#endif   
    135137    bsp_libc_init((void *) heap_start, heap_size, 0);
    136138
     
    142144void zero_bss()
    143145{
    144   memset(&__bss_start, 0, &__rtems_end - &__bss_start);
     146  memset(&__bss_start, 0, ((unsigned) (&__rtems_end)) - ((unsigned) &__bss_start));
    145147}
    146148
     
    185187   * so there is no need to set it in r1 again...
    186188   */
    187   stack = ((unsigned char*) &__rtems_end) + INIT_STACK_SIZE;
     189  stack = ((unsigned char*) &__rtems_end) + INIT_STACK_SIZE - CPU_MINIMUM_STACK_FRAME_SIZE;
    188190  /*
    189191   * Initialize the interrupt related settings
     
    194196   * some settings below...
    195197   */
    196   intrStack = ((unsigned char*) &__rtems_end) + INIT_STACK_SIZE + INTR_STACK_SIZE;
     198  intrStack = ((unsigned char*) &__rtems_end) + INIT_STACK_SIZE + INTR_STACK_SIZE - CPU_MINIMUM_STACK_FRAME_SIZE;
    197199  asm volatile ("mtspr  273, %0" : "=r" (intrStack) : "0" (intrStack));
    198200  asm volatile ("mtspr  272, %0" : "=r" (intrNestingLevel) : "0" (intrNestingLevel));
     
    287289  Cpu_table.exceptions_in_RAM           = TRUE;
    288290
     291#ifdef SHOW_MORE_INIT_SETTINGS
    289292  printk("BSP_Configuration.work_space_size = %x\n", BSP_Configuration.work_space_size);
     293#endif 
    290294  work_space_start =
    291295    (unsigned char *)BSP_mem_size - BSP_Configuration.work_space_size;
     
    307311   */
    308312  BSP_rtems_irq_mng_init(0);
     313#ifdef SHOW_MORE_INIT_SETTINGS
    309314  printk("Exit from bspstart\n");
    310 }
     315#endif 
     316}
  • c/src/lib/libbsp/powerpc/motorola_powerpc/vectors/vectors.S

    r908436c1 r981b99f  
    8787        mfxer   r28
    8888        stw     r28,  EXC_XER_OFFSET(r1)
     89        /*
     90         * compute SP at exception entry
     91         */
     92        addi    r2, r1, EXCEPTION_FRAME_END
     93        /*
     94         * store it at the right place
     95         */
     96        stw     r2, GPR1_OFFSET(r1)
    8997        /*
    9098         * Enable data and instruction address translation, exception nesting
     
    98106         * Call C exception handler
    99107         */
     108        /*
     109         * store the execption frame address in r3 (first param)
     110         */
    100111        addi    r3, r1, 0x8
    101         bl C_exception_handler
     112        /*
     113         * globalExceptHdl(r3)
     114         */
     115        addis   r4, 0, globalExceptHdl@ha
     116        lwz     r5, globalExceptHdl@l(r4)
     117        mtlr    r5
     118        blrl
    102119        /*
    103120         * Restore registers status
     
    136153        SYNC
    137154        rfi
    138 
    139 
    140 
    141 
    142 
  • c/src/lib/libbsp/powerpc/motorola_powerpc/vectors/vectors.h

    r908436c1 r981b99f  
    129129  unsigned      EXC_MSR;
    130130  unsigned      EXC_DAR;
    131 } exception_frame;
     131}BSP_Exception_frame;
    132132
    133 extern void C_exception_handler(exception_frame* excPtr);
     133
     134typedef void (*exception_handler_t) (BSP_Exception_frame* excPtr);
     135extern exception_handler_t globalExceptHdl;
     136/*
     137 * Compatibility with pc386
     138 */
     139typedef BSP_Exception_frame CPU_Exception_frame;
     140typedef exception_handler_t cpuExcHandlerType;
    134141
    135142#endif /* ASM */
  • c/src/lib/libbsp/powerpc/motorola_powerpc/vectors/vectors_init.c

    r908436c1 r981b99f  
    2020static rtems_raw_except_connect_data    exception_table[LAST_VALID_EXC + 1];
    2121
    22 void C_exception_handler(exception_frame* excPtr)
     22exception_handler_t globalExceptHdl;
     23
     24void C_exception_handler(BSP_Exception_frame* excPtr)
    2325{
    2426  int recoverable = 0;
     
    8284{
    8385  int i;
    84  
    85   exception_config.exceptSize           = LAST_VALID_EXC + 1;
    86   exception_config.rawExceptHdlTbl      = &exception_table[0];
     86
     87  /*
     88   * Initialize pointer used by low level execption handling
     89   */
     90  globalExceptHdl                               = C_exception_handler;
     91  /*
     92   * Put  default_exception_vector_code_prolog at relevant exception
     93   * code entry addresses
     94   */
     95  exception_config.exceptSize                   = LAST_VALID_EXC + 1;
     96  exception_config.rawExceptHdlTbl              = &exception_table[0];
    8797  exception_config.defaultRawEntry.exceptIndex  = 0;
    8898  exception_config.defaultRawEntry.hdl.vector   = 0;
  • c/src/lib/librdbg/_servtgt.c

    r908436c1 r981b99f  
    11/*
    22 ============================================================================
    3  _SERVTGT
     3 _SERVTGT
     4 $Id$
    45 ============================================================================
    56*/
     
    1819#include <rtems/score/cpu.h>
    1920
    20 extern void rtems_exception_prologue_50();
    21 
    22 
    2321#ifdef DDEBUG
    2422#define Ptrace  TgtDbgPtrace
     
    3533CPU_Exception_frame Idle_frame;
    3634
    37 cpuExcHandlerType old_currentExcHandler;
    38 
    3935/* -----------------------------------------------------------------
    4036   TgtRealPtrace - lowest level ptrace() wrapper
     
    4844
    4945
    50 /* -----------------------------------------------------------------
    51    Maping of hardware exceptions into Unix-like signal numbers.
    52    It is identical to the one used by the PM and the AM.
    53    ----------------------------------------------------------------- */
    54 
    55     int
    56 ExcepToSig (int excep)
    57 {
    58     switch (excep) {
    59      
    60     case I386_EXCEPTION_MATH_COPROC_UNAVAIL:
    61     case I386_EXCEPTION_I386_COPROC_SEG_ERR:
    62     case I386_EXCEPTION_FLOAT_ERROR:
    63     case I386_EXCEPTION_BOUND:
    64         return SIGFPE;
    65 
    66     case I386_EXCEPTION_DEBUG:
    67     case I386_EXCEPTION_BREAKPOINT:
    68     case I386_EXCEPTION_ENTER_RDBG:
    69         return SIGTRAP;
    70 
    71     case I386_EXCEPTION_OVERFLOW:
    72     case I386_EXCEPTION_DIVIDE_BY_ZERO:
    73     case I386_EXCEPTION_ILLEGAL_INSTR: 
    74         return SIGILL;
    75 
    76     case I386_EXCEPTION_SEGMENT_NOT_PRESENT:
    77     case I386_EXCEPTION_STACK_SEGMENT_FAULT:
    78     case I386_EXCEPTION_GENERAL_PROT_ERR:
    79     case I386_EXCEPTION_PAGE_FAULT:
    80         return SIGSEGV;
    81 
    82     default:
    83         break;
    84     }
    85     return SIGKILL;
    86 }
    8746
    8847/* -----------------------------------------------------------------------
     
    12988    CheckForSingleStep(ctx->ctx);
    13089
    131     TgtChange(pid, ctx->ctx,STS_MAKESIG(ExcepToSig(ctx->ctx->idtIndex)));
     90    TgtChange(pid, ctx->ctx,STS_MAKESIG(ExcepToSig(ctx)));
    13291     
    13392  }
     
    163122  rtems_status_code status;
    164123  rtems_id debugId;
    165   interrupt_gate_descriptor      *currentIdtEntry;
    166   unsigned                       limit;
    167   unsigned                       level;
    168124 
    169125  errno = 0;
     
    178134
    179135
    180   /*
    181    *  Connect the Exception used to debug
    182    */
    183   i386_get_info_from_IDTR (&currentIdtEntry, &limit);
    184  
    185   _CPU_ISR_Disable(level);
    186   create_interrupt_gate_descriptor (&currentIdtEntry[50], rtems_exception_prologue_50);
    187   _CPU_ISR_Enable(level);
    188 
    189   old_currentExcHandler = _currentExcHandler;
    190   _currentExcHandler = BreakPointExcHdl ;
    191 
    192 
     136  connect_rdbg_exception();
     137 
    193138  /*
    194139   * Create the attach debuger task
  • c/src/lib/librdbg/awk.svc

    r908436c1 r981b99f  
    88#
    99#########################################################################
    10 
     10#
     11# $Id$
     12#
    1113BEGIN {
    1214    headerstarted = 0
  • c/src/lib/librdbg/i386/excep.c

    r908436c1 r981b99f  
    1 /*
    2  **************************************************************************
    3  *
    4  * Component =   
    5  *
    6  * Synopsis  =   rdbg/i386/excep.c
    7  *
    8  **************************************************************************
    9  */
    10 
    11 #include <rtems.h>
    12 #include <rtems/error.h>
    13 #include <rdbg/rdbg_f.h>
    14 #include <assert.h>
    15 #include <errno.h>
    16 #include <rdbg/rdbg.h>
    17 #include <rdbg/servrpc.h>
    18 
    19 
    20 extern rtems_id serializeSemId;
    21 extern rtems_id wakeupEventSemId;
    22 
    23 
    24 unsigned int NbExceptCtx;
    25 volatile unsigned int NbSerializedCtx;
    26 Exception_context *FirstCtx = NULL;
    27 Exception_context *LastCtx = NULL;
    28 
    29 CPU_Exception_frame SavedContext;
    30 
    31 
    32 /********* Save an exception context at the end of a list *****/
    33 
    34 int PushExceptCtx ( Objects_Id Id, Objects_Id semId, CPU_Exception_frame *ctx ) {
    35 
    36   Exception_context *SaveCtx;
    37 
    38   SaveCtx = (Exception_context *)malloc(sizeof(Exception_context));
    39   if (SaveCtx == NULL)
    40     rtems_panic("Can't allocate memory to save Exception context");
    41  
    42   SaveCtx->id = Id;
    43   SaveCtx->ctx = ctx;
    44   SaveCtx->semaphoreId = semId;
    45   SaveCtx->previous = NULL;
    46   SaveCtx->next = NULL;
    47  
    48   if (FirstCtx == NULL){  /* initialization */
    49     FirstCtx = SaveCtx;
    50     LastCtx  = SaveCtx;
    51     NbExceptCtx = 1;
    52   }
    53   else {
    54     NbExceptCtx ++;
    55     LastCtx->next = SaveCtx;
    56     SaveCtx->previous = LastCtx;
    57     LastCtx = SaveCtx;
    58   }
    59   return 0;
    60 }
    61 
    62 /********* Save an temporary exception context in a ******/
    63 /********* global variable                          ******/
    64 
    65 int PushSavedExceptCtx ( Objects_Id Id, CPU_Exception_frame *ctx ) {
    66 
    67   memcpy (&(SavedContext), ctx, sizeof(CPU_Exception_frame));
    68   return 0;
    69 }
    70 
    71 
    72 /****** Remove the context of the specified Id thread *********/
    73 /****** If Id = -1, then return the first context     *********/
    74 
    75 
    76 int PopExceptCtx ( Objects_Id Id ) {
    77 
    78   Exception_context *ExtractCtx;
    79  
    80   if (FirstCtx == NULL) return -1;
    81  
    82   if  (Id == -1) {
    83     ExtractCtx = LastCtx;
    84     LastCtx = LastCtx->previous;
    85     free(ExtractCtx);
    86     NbExceptCtx --;
    87     return 0;
    88   }
    89  
    90   ExtractCtx = LastCtx;
    91  
    92   while (ExtractCtx->id != Id && ExtractCtx != NULL) {
    93     ExtractCtx = ExtractCtx->previous;
    94   }
    95 
    96   if (ExtractCtx == NULL)
    97     return -1;
    98 
    99   if ( ExtractCtx->previous != NULL)
    100     (ExtractCtx->previous)->next = ExtractCtx->next;
    101 
    102   if ( ExtractCtx->next != NULL)
    103     (ExtractCtx->next)->previous = ExtractCtx->previous;
    104 
    105   if (ExtractCtx == FirstCtx)
    106     FirstCtx = FirstCtx->next;
    107   else
    108   if (ExtractCtx == LastCtx)
    109     LastCtx = LastCtx->previous;
    110  
    111   free(ExtractCtx);
    112   NbExceptCtx --;
    113   return 0;
    114 }
    115  
    116 /****** Return the context of the specified Id thread *********/
    117 /****** If Id = -1, then return the first context     *********/
    118 
    119 
    120 Exception_context *GetExceptCtx ( Objects_Id Id ) {
    121 
    122   Exception_context *ExtractCtx;
    123 
    124   if (FirstCtx == NULL) return NULL;
    125  
    126   if  (Id == -1) {
    127     return LastCtx;
    128   }
    129  
    130   ExtractCtx = LastCtx;
    131 
    132   while (ExtractCtx->id != Id && ExtractCtx != NULL) {
    133     ExtractCtx = ExtractCtx->previous;
    134   }
    135 
    136   if (ExtractCtx == NULL)
    137     return NULL;
    138 
    139   return ExtractCtx;
    140 }
    141  
    142 /*----- Breakpoint Exception management -----*/
    143 
    144     /*
    145      *  Handler for Breakpoint Exceptions :
    146      *  software breakpoints.
    147      */
    148 
    149 void
    150 BreakPointExcHdl(CPU_Exception_frame *ctx)
    151 {
    152   rtems_status_code status;
    153   rtems_id continueSemId;
    154 
    155   if ( (justSaveContext) && (ctx->idtIndex == I386_EXCEPTION_ENTER_RDBG) ) {
    156     PushSavedExceptCtx (_Thread_Executing->Object.id, ctx);
    157     justSaveContext = 0;
    158   }
    159   else {
    160     if (ctx->idtIndex != I386_EXCEPTION_DEBUG){
    161       NbSerializedCtx++;
    162       rtems_semaphore_obtain(serializeSemId, RTEMS_WAIT, RTEMS_NO_TIMEOUT);
    163       NbSerializedCtx--;
    164     }
    165      
    166     currentTargetThread = _Thread_Executing->Object.id;
    167 
    168 #ifdef DDEBUG
    169     printk("----------------------------------------------------------\n");
    170     printk("Exception %d caught at PC %x by thread %d\n",
    171            ctx->idtIndex,
    172            ctx->eip,
    173            _Thread_Executing->Object.id);
    174     printk("----------------------------------------------------------\n");
    175     printk("Processor execution context at time of the fault was  :\n");
    176     printk("----------------------------------------------------------\n");
    177     printk(" EAX = %x   EBX = %x        ECX = %x        EDX = %x\n",
    178            ctx->eax, ctx->ebx, ctx->ecx, ctx->edx);
    179     printk(" ESI = %x   EDI = %x        EBP = %x        ESP = %x\n",
    180            ctx->esi, ctx->edi, ctx->ebp, ctx->esp0);
    181     printk("----------------------------------------------------------\n");
    182     printk("Error code pushed by processor itself (if not 0) = %x\n",
    183            ctx->faultCode);
    184     printk("----------------------------------------------------------\n\n");
    185 #endif
    186 
    187     status = rtems_semaphore_create (rtems_build_name('D', 'B', 'G', 'c'),
    188                                      0,
    189                                      RTEMS_FIFO |
    190                                      RTEMS_COUNTING_SEMAPHORE |
    191                                      RTEMS_NO_INHERIT_PRIORITY |
    192                                      RTEMS_NO_PRIORITY_CEILING |
    193                                      RTEMS_LOCAL,
    194                                      0,
    195                                      &continueSemId);
    196     if (status != RTEMS_SUCCESSFUL)
    197       rtems_panic ("Can't create continue semaphore: `%s'\n",rtems_status_text(status));
    198 
    199     PushExceptCtx (_Thread_Executing->Object.id, continueSemId, ctx);
    200  
    201     switch (ctx->idtIndex){
    202     case I386_EXCEPTION_DEBUG:
    203       DPRINTF((" DEBUG EXCEPTION !!!\n"));
    204       ctx->eflags &= ~EFLAGS_TF;
    205       ExitForSingleStep-- ;
    206       rtems_semaphore_release( wakeupEventSemId );
    207     break;
    208 
    209     case I386_EXCEPTION_BREAKPOINT:
    210       DPRINTF((" BREAKPOINT EXCEPTION !!!\n"));
    211       rtems_semaphore_release( wakeupEventSemId );
    212     break;
    213 
    214     case I386_EXCEPTION_ENTER_RDBG:
    215       DPRINTF((" ENTER RDBG !!!\n"));
    216       rtems_semaphore_release( wakeupEventSemId );
    217       break;
    218 
    219     default:
    220       DPRINTF((" OTHER EXCEPTION !!!\n"));
    221       rtems_semaphore_release( wakeupEventSemId );
    222       break;
    223     }
    224 
    225     rtems_semaphore_obtain(continueSemId, RTEMS_WAIT, RTEMS_NO_TIMEOUT);
    226    
    227     PopExceptCtx (_Thread_Executing->Object.id);
    228     rtems_semaphore_delete(continueSemId);
    229   }
    230 }
    231 
    232 
    233 
  • c/src/lib/librdbg/i386/pc386/Makefile.in

    r908436c1 r981b99f  
    1818
    1919# C and C++ source names, if any, go here -- minus the .c or .cc
    20 C_PIECES = rdbg servcon servbkpt servrpc excep servtgt servtsp servutil \
    21     _servtgt rdbg_f ptrace
     20C_PIECES = rdbg servcon servbkpt servrpc excep excep_f \
     21        servtgt servtsp servutil _servtgt rdbg_f \
     22        ptrace
     23 
    2224C_FILES = $(C_PIECES:%=%.c)
    2325C_O_FILES = $(C_PIECES:%=${ARCH}/%.o)
  • c/src/lib/librdbg/i386/pc386/remdeb_f.x

    r908436c1 r981b99f  
    66 * Synopsis  =   remdeb_f.x
    77 *
     8 * $Id$
    89 *
    910 **************************************************************************
  • c/src/lib/librdbg/i386/rdbg_cpu_asm.S

    r908436c1 r981b99f  
    33 *  This file contains all assembly code for the Intel i386 implementation
    44 *  of RDBG.
     5 *
     6 * $Id$
    57 *
    68 */
     
    1113
    1214/*
    13  *  void copyback_data_cache_and_invalidate_instr_cache()
     15 *  void copyback_data_cache_and_invalidate_instr_cache(addr, size)
    1416 *
    1517 *  This routine performs a copy of the data cache
  • c/src/lib/librdbg/i386/rdbg_f.c

    r908436c1 r981b99f  
    55 *
    66 * Synopsis  =   rdbg/i386/rdbg_f.c
     7 *
     8 * $Id$
    79 *
    810 **************************************************************************
     
    129131    ExitForSingleStep-- ;
    130132}
     133
     134cpuExcHandlerType old_currentExcHandler;
     135extern void  rtems_exception_prologue_50();
     136
     137void connect_rdbg_exception()
     138{
     139  interrupt_gate_descriptor      *currentIdtEntry;
     140  unsigned                       limit;
     141  unsigned                       level;
     142
     143  /*
     144   *  Connect the Exception used to debug
     145   */
     146  i386_get_info_from_IDTR (&currentIdtEntry, &limit);
     147 
     148  _CPU_ISR_Disable(level);
     149  create_interrupt_gate_descriptor (&currentIdtEntry[50], rtems_exception_prologue_50);
     150  _CPU_ISR_Enable(level);
     151
     152  old_currentExcHandler = _currentExcHandler;
     153  _currentExcHandler = BreakPointExcHdl ;
     154
     155}
  • c/src/lib/librdbg/ptrace.c

    r908436c1 r981b99f  
    55 *
    66 * Synopsis  =   rkdb/rkdb.c
     7 *
     8 * $Id$
    79 *
    810 **************************************************************************
     
    143145     
    144146     if (diag == 0) {
    145        copyback_data_cache_and_invalidate_instr_cache();
     147       copyback_data_cache_and_invalidate_instr_cache(addr, sizeof data);
    146148       return 0;
    147149     }
     
    163165     ctx = GetExceptCtx (currentTargetThread);
    164166
    165      if (
    166          ctx->ctx->idtIndex != I386_EXCEPTION_DEBUG &&
    167          ctx->ctx->idtIndex != I386_EXCEPTION_BREAKPOINT &&
    168          ctx->ctx->idtIndex != I386_EXCEPTION_ENTER_RDBG
    169          ) {
     167     if (!isRdbgException(ctx)) {
    170168       CannotRestart = 1;
    171169       setErrno (EIO);
  • c/src/lib/librdbg/rdbg.c

    r908436c1 r981b99f  
    55 *
    66 * Synopsis  =   rkdb/rkdb.c
     7 *
     8 * $Id$
    79 *
    810 **************************************************************************
  • c/src/lib/librdbg/remdeb.x

    r908436c1 r981b99f  
    77 *  Synopsis:   XDR definitions for remote debug server RPC calls.
    88 *              XDR definitions for RPCGEN to build remote debug server.
     9 *
     10 * $Id$
    911 *
    1012 **********************************************************************
  • c/src/lib/librdbg/servbkpt.c

    r908436c1 r981b99f  
    66 *
    77 *  Synopsis:   Management of breakpoints
     8 *
     9 * $Id$
    810 *
    911 **********************************************************************
  • c/src/lib/librdbg/servcon.c

    r908436c1 r981b99f  
    66 *
    77 *  Synopsis:   Management of RPC client connections.
     8 *
     9 * $Id$
    810 *
    911 **************************************************************************
  • c/src/lib/librdbg/servrpc.c

    r908436c1 r981b99f  
    77 *  Synopsis:   support routines for RPC dispatch for remote debug server.
    88 *              Main server dispatch routines from RPC to support remote debug.
     9 *
     10 * $Id$
    911 *
    1012 **********************************************************************
  • c/src/lib/librdbg/servtgt.c

    r908436c1 r981b99f  
    44 *  Component:  RDB servers
    55 *  Module:     servtgt.c
     6 *
     7 * $Id$
    68 *
    79 **************************************************************************
  • c/src/lib/librdbg/servtsp.c

    r908436c1 r981b99f  
    66 *
    77 *  Synopsis:   Transport management for remote debug server.
     8 *
     9 * $Id$
    810 *
    911 **************************************************************************
  • c/src/lib/librdbg/servutil.c

    r908436c1 r981b99f  
    66 *
    77 *  Synopsis:   Various utility routines
     8 *
     9 * $Id$
    810 *
    911 **********************************************************************
  • c/src/librdbg/include/rdbg/i386/rdbg_f.h

    r908436c1 r981b99f  
    66 *
    77 * Synopsis = Machine-dependent header file
     8 *
     9 * $Id$
    810 *
    911 **************************************************************************
     
    1820#define EFLAGS_TF 0x00100
    1921
    20 typedef struct Exception_context_struct {
    21   struct Exception_context_struct *next;
    22   struct Exception_context_struct *previous;
    23   Objects_Id id;
    24   Objects_Id semaphoreId;
    25   CPU_Exception_frame *ctx;
    26 } Exception_context;
     22static inline int isRdbgException(Exception_context *ctx)
     23{
     24  if (
     25      ctx->ctx->idtIndex != I386_EXCEPTION_DEBUG &&
     26      ctx->ctx->idtIndex != I386_EXCEPTION_BREAKPOINT &&
     27      ctx->ctx->idtIndex != I386_EXCEPTION_ENTER_RDBG
     28      ) return 0;
     29  else return 1;
     30}
     31static inline int getExcNum(Exception_context *ctx)
     32{
     33  return ctx->ctx->idtIndex;
     34}
    2735
    28 extern int      PushExceptCtx           (Objects_Id Id,
    29                                          Objects_Id semId,
    30                                          CPU_Exception_frame *ctx);
    31 extern int      PopExceptCtx            (Objects_Id Id);
    32 extern Exception_context *GetExceptCtx  (Objects_Id Id);
    33 extern int      Single_Step             (CPU_Exception_frame* ctx);
    34 extern int      CheckForSingleStep      (CPU_Exception_frame* ctx);
    35 extern void     BreakPointExcHdl        (CPU_Exception_frame *ctx);
    36 extern void     CtxToRegs               (const CPU_Exception_frame*,xdr_regs*);
    37 extern void     RegsToCtx               (const xdr_regs*,CPU_Exception_frame*);
    38 
    39 extern void     enterRdbg               ();
    40 extern void     get_ctx_thread          (Thread_Control *thread,
    41                                          CPU_Exception_frame* ctx);
    42 extern void     set_ctx_thread          (Thread_Control *thread,
    43                                          CPU_Exception_frame* ctx);
    44 
    45 void copyback_data_cache_and_invalidate_instr_cache();
    46 
    47 extern int      ExitForSingleStep;
    48 
     36extern void connect_rdbg_exception();
    4937
    5038#endif
  • c/src/librdbg/include/rdbg/i386/reg.h

    r908436c1 r981b99f  
    1 
     1/*
     2 * Registers Offset in frame definition
     3 *
     4 * $Id$
     5 */
    26
    37#define NBREGS  19
  • c/src/librdbg/include/rdbg/rdbg.h

    r908436c1 r981b99f  
    55 *
    66 * Synopsis  =   rdbg.h
     7 *
     8 * $Id$
    79 *
    810 **************************************************************************
     
    1517#include <sys/socket.h>
    1618#include <netinet/in.h>
    17 #include <rdbg/rdbg_f.h>
    1819#include <stdlib.h>             /* For malloc() and free() prototypes */
    1920#include <bsp.h>               
     21#include <rtems.h>
    2022
    2123#define Malloc(size)            malloc (size)
     
    5052int       svcudp_enablecache    (SVCXPRT *transp, u_long size);
    5153
     54typedef struct Exception_context_struct {
     55  struct Exception_context_struct *next;
     56  struct Exception_context_struct *previous;
     57  Objects_Id id;
     58  Objects_Id semaphoreId;
     59  CPU_Exception_frame *ctx;
     60} Exception_context;
     61
     62struct          xdr_regs;
     63
     64extern int      PushExceptCtx           (Objects_Id Id,
     65                                         Objects_Id semId,
     66                                         CPU_Exception_frame *ctx);
     67extern int      PopExceptCtx            (Objects_Id Id);
     68extern Exception_context *GetExceptCtx  (Objects_Id Id);
     69extern int      Single_Step             (CPU_Exception_frame* ctx);
     70extern int      CheckForSingleStep      (CPU_Exception_frame* ctx);
     71extern void     BreakPointExcHdl        (CPU_Exception_frame *ctx);
     72extern void     CtxToRegs               (const CPU_Exception_frame*,struct xdr_regs*);
     73extern void     RegsToCtx               (const struct xdr_regs*,CPU_Exception_frame*);
     74
     75extern void     enterRdbg               ();
     76extern void     get_ctx_thread          (Thread_Control *thread,
     77                                         CPU_Exception_frame* ctx);
     78extern void     set_ctx_thread          (Thread_Control *thread,
     79                                         CPU_Exception_frame* ctx);
     80extern int      PushSavedExceptCtx      ( Objects_Id Id,
     81                                          CPU_Exception_frame *ctx );
     82extern int      ExcepToSig              (Exception_context *ctx);
     83
     84extern int      ExitForSingleStep;
     85
     86extern rtems_id serializeSemId;
     87extern rtems_id wakeupEventSemId;
     88extern volatile unsigned int NbSerializedCtx;
     89
     90void copyback_data_cache_and_invalidate_instr_cache(unsigned char* addr, int size);
     91
     92#include <rdbg/rdbg_f.h>
     93
    5294#endif /* !RDBG_H */
    5395
  • c/src/librdbg/include/rdbg/servrpc.h

    r908436c1 r981b99f  
     1/*
     2 * $Id$
     3 */
    14
    25#ifndef SERVRPC_H
     
    3033extern const char* BmsgNames[]; /* list of BMSG_xxx names */
    3134extern const char* PtraceName(int req);
     35
     36#ifdef i386                     /* low-high machine such as 386 */
     37#define HL_W(w)         (((UINT16)(w)>>8)+((((w)&0xFF)<<8)))
     38#define HL_D(d)         (((UINT32)(d)>>24)+(((d)&0x00FF0000)>>8) \
     39                       +(((d)&0xFF00)<<8)+(((d)&0xFF)<<24))
     40#else
     41#define HL_W(w)         w
     42#define HL_D(d)         d
     43#endif
    3244
    3345# define DPRINTF(a)     (rdb_debug ? printk ("%d >>> ", getId()), printk a : 0)
  • c/src/librdbg/src/_servtgt.c

    r908436c1 r981b99f  
    11/*
    22 ============================================================================
    3  _SERVTGT
     3 _SERVTGT
     4 $Id$
    45 ============================================================================
    56*/
     
    1819#include <rtems/score/cpu.h>
    1920
    20 extern void rtems_exception_prologue_50();
    21 
    22 
    2321#ifdef DDEBUG
    2422#define Ptrace  TgtDbgPtrace
     
    3533CPU_Exception_frame Idle_frame;
    3634
    37 cpuExcHandlerType old_currentExcHandler;
    38 
    3935/* -----------------------------------------------------------------
    4036   TgtRealPtrace - lowest level ptrace() wrapper
     
    4844
    4945
    50 /* -----------------------------------------------------------------
    51    Maping of hardware exceptions into Unix-like signal numbers.
    52    It is identical to the one used by the PM and the AM.
    53    ----------------------------------------------------------------- */
    54 
    55     int
    56 ExcepToSig (int excep)
    57 {
    58     switch (excep) {
    59      
    60     case I386_EXCEPTION_MATH_COPROC_UNAVAIL:
    61     case I386_EXCEPTION_I386_COPROC_SEG_ERR:
    62     case I386_EXCEPTION_FLOAT_ERROR:
    63     case I386_EXCEPTION_BOUND:
    64         return SIGFPE;
    65 
    66     case I386_EXCEPTION_DEBUG:
    67     case I386_EXCEPTION_BREAKPOINT:
    68     case I386_EXCEPTION_ENTER_RDBG:
    69         return SIGTRAP;
    70 
    71     case I386_EXCEPTION_OVERFLOW:
    72     case I386_EXCEPTION_DIVIDE_BY_ZERO:
    73     case I386_EXCEPTION_ILLEGAL_INSTR: 
    74         return SIGILL;
    75 
    76     case I386_EXCEPTION_SEGMENT_NOT_PRESENT:
    77     case I386_EXCEPTION_STACK_SEGMENT_FAULT:
    78     case I386_EXCEPTION_GENERAL_PROT_ERR:
    79     case I386_EXCEPTION_PAGE_FAULT:
    80         return SIGSEGV;
    81 
    82     default:
    83         break;
    84     }
    85     return SIGKILL;
    86 }
    8746
    8847/* -----------------------------------------------------------------------
     
    12988    CheckForSingleStep(ctx->ctx);
    13089
    131     TgtChange(pid, ctx->ctx,STS_MAKESIG(ExcepToSig(ctx->ctx->idtIndex)));
     90    TgtChange(pid, ctx->ctx,STS_MAKESIG(ExcepToSig(ctx)));
    13291     
    13392  }
     
    163122  rtems_status_code status;
    164123  rtems_id debugId;
    165   interrupt_gate_descriptor      *currentIdtEntry;
    166   unsigned                       limit;
    167   unsigned                       level;
    168124 
    169125  errno = 0;
     
    178134
    179135
    180   /*
    181    *  Connect the Exception used to debug
    182    */
    183   i386_get_info_from_IDTR (&currentIdtEntry, &limit);
    184  
    185   _CPU_ISR_Disable(level);
    186   create_interrupt_gate_descriptor (&currentIdtEntry[50], rtems_exception_prologue_50);
    187   _CPU_ISR_Enable(level);
    188 
    189   old_currentExcHandler = _currentExcHandler;
    190   _currentExcHandler = BreakPointExcHdl ;
    191 
    192 
     136  connect_rdbg_exception();
     137 
    193138  /*
    194139   * Create the attach debuger task
  • c/src/librdbg/src/awk.svc

    r908436c1 r981b99f  
    88#
    99#########################################################################
    10 
     10#
     11# $Id$
     12#
    1113BEGIN {
    1214    headerstarted = 0
  • c/src/librdbg/src/i386/any/Makefile.in

    r908436c1 r981b99f  
    1818
    1919# C and C++ source names, if any, go here -- minus the .c or .cc
    20 C_PIECES = rdbg servcon servbkpt servrpc excep servtgt servtsp servutil \
    21     _servtgt rdbg_f ptrace
     20C_PIECES = rdbg servcon servbkpt servrpc excep excep_f \
     21        servtgt servtsp servutil _servtgt rdbg_f \
     22        ptrace
     23 
    2224C_FILES = $(C_PIECES:%=%.c)
    2325C_O_FILES = $(C_PIECES:%=${ARCH}/%.o)
  • c/src/librdbg/src/i386/any/remdeb_f.x

    r908436c1 r981b99f  
    66 * Synopsis  =   remdeb_f.x
    77 *
     8 * $Id$
    89 *
    910 **************************************************************************
  • c/src/librdbg/src/i386/excep.c

    r908436c1 r981b99f  
    1 /*
    2  **************************************************************************
    3  *
    4  * Component =   
    5  *
    6  * Synopsis  =   rdbg/i386/excep.c
    7  *
    8  **************************************************************************
    9  */
    10 
    11 #include <rtems.h>
    12 #include <rtems/error.h>
    13 #include <rdbg/rdbg_f.h>
    14 #include <assert.h>
    15 #include <errno.h>
    16 #include <rdbg/rdbg.h>
    17 #include <rdbg/servrpc.h>
    18 
    19 
    20 extern rtems_id serializeSemId;
    21 extern rtems_id wakeupEventSemId;
    22 
    23 
    24 unsigned int NbExceptCtx;
    25 volatile unsigned int NbSerializedCtx;
    26 Exception_context *FirstCtx = NULL;
    27 Exception_context *LastCtx = NULL;
    28 
    29 CPU_Exception_frame SavedContext;
    30 
    31 
    32 /********* Save an exception context at the end of a list *****/
    33 
    34 int PushExceptCtx ( Objects_Id Id, Objects_Id semId, CPU_Exception_frame *ctx ) {
    35 
    36   Exception_context *SaveCtx;
    37 
    38   SaveCtx = (Exception_context *)malloc(sizeof(Exception_context));
    39   if (SaveCtx == NULL)
    40     rtems_panic("Can't allocate memory to save Exception context");
    41  
    42   SaveCtx->id = Id;
    43   SaveCtx->ctx = ctx;
    44   SaveCtx->semaphoreId = semId;
    45   SaveCtx->previous = NULL;
    46   SaveCtx->next = NULL;
    47  
    48   if (FirstCtx == NULL){  /* initialization */
    49     FirstCtx = SaveCtx;
    50     LastCtx  = SaveCtx;
    51     NbExceptCtx = 1;
    52   }
    53   else {
    54     NbExceptCtx ++;
    55     LastCtx->next = SaveCtx;
    56     SaveCtx->previous = LastCtx;
    57     LastCtx = SaveCtx;
    58   }
    59   return 0;
    60 }
    61 
    62 /********* Save an temporary exception context in a ******/
    63 /********* global variable                          ******/
    64 
    65 int PushSavedExceptCtx ( Objects_Id Id, CPU_Exception_frame *ctx ) {
    66 
    67   memcpy (&(SavedContext), ctx, sizeof(CPU_Exception_frame));
    68   return 0;
    69 }
    70 
    71 
    72 /****** Remove the context of the specified Id thread *********/
    73 /****** If Id = -1, then return the first context     *********/
    74 
    75 
    76 int PopExceptCtx ( Objects_Id Id ) {
    77 
    78   Exception_context *ExtractCtx;
    79  
    80   if (FirstCtx == NULL) return -1;
    81  
    82   if  (Id == -1) {
    83     ExtractCtx = LastCtx;
    84     LastCtx = LastCtx->previous;
    85     free(ExtractCtx);
    86     NbExceptCtx --;
    87     return 0;
    88   }
    89  
    90   ExtractCtx = LastCtx;
    91  
    92   while (ExtractCtx->id != Id && ExtractCtx != NULL) {
    93     ExtractCtx = ExtractCtx->previous;
    94   }
    95 
    96   if (ExtractCtx == NULL)
    97     return -1;
    98 
    99   if ( ExtractCtx->previous != NULL)
    100     (ExtractCtx->previous)->next = ExtractCtx->next;
    101 
    102   if ( ExtractCtx->next != NULL)
    103     (ExtractCtx->next)->previous = ExtractCtx->previous;
    104 
    105   if (ExtractCtx == FirstCtx)
    106     FirstCtx = FirstCtx->next;
    107   else
    108   if (ExtractCtx == LastCtx)
    109     LastCtx = LastCtx->previous;
    110  
    111   free(ExtractCtx);
    112   NbExceptCtx --;
    113   return 0;
    114 }
    115  
    116 /****** Return the context of the specified Id thread *********/
    117 /****** If Id = -1, then return the first context     *********/
    118 
    119 
    120 Exception_context *GetExceptCtx ( Objects_Id Id ) {
    121 
    122   Exception_context *ExtractCtx;
    123 
    124   if (FirstCtx == NULL) return NULL;
    125  
    126   if  (Id == -1) {
    127     return LastCtx;
    128   }
    129  
    130   ExtractCtx = LastCtx;
    131 
    132   while (ExtractCtx->id != Id && ExtractCtx != NULL) {
    133     ExtractCtx = ExtractCtx->previous;
    134   }
    135 
    136   if (ExtractCtx == NULL)
    137     return NULL;
    138 
    139   return ExtractCtx;
    140 }
    141  
    142 /*----- Breakpoint Exception management -----*/
    143 
    144     /*
    145      *  Handler for Breakpoint Exceptions :
    146      *  software breakpoints.
    147      */
    148 
    149 void
    150 BreakPointExcHdl(CPU_Exception_frame *ctx)
    151 {
    152   rtems_status_code status;
    153   rtems_id continueSemId;
    154 
    155   if ( (justSaveContext) && (ctx->idtIndex == I386_EXCEPTION_ENTER_RDBG) ) {
    156     PushSavedExceptCtx (_Thread_Executing->Object.id, ctx);
    157     justSaveContext = 0;
    158   }
    159   else {
    160     if (ctx->idtIndex != I386_EXCEPTION_DEBUG){
    161       NbSerializedCtx++;
    162       rtems_semaphore_obtain(serializeSemId, RTEMS_WAIT, RTEMS_NO_TIMEOUT);
    163       NbSerializedCtx--;
    164     }
    165      
    166     currentTargetThread = _Thread_Executing->Object.id;
    167 
    168 #ifdef DDEBUG
    169     printk("----------------------------------------------------------\n");
    170     printk("Exception %d caught at PC %x by thread %d\n",
    171            ctx->idtIndex,
    172            ctx->eip,
    173            _Thread_Executing->Object.id);
    174     printk("----------------------------------------------------------\n");
    175     printk("Processor execution context at time of the fault was  :\n");
    176     printk("----------------------------------------------------------\n");
    177     printk(" EAX = %x   EBX = %x        ECX = %x        EDX = %x\n",
    178            ctx->eax, ctx->ebx, ctx->ecx, ctx->edx);
    179     printk(" ESI = %x   EDI = %x        EBP = %x        ESP = %x\n",
    180            ctx->esi, ctx->edi, ctx->ebp, ctx->esp0);
    181     printk("----------------------------------------------------------\n");
    182     printk("Error code pushed by processor itself (if not 0) = %x\n",
    183            ctx->faultCode);
    184     printk("----------------------------------------------------------\n\n");
    185 #endif
    186 
    187     status = rtems_semaphore_create (rtems_build_name('D', 'B', 'G', 'c'),
    188                                      0,
    189                                      RTEMS_FIFO |
    190                                      RTEMS_COUNTING_SEMAPHORE |
    191                                      RTEMS_NO_INHERIT_PRIORITY |
    192                                      RTEMS_NO_PRIORITY_CEILING |
    193                                      RTEMS_LOCAL,
    194                                      0,
    195                                      &continueSemId);
    196     if (status != RTEMS_SUCCESSFUL)
    197       rtems_panic ("Can't create continue semaphore: `%s'\n",rtems_status_text(status));
    198 
    199     PushExceptCtx (_Thread_Executing->Object.id, continueSemId, ctx);
    200  
    201     switch (ctx->idtIndex){
    202     case I386_EXCEPTION_DEBUG:
    203       DPRINTF((" DEBUG EXCEPTION !!!\n"));
    204       ctx->eflags &= ~EFLAGS_TF;
    205       ExitForSingleStep-- ;
    206       rtems_semaphore_release( wakeupEventSemId );
    207     break;
    208 
    209     case I386_EXCEPTION_BREAKPOINT:
    210       DPRINTF((" BREAKPOINT EXCEPTION !!!\n"));
    211       rtems_semaphore_release( wakeupEventSemId );
    212     break;
    213 
    214     case I386_EXCEPTION_ENTER_RDBG:
    215       DPRINTF((" ENTER RDBG !!!\n"));
    216       rtems_semaphore_release( wakeupEventSemId );
    217       break;
    218 
    219     default:
    220       DPRINTF((" OTHER EXCEPTION !!!\n"));
    221       rtems_semaphore_release( wakeupEventSemId );
    222       break;
    223     }
    224 
    225     rtems_semaphore_obtain(continueSemId, RTEMS_WAIT, RTEMS_NO_TIMEOUT);
    226    
    227     PopExceptCtx (_Thread_Executing->Object.id);
    228     rtems_semaphore_delete(continueSemId);
    229   }
    230 }
    231 
    232 
    233 
  • c/src/librdbg/src/i386/pc386/Makefile.in

    r908436c1 r981b99f  
    1818
    1919# C and C++ source names, if any, go here -- minus the .c or .cc
    20 C_PIECES = rdbg servcon servbkpt servrpc excep servtgt servtsp servutil \
    21     _servtgt rdbg_f ptrace
     20C_PIECES = rdbg servcon servbkpt servrpc excep excep_f \
     21        servtgt servtsp servutil _servtgt rdbg_f \
     22        ptrace
     23 
    2224C_FILES = $(C_PIECES:%=%.c)
    2325C_O_FILES = $(C_PIECES:%=${ARCH}/%.o)
  • c/src/librdbg/src/i386/pc386/remdeb_f.x

    r908436c1 r981b99f  
    66 * Synopsis  =   remdeb_f.x
    77 *
     8 * $Id$
    89 *
    910 **************************************************************************
  • c/src/librdbg/src/i386/rdbg_cpu_asm.S

    r908436c1 r981b99f  
    33 *  This file contains all assembly code for the Intel i386 implementation
    44 *  of RDBG.
     5 *
     6 * $Id$
    57 *
    68 */
     
    1113
    1214/*
    13  *  void copyback_data_cache_and_invalidate_instr_cache()
     15 *  void copyback_data_cache_and_invalidate_instr_cache(addr, size)
    1416 *
    1517 *  This routine performs a copy of the data cache
  • c/src/librdbg/src/i386/rdbg_f.c

    r908436c1 r981b99f  
    55 *
    66 * Synopsis  =   rdbg/i386/rdbg_f.c
     7 *
     8 * $Id$
    79 *
    810 **************************************************************************
     
    129131    ExitForSingleStep-- ;
    130132}
     133
     134cpuExcHandlerType old_currentExcHandler;
     135extern void  rtems_exception_prologue_50();
     136
     137void connect_rdbg_exception()
     138{
     139  interrupt_gate_descriptor      *currentIdtEntry;
     140  unsigned                       limit;
     141  unsigned                       level;
     142
     143  /*
     144   *  Connect the Exception used to debug
     145   */
     146  i386_get_info_from_IDTR (&currentIdtEntry, &limit);
     147 
     148  _CPU_ISR_Disable(level);
     149  create_interrupt_gate_descriptor (&currentIdtEntry[50], rtems_exception_prologue_50);
     150  _CPU_ISR_Enable(level);
     151
     152  old_currentExcHandler = _currentExcHandler;
     153  _currentExcHandler = BreakPointExcHdl ;
     154
     155}
  • c/src/librdbg/src/ptrace.c

    r908436c1 r981b99f  
    55 *
    66 * Synopsis  =   rkdb/rkdb.c
     7 *
     8 * $Id$
    79 *
    810 **************************************************************************
     
    143145     
    144146     if (diag == 0) {
    145        copyback_data_cache_and_invalidate_instr_cache();
     147       copyback_data_cache_and_invalidate_instr_cache(addr, sizeof data);
    146148       return 0;
    147149     }
     
    163165     ctx = GetExceptCtx (currentTargetThread);
    164166
    165      if (
    166          ctx->ctx->idtIndex != I386_EXCEPTION_DEBUG &&
    167          ctx->ctx->idtIndex != I386_EXCEPTION_BREAKPOINT &&
    168          ctx->ctx->idtIndex != I386_EXCEPTION_ENTER_RDBG
    169          ) {
     167     if (!isRdbgException(ctx)) {
    170168       CannotRestart = 1;
    171169       setErrno (EIO);
  • c/src/librdbg/src/rdbg.c

    r908436c1 r981b99f  
    55 *
    66 * Synopsis  =   rkdb/rkdb.c
     7 *
     8 * $Id$
    79 *
    810 **************************************************************************
  • c/src/librdbg/src/remdeb.x

    r908436c1 r981b99f  
    77 *  Synopsis:   XDR definitions for remote debug server RPC calls.
    88 *              XDR definitions for RPCGEN to build remote debug server.
     9 *
     10 * $Id$
    911 *
    1012 **********************************************************************
  • c/src/librdbg/src/servbkpt.c

    r908436c1 r981b99f  
    66 *
    77 *  Synopsis:   Management of breakpoints
     8 *
     9 * $Id$
    810 *
    911 **********************************************************************
  • c/src/librdbg/src/servcon.c

    r908436c1 r981b99f  
    66 *
    77 *  Synopsis:   Management of RPC client connections.
     8 *
     9 * $Id$
    810 *
    911 **************************************************************************
  • c/src/librdbg/src/servrpc.c

    r908436c1 r981b99f  
    77 *  Synopsis:   support routines for RPC dispatch for remote debug server.
    88 *              Main server dispatch routines from RPC to support remote debug.
     9 *
     10 * $Id$
    911 *
    1012 **********************************************************************
  • c/src/librdbg/src/servtgt.c

    r908436c1 r981b99f  
    44 *  Component:  RDB servers
    55 *  Module:     servtgt.c
     6 *
     7 * $Id$
    68 *
    79 **************************************************************************
  • c/src/librdbg/src/servtsp.c

    r908436c1 r981b99f  
    66 *
    77 *  Synopsis:   Transport management for remote debug server.
     8 *
     9 * $Id$
    810 *
    911 **************************************************************************
  • c/src/librdbg/src/servutil.c

    r908436c1 r981b99f  
    66 *
    77 *  Synopsis:   Various utility routines
     8 *
     9 * $Id$
    810 *
    911 **********************************************************************
  • make/custom/mcp750.cfg

    r908436c1 r981b99f  
    105105        $(NM) -g -n $(basename $@).exe > $(basename $@).num
    106106        $(SIZE) $(basename $@).exe
    107         $(CP) $(basename $@).exe $(PROJECT_ROOT)/c/src/lib/libbsp/powerpc/mcp750/bootloader/$(ARCH); \
    108         cd $(PROJECT_ROOT)/c/src/lib/libbsp/powerpc/mcp750/bootloader; \
     107        $(CP) $(basename $@).exe $(PROJECT_ROOT)/powerpc-rtems/c/mcp750/lib/libbsp/powerpc/mcp750/bootloader/$(ARCH); \
     108        cd $(PROJECT_ROOT)/powerpc-rtems/c/mcp750/lib/libbsp/powerpc/mcp750/bootloader; \
    109109        make bootloader BINARY_LOADED=$(basename $@).exe; \
    110110        COMPLETE_FILE_NAME=$(basename $@).exe ;\
     
    112112        FILE_NAME=`basename $${COMPLETE_FILE_NAME}` ;\
    113113        echo $${FILE_NAME} ;\
     114        mkdir -p $(PROJECT_ROOT)/$(RTEMS_BSP)/bin ;\
    114115        $(CP) bootloader $(PROJECT_ROOT)/$(RTEMS_BSP)/bin/$${FILE_NAME}
    115116endef
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