Changeset 97cf623d in rtems


Ignore:
Timestamp:
Feb 5, 2014, 10:36:05 AM (5 years ago)
Author:
Sebastian Huber <sebastian.huber@…>
Branches:
4.11, master
Children:
bab16de2
Parents:
62c5c4a5
git-author:
Sebastian Huber <sebastian.huber@…> (02/05/14 10:36:05)
git-committer:
Sebastian Huber <sebastian.huber@…> (02/12/14 08:18:00)
Message:

sparc: Save/restore only non-volatile context

The _CPU_Context_switch() is a normal function call. The following
registers are volatile (the caller must assume that the register
contents are destroyed by the callee) according to "SYSTEM V APPLICATION
BINARY INTERFACE - SPARC Processor Supplement", Third Edition: g1, o0,
o1, o2, o3, o4, o5. Drop these registers from the context.

Ensure that offset defines match the structure offsets.

Files:
3 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/sparc/shared/irq_asm.S

    r62c5c4a5 r97cf623d  
    5353        PUBLIC(_CPU_Context_switch)
    5454SYM(_CPU_Context_switch):
    55         ! skip g0
    56         st      %g1, [%o0 + G1_OFFSET]       ! save the global registers
    57         std     %g2, [%o0 + G2_OFFSET]
     55        std     %g2, [%o0 + G2_OFFSET]       ! save the global registers
    5856        std     %g4, [%o0 + G4_OFFSET]
    5957        std     %g6, [%o0 + G6_OFFSET]
     
    6967        std     %i6, [%o0 + I6_FP_OFFSET]
    7068
    71         std     %o0, [%o0 + O0_OFFSET]       ! save the output registers
    72         std     %o2, [%o0 + O2_OFFSET]
    73         std     %o4, [%o0 + O4_OFFSET]
    74         std     %o6, [%o0 + O6_SP_OFFSET]
     69        std     %o6, [%o0 + O6_SP_OFFSET]    ! save the output registers
    7570
    7671        ! o3 = self per-CPU control
     
    191186        nop
    192187
    193         ! skip g0
    194         ld      [%o1 + G1_OFFSET], %g1        ! restore the global registers
    195         ldd     [%o1 + G2_OFFSET], %g2
     188        ldd     [%o1 + G2_OFFSET], %g2        ! restore the global registers
    196189        ldd     [%o1 + G4_OFFSET], %g4
    197190        ldd     [%o1 + G6_OFFSET], %g6
     
    214207        ldd     [%o1 + I6_FP_OFFSET], %i6
    215208
    216         ldd     [%o1 + O2_OFFSET], %o2        ! restore the output registers
    217         ldd     [%o1 + O4_OFFSET], %o4
    218         ldd     [%o1 + O6_SP_OFFSET], %o6
    219         ! do o0/o1 last to avoid destroying heir context pointer
    220         ldd     [%o1 + O0_OFFSET], %o0        ! overwrite heir pointer
     209        ldd     [%o1 + O6_SP_OFFSET], %o6     ! restore the output registers
    221210
    222211        jmp     %o7 + 8                       ! return
  • cpukit/score/cpu/sparc/cpu.c

    r62c5c4a5 r97cf623d  
    2828    == SPARC_PER_CPU_ISR_DISPATCH_DISABLE,
    2929  SPARC_PER_CPU_ISR_DISPATCH_DISABLE
     30);
     31
     32#define SPARC_ASSERT_OFFSET(field, off) \
     33  RTEMS_STATIC_ASSERT( \
     34    offsetof(Context_Control, field) == off ## _OFFSET, \
     35    Context_Control_offset_ ## field \
     36  )
     37
     38SPARC_ASSERT_OFFSET(g2_g3, G2);
     39SPARC_ASSERT_OFFSET(g4, G4);
     40SPARC_ASSERT_OFFSET(g5, G5);
     41SPARC_ASSERT_OFFSET(g6, G6);
     42SPARC_ASSERT_OFFSET(g7, G7);
     43SPARC_ASSERT_OFFSET(l0, L0);
     44SPARC_ASSERT_OFFSET(l1, L1);
     45SPARC_ASSERT_OFFSET(l2, L2);
     46SPARC_ASSERT_OFFSET(l3, L3);
     47SPARC_ASSERT_OFFSET(l4, L4);
     48SPARC_ASSERT_OFFSET(l5, L5);
     49SPARC_ASSERT_OFFSET(l6, L6);
     50SPARC_ASSERT_OFFSET(l7, L7);
     51SPARC_ASSERT_OFFSET(i0, I0);
     52SPARC_ASSERT_OFFSET(i1, I1);
     53SPARC_ASSERT_OFFSET(i2, I2);
     54SPARC_ASSERT_OFFSET(i3, I3);
     55SPARC_ASSERT_OFFSET(i4, I4);
     56SPARC_ASSERT_OFFSET(i5, I5);
     57SPARC_ASSERT_OFFSET(i6_fp, I6_FP);
     58SPARC_ASSERT_OFFSET(i7, I7);
     59SPARC_ASSERT_OFFSET(o6_sp, O6_SP);
     60SPARC_ASSERT_OFFSET(o7, O7);
     61SPARC_ASSERT_OFFSET(psr, PSR);
     62SPARC_ASSERT_OFFSET(isr_dispatch_disable, ISR_DISPATCH_DISABLE_STACK);
     63
     64RTEMS_STATIC_ASSERT(
     65  (offsetof(Context_Control, g2_g3)
     66     + offsetof(Context_Control, g4)) / 2 == G3_OFFSET,
     67  Context_Control_offset_G3
    3068);
    3169
  • cpukit/score/cpu/sparc/rtems/score/cpu.h

    r62c5c4a5 r97cf623d  
    402402 * @brief SPARC basic context.
    403403 *
    404  * This structure defines the basic integer and processor state context
    405  * for the SPARC architecture.
     404 * This structure defines the non-volatile integer and processor state context
     405 * for the SPARC architecture according to "SYSTEM V APPLICATION BINARY
     406 * INTERFACE - SPARC Processor Supplement", Third Edition.
    406407 */
    407408typedef struct {
    408409  /**
    409    * Using a double g0_g1 will put everything in this structure on a
     410   * Using a double g2_g3 will put everything in this structure on a
    410411   * double word boundary which allows us to use double word loads
    411412   * and stores safely in the context switch.
    412413   */
    413   double     g0_g1;
    414   /** This will contain the contents of the g2 register. */
    415   uint32_t   g2;
    416   /** This will contain the contents of the g3 register. */
    417   uint32_t   g3;
     414  double     g2_g3;
    418415  /** This will contain the contents of the g4 register. */
    419416  uint32_t   g4;
     
    459456  uint32_t   i7;
    460457
    461   /** This will contain the contents of the o0 register. */
    462   uint32_t   o0;
    463   /** This will contain the contents of the o1 register. */
    464   uint32_t   o1;
    465   /** This will contain the contents of the o2 register. */
    466   uint32_t   o2;
    467   /** This will contain the contents of the o3 register. */
    468   uint32_t   o3;
    469   /** This will contain the contents of the o4 register. */
    470   uint32_t   o4;
    471   /** This will contain the contents of the o5 register. */
    472   uint32_t   o5;
    473458  /** This will contain the contents of the o6 (e.g. frame pointer) register. */
    474459  uint32_t   o6_sp;
    475   /** This will contain the contents of the o7 register. */
     460  /**
     461   * This will contain the contents of the o7 (e.g. address of CALL
     462   * instruction) register.
     463   */
    476464  uint32_t   o7;
    477465
     
    501489
    502490/** This macro defines an offset into the context for use in assembly. */
    503 #define G0_OFFSET    0x00
    504 /** This macro defines an offset into the context for use in assembly. */
    505 #define G1_OFFSET    0x04
    506 /** This macro defines an offset into the context for use in assembly. */
    507 #define G2_OFFSET    0x08
    508 /** This macro defines an offset into the context for use in assembly. */
    509 #define G3_OFFSET    0x0C
    510 /** This macro defines an offset into the context for use in assembly. */
    511 #define G4_OFFSET    0x10
    512 /** This macro defines an offset into the context for use in assembly. */
    513 #define G5_OFFSET    0x14
    514 /** This macro defines an offset into the context for use in assembly. */
    515 #define G6_OFFSET    0x18
    516 /** This macro defines an offset into the context for use in assembly. */
    517 #define G7_OFFSET    0x1C
    518 
    519 /** This macro defines an offset into the context for use in assembly. */
    520 #define L0_OFFSET    0x20
    521 /** This macro defines an offset into the context for use in assembly. */
    522 #define L1_OFFSET    0x24
    523 /** This macro defines an offset into the context for use in assembly. */
    524 #define L2_OFFSET    0x28
    525 /** This macro defines an offset into the context for use in assembly. */
    526 #define L3_OFFSET    0x2C
    527 /** This macro defines an offset into the context for use in assembly. */
    528 #define L4_OFFSET    0x30
    529 /** This macro defines an offset into the context for use in assembly. */
    530 #define L5_OFFSET    0x34
    531 /** This macro defines an offset into the context for use in assembly. */
    532 #define L6_OFFSET    0x38
    533 /** This macro defines an offset into the context for use in assembly. */
    534 #define L7_OFFSET    0x3C
    535 
    536 /** This macro defines an offset into the context for use in assembly. */
    537 #define I0_OFFSET    0x40
    538 /** This macro defines an offset into the context for use in assembly. */
    539 #define I1_OFFSET    0x44
    540 /** This macro defines an offset into the context for use in assembly. */
    541 #define I2_OFFSET    0x48
    542 /** This macro defines an offset into the context for use in assembly. */
    543 #define I3_OFFSET    0x4C
    544 /** This macro defines an offset into the context for use in assembly. */
    545 #define I4_OFFSET    0x50
    546 /** This macro defines an offset into the context for use in assembly. */
    547 #define I5_OFFSET    0x54
    548 /** This macro defines an offset into the context for use in assembly. */
    549 #define I6_FP_OFFSET 0x58
    550 /** This macro defines an offset into the context for use in assembly. */
    551 #define I7_OFFSET    0x5C
    552 
    553 /** This macro defines an offset into the context for use in assembly. */
    554 #define O0_OFFSET    0x60
    555 /** This macro defines an offset into the context for use in assembly. */
    556 #define O1_OFFSET    0x64
    557 /** This macro defines an offset into the context for use in assembly. */
    558 #define O2_OFFSET    0x68
    559 /** This macro defines an offset into the context for use in assembly. */
    560 #define O3_OFFSET    0x6C
    561 /** This macro defines an offset into the context for use in assembly. */
    562 #define O4_OFFSET    0x70
    563 /** This macro defines an offset into the context for use in assembly. */
    564 #define O5_OFFSET    0x74
    565 /** This macro defines an offset into the context for use in assembly. */
    566 #define O6_SP_OFFSET 0x78
    567 /** This macro defines an offset into the context for use in assembly. */
    568 #define O7_OFFSET    0x7C
    569 
    570 /** This macro defines an offset into the context for use in assembly. */
    571 #define PSR_OFFSET   0x80
    572 /** This macro defines an offset into the context for use in assembly. */
    573 #define ISR_DISPATCH_DISABLE_STACK_OFFSET 0x84
     491#define G2_OFFSET    0x00
     492/** This macro defines an offset into the context for use in assembly. */
     493#define G3_OFFSET    0x04
     494/** This macro defines an offset into the context for use in assembly. */
     495#define G4_OFFSET    0x08
     496/** This macro defines an offset into the context for use in assembly. */
     497#define G5_OFFSET    0x0C
     498/** This macro defines an offset into the context for use in assembly. */
     499#define G6_OFFSET    0x10
     500/** This macro defines an offset into the context for use in assembly. */
     501#define G7_OFFSET    0x14
     502
     503/** This macro defines an offset into the context for use in assembly. */
     504#define L0_OFFSET    0x18
     505/** This macro defines an offset into the context for use in assembly. */
     506#define L1_OFFSET    0x1C
     507/** This macro defines an offset into the context for use in assembly. */
     508#define L2_OFFSET    0x20
     509/** This macro defines an offset into the context for use in assembly. */
     510#define L3_OFFSET    0x24
     511/** This macro defines an offset into the context for use in assembly. */
     512#define L4_OFFSET    0x28
     513/** This macro defines an offset into the context for use in assembly. */
     514#define L5_OFFSET    0x2C
     515/** This macro defines an offset into the context for use in assembly. */
     516#define L6_OFFSET    0x30
     517/** This macro defines an offset into the context for use in assembly. */
     518#define L7_OFFSET    0x34
     519
     520/** This macro defines an offset into the context for use in assembly. */
     521#define I0_OFFSET    0x38
     522/** This macro defines an offset into the context for use in assembly. */
     523#define I1_OFFSET    0x3C
     524/** This macro defines an offset into the context for use in assembly. */
     525#define I2_OFFSET    0x40
     526/** This macro defines an offset into the context for use in assembly. */
     527#define I3_OFFSET    0x44
     528/** This macro defines an offset into the context for use in assembly. */
     529#define I4_OFFSET    0x48
     530/** This macro defines an offset into the context for use in assembly. */
     531#define I5_OFFSET    0x4C
     532/** This macro defines an offset into the context for use in assembly. */
     533#define I6_FP_OFFSET 0x50
     534/** This macro defines an offset into the context for use in assembly. */
     535#define I7_OFFSET    0x54
     536
     537/** This macro defines an offset into the context for use in assembly. */
     538#define O6_SP_OFFSET 0x58
     539/** This macro defines an offset into the context for use in assembly. */
     540#define O7_OFFSET    0x5C
     541
     542/** This macro defines an offset into the context for use in assembly. */
     543#define PSR_OFFSET   0x60
     544/** This macro defines an offset into the context for use in assembly. */
     545#define ISR_DISPATCH_DISABLE_STACK_OFFSET 0x64
    574546
    575547/** This defines the size of the context area for use in assembly. */
    576 #define CONTEXT_CONTROL_SIZE 0x88
     548#define CONTEXT_CONTROL_SIZE 0x68
    577549
    578550#ifndef ASM
Note: See TracChangeset for help on using the changeset viewer.