Changeset 978eba3 in rtems for c


Ignore:
Timestamp:
Sep 30, 2008, 11:17:15 PM (12 years ago)
Author:
Joel Sherrill <joel.sherrill@…>
Branches:
4.9
Children:
4566e9c1
Parents:
db6e1f55
Message:

2008-09-30 Jennifer Averett <jennifer.averett@…>

  • Makefile.am, preinstall.am, PCI_bus/universe.c, console/console.c, include/bsp.h, irq/FPGA.c, irq/irq.c, startup/Hwr_init.c, startup/bspstart.c, startup/vmeintr.c: Modifications required to run on hardware. Some cleanup.
  • include/irq-config.h: New file.
  • startup/spurious.c: Removed.
Location:
c/src/lib/libbsp/powerpc/score603e
Files:
1 added
1 deleted
11 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/powerpc/score603e/ChangeLog

    rdb6e1f55 r978eba3  
     12008-09-30      Jennifer Averett <jennifer.averett@oarcorp.com>
     2
     3        * Makefile.am, preinstall.am, PCI_bus/universe.c, console/console.c,
     4        include/bsp.h, irq/FPGA.c, irq/irq.c, startup/Hwr_init.c,
     5        startup/bspstart.c, startup/vmeintr.c: Modifications required to run
     6        on hardware. Some cleanup.
     7        * include/irq-config.h: New file.
     8        * startup/spurious.c: Removed.
     9
    1102008-09-29      Ralf Corsépius <ralf.corsepius@rtems.org>
    211
  • c/src/lib/libbsp/powerpc/score603e/Makefile.am

    rdb6e1f55 r978eba3  
    3535
    3636include_bsp_HEADERS = ../../powerpc/shared/pci/pci.h \
    37     PCI_bus/PCI.h \
    38     ../../powerpc/shared/residual/residual.h \
    39     ../../powerpc/shared/residual/pnp.h \
    40     ../../powerpc/shared/openpic/openpic.h \
    41     ../../powerpc/shared/console/consoleIo.h
     37        PCI_bus/PCI.h \
     38        ../../powerpc/shared/residual/residual.h \
     39        ../../powerpc/shared/residual/pnp.h \
     40        ../../powerpc/shared/openpic/openpic.h \
     41        ../../powerpc/shared/console/consoleIo.h \
     42        ../../shared/include/irq-generic.h \
     43        include/irq-config.h
     44
    4245pci_SOURCES = pci/no_host_bridge.c ../../powerpc/shared/pci/pci.c \
    4346    ../../powerpc/shared/pci/pcifinddevice.c  PCI_bus/PCI.c  PCI_bus/universe.c
    4447
    4548include_bsp_HEADERS += irq/irq.h \
    46     ../../../libcpu/@RTEMS_CPU@/@exceptions@/bspsupport/ppc_exc_bspsupp.h \
    47     ../../../libcpu/@RTEMS_CPU@/@exceptions@/bspsupport/vectors.h \
    48     ../../../libcpu/@RTEMS_CPU@/@exceptions@/bspsupport/irq_supp.h
    49 irq_SOURCES = irq/FPGA.c irq/irq.c ../../powerpc/shared/irq/irq_asm.S
     49        ../../../libcpu/@RTEMS_CPU@/@exceptions@/bspsupport/ppc_exc_bspsupp.h \
     50        ../../../libcpu/@RTEMS_CPU@/@exceptions@/bspsupport/vectors.h \
     51        ../../../libcpu/@RTEMS_CPU@/@exceptions@/bspsupport/irq_supp.h
     52irq_SOURCES = include/irq-config.h \
     53    irq/FPGA.c irq/irq.c       \
     54    ../../shared/src/irq-generic.c       \
     55    ../../powerpc/shared/irq/irq_asm.S
    5056
    5157include_bsp_HEADERS += ../../powerpc/shared/vectors/vectors.h
     
    5460
    5561include_bsp_HEADERS += ../../shared/vmeUniverse/vmeUniverse.h \
     62    ../../shared/include/irq-generic.h \
    5663    ../../shared/vmeUniverse/vme_am_defs.h \
    5764    ../../shared/vmeUniverse/VME.h \
  • c/src/lib/libbsp/powerpc/score603e/PCI_bus/universe.c

    rdb6e1f55 r978eba3  
    158158  uint32_t         jumper_selection;
    159159  uint32_t         pci_id;
    160 #if (SCORE603E_USE_SDS) | (SCORE603E_USE_OPEN_FIRMWARE) | (SCORE603E_USE_NONE)
    161   volatile uint32_t         universe_temp_value;
    162 #endif
    163160
    164161  /*
     
    167164  jumper_selection = PCI_bus_read(
    168165                     (volatile uint32_t*)SCORE603E_VME_JUMPER_ADDR );
     166  printk("initialize_universe: Read 0x%x = 0x%x\n",
     167          SCORE603E_VME_JUMPER_ADDR, jumper_selection);
    169168  jumper_selection = (jumper_selection >> 3) & 0x1f;
    170169
     
    180179     printk ("Invalid SCORE603E_UNIVERSE_CHIP_ID: 0x08%" PRId32 "\n", pci_id);
    181180     rtems_fatal_error_occurred( 0x603e0bad );
     181   } else {
     182     printk("initialize_universe: Reg 0x%x read 0x%x\n",
     183     SCORE603E_IO_VME_UNIVERSE_BASE, pci_id );
    182184   }
    183185
    184 #if (SCORE603E_USE_SDS) | (SCORE603E_USE_OPEN_FIRMWARE) | (SCORE603E_USE_NONE)
    185 
    186    /*
    187     * Set the UNIVERSE PCI Configuration Base Address Register with 0x30001
    188     * to specifies the 64 Kbyte aligned base address of the UNIVERSE register
    189     * space on PCI to be 0x30000 + 0x80000000 (IO_BASE)
    190     */
    191    Write_pci_device_register( SCORE603E_IO_VME_UNIVERSE_BASE+0x10,0x30001 );
    192 
    193    /*
    194     * Set the UNIVERSE PCI Configuration Space Control and Status Register to
    195     * medium speed device, Target Back to Back Capable, Master Enable, Target
    196     * Memory Enable and Target IO Enable
    197     */
    198    Write_pci_device_register( SCORE603E_IO_VME_UNIVERSE_BASE+0x4, 0x2800007 );
    199 
    200    /*
    201     * Turn off the sysfail by setting SYSFAIL bit to 1 on the VCSR_CLR register
    202     */
    203    PCI_bus_write( &UNIVERSE->VCSR_CLR, 0x40000000 );
    204 
    205    /*
    206     * Set the VMEbus Master Control register with retry forever, 256 bytes
    207     * posted write transfer count, VMEbus request level 3, RWD, PCI 32 bytes
    208     * aligned burst size and PCI bus number to be zero
    209     */
    210    PCI_bus_write( &UNIVERSE->MAST_CTL, 0x01C00000 );
    211 
    212    /*
    213     * VMEbus DMA Transfer Control register with 32 bit VMEbus Maximum Data
    214     * width, A32 VMEbus Address Space, AM code to be data, none-privilleged,
    215     * single and BLT cycles on VME bus and 64-bit PCI Bus Transactions enable
    216     PCI_bus_write( &UNIVERSE->DCTL, 0x00820180 );
    217     */
    218 
    219    PCI_bus_write( &UNIVERSE->LSI0_CTL, 0x80700040 );
    220    PCI_bus_write( &UNIVERSE->LSI0_BS,  0x04000000 );
    221    PCI_bus_write( &UNIVERSE->LSI0_BD,  0x05000000 );
    222    PCI_bus_write( &UNIVERSE->LSI0_TO,  0x7C000000 );
    223 
    224    /*
    225     * Remove the Universe from VMEbus BI-Mode (bus-isolation).  Once out of
    226     * BI-Mode VMEbus accesses can be made.
    227     */
    228 
    229    universe_temp_value = PCI_bus_read( &UNIVERSE->MISC_CTL );
    230 
    231    if (universe_temp_value & 0x100000)
    232      PCI_bus_write( &UNIVERSE->MISC_CTL,(universe_temp_value | ~0xFF0FFFFF));
    233 
    234 #elif (SCORE603E_USE_DINK)
    235186   /*
    236187    * Do not modify the DINK setup of the universe chip.
    237188    */
    238 
    239 #else
    240 #error "SCORE603E BSPSTART.C -- what ROM monitor are you using"
    241 #endif
    242 
    243189}
    244190
  • c/src/lib/libbsp/powerpc/score603e/console/console.c

    rdb6e1f55 r978eba3  
    2424#include <rtems/bspIo.h>
    2525
    26 #if (1)
    2726/*
    2827 * The Port Used for the Console interface is based upon which
     
    3231 */
    3332
    34 #if (SCORE603E_USE_SDS)
    35 #define USE_FOR_CONSOLE_DEF  1
    36 
    37 #elif (SCORE603E_USE_OPEN_FIRMWARE)
    3833#define USE_FOR_CONSOLE_DEF  0
    39 
    40 #elif (SCORE603E_USE_NONE)
    41 #define USE_FOR_CONSOLE_DEF  0
    42 
    43 #elif (SCORE603E_USE_DINK)
    44 #define USE_FOR_CONSOLE_DEF  0
    45 
    46 #else
    47 #error "SCORE603E CONSOLE.C -- what ROM monitor are you using"
    48 #endif
    49 
    50 #endif
    51 
    52 #if (0)
    53 extern int USE_FOR_CONSOLE;
    54 #endif
    55 
    5634int USE_FOR_CONSOLE = USE_FOR_CONSOLE_DEF;
    5735
     
    135113  for (i=0; i < NUM_Z85C30_PORTS; i++){
    136114      ISR_85c30_Async( &Ports_85C30[i] );
    137 
    138 #if (0) /* XXX - TO TEST LOOP BACKS comment this out. */
    139     if ( Ports_85C30[i].Chip->vector == vector ) {
    140       ISR_85c30_Async( &Ports_85C30[i] );
    141     }
    142 #endif
    143115  }
    144116}
     
    192164);
    193165
    194 /* XXXXXX */
    195166#endif
    196167
  • c/src/lib/libbsp/powerpc/score603e/include/bsp.h

    rdb6e1f55 r978eba3  
    3636#define CONFIGURE_NUMBER_OF_TERMIOS_PORTS (4 + 4)
    3737#else
     38/* XXXXX FIX THIS */
     39#error "MUST HAVE PSC8 SET FOR BOEING CODE"
    3840#define CONFIGURE_NUMBER_OF_TERMIOS_PORTS (4)
    3941#endif
     
    7779
    7880#define Processor_Synchronize() \
    79   asm(" eieio ")
     81  asm volatile(" eieio ")
    8082
    8183
     
    130132
    131133/*
    132  * spurious.c
    133  */
    134 rtems_isr bsp_stub_handler(
    135    rtems_vector_number trap
    136 );
    137 rtems_isr bsp_spurious_handler(
    138    rtems_vector_number trap
    139 );
    140 void bsp_spurious_initialize();
    141 
    142 /*
    143134 * genvec.c
    144135 */
  • c/src/lib/libbsp/powerpc/score603e/irq/FPGA.c

    rdb6e1f55 r978eba3  
    2525void initialize_PCI_bridge (void)
    2626{
    27 #if (!SCORE603E_USE_DINK)
    28   uint16_t         mask, shift, data;
    29 
    30   shift = SCORE603E_85C30_0_IRQ - Score_IRQ_First;
    31   mask = 1 << shift;
    32 
    33   shift = SCORE603E_85C30_1_IRQ - Score_IRQ_First;
    34   mask  = mask & (1 << shift);
    35 
    36   data = *SCORE603E_FPGA_MASK_DATA;
    37   data = ~mask;
    38 
    39   *SCORE603E_FPGA_MASK_DATA = data;
    40 #endif
    41 
     27  /* Note: Accept DINKs setup of the PCI Bridge and don't
     28   *       change anything.
     29   */
     30  printk("initialize_PCI_bridge: \n");
    4231}
    4332
     
    9685  uint32_t         i;
    9786
    98 #if (SCORE603E_USE_DINK)
    9987  set_irq_mask( 0xffff );
    100 #endif
    10188
    10289  /*
  • c/src/lib/libbsp/powerpc/score603e/irq/irq.c

    rdb6e1f55 r978eba3  
    141141
    142142/*
     143 * This function disables a given XXX interrupt
     144 */
     145rtems_status_code bsp_interrupt_vector_disable( rtems_vector_number irqLine)
     146{
     147  /* XXX FIX ME!!!! */
     148
     149  printk("bsp_interrupt_vector_disable: 0x%x\n", irqLine );
     150  return RTEMS_SUCCESSFUL;
     151}
     152
     153rtems_status_code bsp_interrupt_vector_enable( rtems_vector_number irqLine)
     154{
     155  /* XXX FIX ME!!!! */
     156  printk("bsp_interrupt_vector_enable: 0x%x\n", irqLine );
     157
     158  return RTEMS_SUCCESSFUL;
     159}
     160
     161
     162
     163/*
    143164 * ------------------------ RTEMS Single Irq Handler Mngt Routines ----------------
    144165 */
     
    179200       * Enable interrupt
    180201       */
     202      printk("is_pci_irq = TRUE - FIX THIS!\n");
    181203    }
    182204
     
    185207       * Enable exception at processor level
    186208       */
    187     }
     209      printk("is_processor_irq = TRUE : Fix This\n");
     210    }
     211
    188212    /*
    189213     * Enable interrupt on device
    190214     */
    191         if (irq->on)
     215    if (irq->on) {
     216        printk("Call 0x%x\n", irq->on );
    192217        irq->on(irq);
     218    }
    193219
    194220    rtems_interrupt_enable(level);
     
    416442  register unsigned new_msr;
    417443
    418 printk(" C_dispatch_irq_handler %d\n", excNum);
    419444  if (excNum == ASM_DEC_VECTOR) {
    420445    _CPU_MSR_GET(msr);
     
    469494   */
    470495}
     496
     497rtems_status_code bsp_interrupt_facility_initialize( void)
     498{
     499  /* Install exception handler */
     500  if (ppc_exc_set_handler( ASM_EXT_VECTOR, C_dispatch_irq_handler)) {
     501    return RTEMS_IO_ERROR;
     502  }
     503  if (ppc_exc_set_handler( ASM_DEC_VECTOR, C_dispatch_irq_handler)) {
     504    return RTEMS_IO_ERROR;
     505  }
     506  if (ppc_exc_set_handler( ASM_E300_SYSMGMT_VECTOR, C_dispatch_irq_handler)) {
     507    return RTEMS_IO_ERROR;
     508  }
     509
     510  return RTEMS_SUCCESSFUL;
     511}
     512
     513
  • c/src/lib/libbsp/powerpc/score603e/preinstall.am

    rdb6e1f55 r978eba3  
    9090PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/consoleIo.h
    9191
     92$(PROJECT_INCLUDE)/bsp/irq-generic.h: ../../shared/include/irq-generic.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
     93        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq-generic.h
     94PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq-generic.h
     95
     96$(PROJECT_INCLUDE)/bsp/irq-config.h: include/irq-config.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
     97        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq-config.h
     98PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq-config.h
     99
    92100$(PROJECT_INCLUDE)/bsp/irq.h: irq/irq.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
    93101        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq.h
     
    113121        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/vmeUniverse.h
    114122PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/vmeUniverse.h
     123
     124$(PROJECT_INCLUDE)/bsp/irq-generic.h: ../../shared/include/irq-generic.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
     125        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq-generic.h
     126PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq-generic.h
    115127
    116128$(PROJECT_INCLUDE)/bsp/vme_am_defs.h: ../../shared/vmeUniverse/vme_am_defs.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
  • c/src/lib/libbsp/powerpc/score603e/startup/Hwr_init.c

    rdb6e1f55 r978eba3  
    8181void init_PCI(void)
    8282{
    83 #if (SCORE603E_USE_SDS) | (SCORE603E_USE_OPEN_FIRMWARE) | (SCORE603E_USE_NONE)
    84   uint32_t         value;
    85 
    86  /*
    87   * NOTE:  Accessing any memory location not mapped by the BAT
    88   * registers will cause a TLB miss exception.
    89   * Set the DBAT1 to be configured for 256M of PCI MEM
    90   * at 0xC0000000 with Write-through and Guarded Attributed and
    91   * read/write access allowed
    92   */
    93 
    94  /* load DBAT1U (spr538) - 256Mbytes, User, Super */
    95   value = SCORE603E_PCI_MEM_BASE | 0x1FFF;
    96   asm volatile(
    97     "isync;"
    98     "mtspr 538, %0"
    99     : "=r" (value)
    100     : "0" (value)
    101   );
    102 
    103   /* load DBAT1L (spr539) - Write-through, Guarded and Read/Write */
    104   value = SCORE603E_PCI_MEM_BASE | 0x0002;
    105   asm volatile (
    106       "mtspr 539, %0;"
    107       "isync"
    108       : "=r" (value)
    109       : "0" (value)
    110   );
    111 
    112 #elif (SCORE603E_USE_DINK)
    11383  /* DINK Monitor setsup and uses all 4 BAT registers.  */
    11484  /* The fourth BAT register can be modified to access this area */
    11585
    116 #if (0)
    117  /*
    118   * NOTE:  Accessing any memory location not mapped by the BAT
    119   * registers will cause a TLB miss exception.
    120   * Set the DBAT3 to be configured for 256M of PCI MEM
    121   * at 0xC0000000 with Write-through and Guarded Attributed and
    122   * read/write access allowed
    123   */
    124 
    125  /* load DBAT3U (spr542) - 256Mbytes, User, Super */
    126   value = SCORE603E_PCI_MEM_BASE | 0x1FFF;
    127   asm volatile(
    128     "isync;"
    129     "mtspr 542, %0"
    130     : "=r" (value)
    131     : "0" (value)
    132   );
    133 
    134   /* load DBAT3L (spr543) - Write-through, Guarded and Read/Write */
    135   value = SCORE603E_PCI_MEM_BASE | 0x0002;
    136   asm volatile (
    137       "mtspr 543, %0;"
    138       "isync"
    139       : "=r" (value)
    140       : "0" (value)
    141   );
    142 #endif
    143 
    144 #else
    145 #error "SCORE603E BSPSTART.C -- what ROM monitor are you using"
    146 #endif
     86  printk("init_PCI:\n");
    14787}
    14888
  • c/src/lib/libbsp/powerpc/score603e/startup/bspstart.c

    rdb6e1f55 r978eba3  
    4343 * Time base divisior (how many tick for 1 second).
    4444 */
    45 unsigned int BSP_time_base_divisor = 1000;  /* XXX - Just a guess */
     45unsigned int BSP_time_base_divisor = 4000;
    4646
    4747/*
     
    122122void bsp_predriver_hook(void)
    123123{
    124   #if DEBUG
    125     printk("bsp_predriver_hook: init_RTC\n");
    126   #endif
    127   init_RTC();
    128   init_PCI();
    129   initialize_universe();
    130 
    131   #if DEBUG
    132     printk("bsp_predriver_hook: initialize_PCI_bridge\n");
    133   #endif
    134   initialize_PCI_bridge ();
    135124
    136125#if (HAS_PMC_PSC8)
     
    141130#endif
    142131
    143 #if 0
    144  /*
    145   * Initialize Bsp General purpose vector table.
    146   */
    147   #if DEBUG
    148     printk("bsp_predriver_hook: initialize_external_exception_vector\n");
    149   #endif
    150  initialize_external_exception_vector();
    151 #endif
    152 
    153 #if (0)
    154   /*
    155    * XXX - Modify this to write a 48000000 (loop to self) command
    156    *       to each interrupt location.  This is better for debug.
    157    */
    158   #if DEBUG
    159     printk("bsp_predriver_hook: bsp_spurious_initialize\n");
    160   #endif
    161  bsp_spurious_initialize();
    162 #endif
    163 
    164   ShowBATS();
    165 
    166132  #if DEBUG
    167133    printk("bsp_predriver_hook: End of routine\n");
     
    176142
    177143void initialize_PMC() {
    178   volatile uint32_t         *PMC_addr;
    179   uint8_t          data;
    180 
    181 #if (0) /* First Values sent */
     144  volatile uint32_t     *PMC_addr;
     145  uint32_t               data;
     146
     147  /*
     148   * Clear status, enable SERR and memory space only.
     149   */
     150  PMC_addr = BSP_PCI_DEVICE_ADDRESS( 0x4 );
     151  *PMC_addr = 0x020080cc;
     152  #if DEBUG
     153    printk("initialize_PMC: 0x%x = 0x%x\n", PMC_addr, 0x020080cc);
     154  #endif
     155
    182156  /*
    183157   * set PMC base address.
     
    185159  PMC_addr  = BSP_PCI_DEVICE_ADDRESS( 0x14 );
    186160  *PMC_addr = (BSP_PCI_REGISTER_BASE >> 24) & 0x3f;
    187 
    188   /*
    189    * Clear status, enable SERR and memory space only.
    190    */
    191   PMC_addr = BSP_PCI_DEVICE_ADDRESS( 0x4 );
    192   *PMC_addr = 0x0201ff37;
    193 
    194   /*
    195    * Bit 0 and 1 HI cause Medium Loopback to occur.
    196    */
    197   PMC_addr = (volatile uint32_t*)
    198         BSP_PMC_SERIAL_ADDRESS( 0x100000 );
    199   data = *PMC_addr;
    200   /*   *PMC_addr = data | 0x3;  */
    201   *PMC_addr = data & 0xfc;
    202 
    203 #endif
    204 
    205 #if (1)
    206 
    207   /*
    208    * Clear status, enable SERR and memory space only.
    209    */
    210   #if DEBUG
    211     printk("initialize_PMC: set Device Address 0x4 \n");
    212   ShowBATS();
    213   #endif
    214   PMC_addr = BSP_PCI_DEVICE_ADDRESS( 0x4 );
    215   *PMC_addr = 0x020080cc;
    216 
    217   /*
    218    * set PMC base address.
    219    */
    220   #if DEBUG
    221     printk("initialize_PMC: set Device Address 0x14 \n");
    222   ShowBATS();
    223   #endif
    224   PMC_addr  = BSP_PCI_DEVICE_ADDRESS( 0x14 );
    225   *PMC_addr = (BSP_PCI_REGISTER_BASE >> 24) & 0x3f;
    226 
    227   #if DEBUG
    228     printk("initialize_PMC: set PMC Serial Address 0x100000\n");
    229   #endif
     161  #if DEBUG
     162    printk("initialize_PMC: 0x%x = 0x%x\n", PMC_addr, ((BSP_PCI_REGISTER_BASE >> 24) & 0x3f));
     163  #endif
     164
    230165   PMC_addr = (volatile uint32_t*)
    231166      BSP_PMC_SERIAL_ADDRESS( 0x100000 );
    232167  data = *PMC_addr;
     168  #if DEBUG
     169    printk("initialize_PMC: Read 0x%x (0x%x)\n", PMC_addr, data );
     170    printk("initialize_PMC: Read 0x%x (0x%x)\n", PMC_addr, data & 0xfc );
     171  #endif
    233172  *PMC_addr = data & 0xfc;
    234 
    235 #endif
    236173}
    237174
     
    247184  extern void Init_EE_mask_init(void);
    248185  extern void open_dev_console(void);
    249 
    250186  #if DEBUG
    251187    printk("bsp_postdriver_hook: open_dev_console\n");
    252188  #endif
    253189  open_dev_console();
    254   ShowBATS();
    255190
    256191  #if DEBUG
     
    258193  #endif
    259194  Init_EE_mask_init();
    260   ShowBATS();
    261195  #if DEBUG
    262196    printk("bsp_postdriver_hook: Finished procedure\n");
     
    282216  ppc_cpu_id_t myCpu;
    283217  ppc_cpu_revision_t myCpuRevision;
    284  
     218
    285219  rtems_bsp_delay( 1000 );
    286220
     
    290224  #if DEBUG
    291225    printk("bsp_start: Zero out lots of memory\n");
    292     ShowBATS();
    293226  #endif
    294227
     
    309242  myCpu         = get_ppc_cpu_type();
    310243  myCpuRevision = get_ppc_cpu_revision();
     244  printk("Cpu: 0x%x  Revision: %d\n", myCpu, myCpuRevision);
     245  printk("Cpu %s\n", get_ppc_cpu_type_name(myCpu) );
    311246
    312247  /*
     
    320255   * Initialize default raw exception handlers.
    321256   */
    322 printk("ppc_exc_initialize\n");
    323257  ppc_exc_initialize(
    324258    PPC_INTERRUPT_DISABLE_MASK_DEFAULT,
     
    326260    intrStackSize
    327261  );
    328 
    329   /*
    330    *  There are multiple ROM monitors available for this board.
    331    */
    332 #if (SCORE603E_USE_SDS)
    333   #if DEBUG
    334     printk("bsp_start: USE SDS\n");
    335   #endif
    336 
    337 
    338   /*
    339    * Write instruction for Unconditional Branch to ROM vector.
    340    */
    341 
    342    Code = 0x4bf00002;
    343    for (Address = 0x100; Address <= 0xe00; Address += 0x100) {
    344      A_Vector = (uint32_t*)Address;
    345      Code = 0x4bf00002 + Address;
    346      *A_Vector = Code;
    347    }
    348 
    349    for (Address = 0x1000; Address <= 0x1400; Address += 0x100) {
    350      A_Vector = (uint32_t*)Address;
    351      Code = 0x4bf00002 + Address;
    352      *A_Vector = Code;
    353    }
    354 
    355   msr_value = 0x2030;
    356 
    357 #elif (SCORE603E_USE_OPEN_FIRMWARE)
    358   #if DEBUG
    359     printk("bsp_start: USE OPEN FIRMWARE\n");
    360   #endif
    361   msr_value = 0x2030;
    362 
    363 #elif (SCORE603E_USE_NONE)
    364   #if DEBUG
    365     printk("bsp_start: USE NONE\n");
    366   #endif
     262  #if DEBUG
     263    printk("bsp_predriver_hook: init_RTC\n");
     264  #endif
     265
     266/*   init_RTC(); */
     267  init_PCI();
     268  initialize_universe();
     269
     270  #if DEBUG
     271    printk("bsp_predriver_hook: initialize_PCI_bridge\n");
     272  #endif
     273  initialize_PCI_bridge ();
     274
    367275  msr_value = 0x2030;
    368276  _CPU_MSR_SET( msr_value );
    369   bsp_set_trap_vectors();
    370 
    371 #elif (SCORE603E_USE_DINK)
    372   #if DEBUG
    373     printk("bsp_start: USE DINK\n");
    374   #endif
    375   msr_value = 0x2030;
    376   _CPU_MSR_SET( msr_value );
    377 
    378   /*
    379    * Override the DINK error on a Decrementor interrupt.
    380    */
    381   /* org    dec_vector  - rfi */
    382   ptr = (uint32_t*)0x900;
    383   *ptr = 0x4c000064;
    384 
    385 #else
    386   #if DEBUG
    387     printk("bsp_start: ERROR unknow ROM Monitor\n");
    388   #endif
    389 #error "SCORE603E BSPSTART.C -- what ROM monitor are you using"
    390 #endif
     277
    391278
    392279  _CPU_MSR_SET( msr_value );
     
    429316  #endif
    430317#endif
     318
     319  /* Initalize interrupt support */
     320  if (bsp_interrupt_initialize() != RTEMS_SUCCESSFUL) {
     321    BSP_panic( "Cannot intitialize interrupt support\n");
     322  }
     323
    431324  #if DEBUG
    432325    printk("bsp_start: end BSPSTART\n");
  • c/src/lib/libbsp/powerpc/score603e/startup/vmeintr.c

    rdb6e1f55 r978eba3  
    2727)
    2828{
    29   volatile uint8_t          *VME_interrupt_enable;
    30   uint8_t          value;
     29  volatile uint8_t  *VME_interrupt_enable;
     30  uint8_t           value;
    3131
    32 #if 0
    33   VME_interrupt_enable = ACC_VIE;
    34 #else
    3532  VME_interrupt_enable = 0;
    36 #endif
    3733  value = *VME_interrupt_enable;
    38 
    3934  value &= ~mask;  /* turn off interrupts for all levels in mask */
    40 
    4135  *VME_interrupt_enable = value;
    4236}
     
    5549  uint8_t          value;
    5650
    57 #if 0
    58   VME_interrupt_enable = ACC_VIE;
    59 #else
    6051  VME_interrupt_enable = 0;
    61 #endif
    6252  value = *VME_interrupt_enable;
    63 
    6453  value |= mask;  /* turn on interrupts for all levels in mask */
    65 
    6654  *VME_interrupt_enable = value;
    6755}
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