Changeset 976c170 in umon


Ignore:
Timestamp:
Aug 7, 2015, 6:04:18 PM (4 years ago)
Author:
Jarielle Catbagan <jcatbagan93@…>
Branches:
master
Children:
91be006
Parents:
d355df2
git-author:
Jarielle Catbagan <jcatbagan93@…> (08/07/15 18:04:18)
git-committer:
Ed Sutter <edsutterjr@…> (08/08/15 00:44:37)
Message:

BBB: Clean up *.c and *.h files using 'astyle --unpad-paren --align-pointer=name --lineend=linux --add-brackets --convert-tabs -A4 <file>'

Note: <file> is the file being formatted

Location:
ports/beagleboneblack
Files:
8 edited

Legend:

Unmodified
Added
Removed
  • ports/beagleboneblack/am335x_mmc.c

    rd355df2 r976c170  
    1717
    1818char *mmcHelp[] = {
    19         "MultiMediaCard Interface",
    20         "[options] {operation} [args]...",
     19    "MultiMediaCard Interface",
     20    "[options] {operation} [args]...",
    2121#if INCLUDE_VERBOSEHELP
    22         "",
    23         "Options:",
    24         " -i ## interface # (default is 0)",
    25         " -v    additive verbosity",
    26         "",
    27         "Operations:",
    28         " init",
    29         " read {dest} {blk} {blktot}",
    30         " write {source} {blk} {blktot}",
     22    "",
     23    "Options:",
     24    " -i ##     interface # (default is 0)",
     25    " -v        additive verbosity",
     26    "",
     27    "Operations:",
     28    " init",
     29    " read {dest} {blk} {blktot}",
     30    " write {source} {blk} {blktot}",
    3131#endif /* INCLUDE_VERBOSEHELP */
    32         0
     32    0
    3333};
    3434
     
    3636mmccmd(uint32_t cmd, uint32_t arg, uint32_t resp[4])
    3737{
    38         /* Clear the SD_STAT register for proper update of status bits after CMD invocation */
    39         MMC1_REG(SD_STAT) = 0xFFFFFFFF;
    40 
    41         MMC1_REG(SD_ARG) = arg;
    42         MMC1_REG(SD_CMD) = cmd;
    43 
    44         /* CMDx complete? */
    45         while (!(MMC1_REG(SD_STAT) & (SD_STAT_CC | SD_STAT_ERRI)));
    46 
    47         resp[0] = MMC1_REG(SD_RSP10);
    48         resp[1] = MMC1_REG(SD_RSP32);
    49         resp[2] = MMC1_REG(SD_RSP54);
    50         resp[3] = MMC1_REG(SD_RSP76);
    51 
    52         /* CMDx error? */
    53         if (MMC1_REG(SD_STAT) & SD_STAT_ERRI)
    54                 return(-1);
    55         else
    56                 return(0);
     38    /* Clear the SD_STAT register for proper update of status bits after CMD invocation */
     39    MMC1_REG(SD_STAT) = 0xFFFFFFFF;
     40
     41    MMC1_REG(SD_ARG) = arg;
     42    MMC1_REG(SD_CMD) = cmd;
     43
     44    /* CMDx complete? */
     45    while(!(MMC1_REG(SD_STAT) & (SD_STAT_CC | SD_STAT_ERRI)));
     46
     47    resp[0] = MMC1_REG(SD_RSP10);
     48    resp[1] = MMC1_REG(SD_RSP32);
     49    resp[2] = MMC1_REG(SD_RSP54);
     50    resp[3] = MMC1_REG(SD_RSP76);
     51
     52    /* CMDx error? */
     53    if(MMC1_REG(SD_STAT) & SD_STAT_ERRI) {
     54        return(-1);
     55    } else {
     56        return(0);
     57    }
    5758}
    5859
     
    6061mmc(int argc, char *argv[])
    6162{
    62         char *cmd, *buf;
    63         int opt, verbose, mmcret, blknum, blkcnt;
    64 
    65         verbose = 0;
    66 
    67         while ((opt = getopt(argc, argv, "i:v")) != -1) {
    68                 switch (opt) {
    69                         case 'i':
    70                                 mmcInum = atoi(optarg);
    71                                 break;
    72                         case 'v':
    73                                 verbose++;
    74                                 break;
    75                         default:
    76                                 return(CMD_PARAM_ERROR);
    77                 }
    78         }
    79 
    80         if (argc < optind + 1)
    81                 return(CMD_PARAM_ERROR);
    82 
    83         cmd = argv[optind];
    84 
    85         if (mmcInstalled(mmcInum) == 0) {
    86                 printf("MMC not installed\n");
    87                 return(CMD_FAILURE);
    88         }
    89 
    90         if (strcmp(cmd, "init") == 0) {
    91                 mmcret = mmcInit(mmcInum, verbose);
    92                 if(mmcret < 0) {
    93                         printf("mmcInit returned %d\n", mmcret);
    94                         return(CMD_FAILURE);
    95                 }
    96         }
    97         else if (strcmp(cmd, "read") == 0) {
    98                 if (argc != (optind + 4))
    99                         return(CMD_PARAM_ERROR);
    100 
    101                 buf = (char *)strtoul(argv[optind + 1], 0, 0);
    102                 blknum = strtoul(argv[optind + 2], 0, 0);
    103                 blkcnt = strtoul(argv[optind + 3], 0, 0);
    104 
    105                 mmcret = mmcRead(mmcInum, buf, blknum, blkcnt);
    106                 if (mmcret < 0) {
    107                         printf("mmcRead returned %d\n", mmcret);
    108                         return(CMD_FAILURE);
    109                 }
    110         }
    111         else if (strcmp(cmd, "write") == 0) {
    112                 if (argc != (optind + 4))
    113                         return(CMD_PARAM_ERROR);
    114 
    115                 buf = (char *)strtoul(argv[optind + 1], 0, 0);
    116                 blknum = strtoul(argv[optind + 2], 0, 0);
    117                 blkcnt = strtoul(argv[optind + 3], 0, 0);
    118 
    119                 mmcret = mmcWrite(mmcInum, buf, blknum, blkcnt);
    120                 if (mmcret < 0) {
    121                         printf("mmcWrite returned %d\n", mmcret);
    122                         return(CMD_FAILURE);
    123                 }
    124         }
    125         else {
    126                 printf("mmc op <%s> not found\n", cmd);
    127                 return(CMD_FAILURE);
    128         }
    129 
    130         return(CMD_SUCCESS);
     63    char *cmd, *buf;
     64    int opt, verbose, mmcret, blknum, blkcnt;
     65
     66    verbose = 0;
     67
     68    while((opt = getopt(argc, argv, "i:v")) != -1) {
     69        switch(opt) {
     70        case 'i':
     71            mmcInum = atoi(optarg);
     72            break;
     73        case 'v':
     74            verbose++;
     75            break;
     76        default:
     77            return(CMD_PARAM_ERROR);
     78        }
     79    }
     80
     81    if(argc < optind + 1) {
     82        return(CMD_PARAM_ERROR);
     83    }
     84
     85    cmd = argv[optind];
     86
     87    if(mmcInstalled(mmcInum) == 0) {
     88        printf("MMC not installed\n");
     89        return(CMD_FAILURE);
     90    }
     91
     92    if(strcmp(cmd, "init") == 0) {
     93        mmcret = mmcInit(mmcInum, verbose);
     94        if(mmcret < 0) {
     95            printf("mmcInit returned %d\n", mmcret);
     96            return(CMD_FAILURE);
     97        }
     98    } else if(strcmp(cmd, "read") == 0) {
     99        if(argc != (optind + 4)) {
     100            return(CMD_PARAM_ERROR);
     101        }
     102
     103        buf = (char *)strtoul(argv[optind + 1], 0, 0);
     104        blknum = strtoul(argv[optind + 2], 0, 0);
     105        blkcnt = strtoul(argv[optind + 3], 0, 0);
     106
     107        mmcret = mmcRead(mmcInum, buf, blknum, blkcnt);
     108        if(mmcret < 0) {
     109            printf("mmcRead returned %d\n", mmcret);
     110            return(CMD_FAILURE);
     111        }
     112    } else if(strcmp(cmd, "write") == 0) {
     113        if(argc != (optind + 4)) {
     114            return(CMD_PARAM_ERROR);
     115        }
     116
     117        buf = (char *)strtoul(argv[optind + 1], 0, 0);
     118        blknum = strtoul(argv[optind + 2], 0, 0);
     119        blkcnt = strtoul(argv[optind + 3], 0, 0);
     120
     121        mmcret = mmcWrite(mmcInum, buf, blknum, blkcnt);
     122        if(mmcret < 0) {
     123            printf("mmcWrite returned %d\n", mmcret);
     124            return(CMD_FAILURE);
     125        }
     126    } else {
     127        printf("mmc op <%s> not found\n", cmd);
     128        return(CMD_FAILURE);
     129    }
     130
     131    return(CMD_SUCCESS);
    131132}
    132133
     
    134135mmcInit(int interface, int verbose)
    135136{
    136         uint32_t cmd, arg, resp[4];
    137 
    138         /* Reset the MMC1 Controller */
    139         MMC1_REG(SD_SYSCONFIG) = SD_SYSCONFIG_SOFTRESET;
    140         while (!(MMC1_REG(SD_SYSSTATUS) & SD_SYSSTATUS_RESETDONE));
    141 
    142         /* Reset the command and data lines */
    143         MMC1_REG(SD_SYSCTL) |= SD_SYSCTL_SRA;
    144         while (MMC1_REG(SD_SYSCTL) & SD_SYSCTL_SRA);
    145 
    146         /* Configure the MMC1 controller capabilities to enable 3.0 V operating voltage */
    147         MMC1_REG(SD_CAPA) |= SD_CAPA_VS30;
    148 
    149         /* Configure SD_IE register to update certain status bits in SD_STAT */
    150         MMC1_REG(SD_IE) = SD_IE_BADA_ENABLE | SD_IE_CERR_ENABLE | SD_IE_ACE_ENABLE |
    151                 SD_IE_DEB_ENABLE | SD_IE_DCRC_ENABLE | SD_IE_DTO_ENABLE | SD_IE_CIE_ENABLE |
    152                 SD_IE_CEB_ENABLE | SD_IE_CCRC_ENABLE | SD_IE_CIRQ_ENABLE | SD_IE_CREM_ENABLE |
    153                 SD_IE_CINS_ENABLE | SD_IE_BRR_ENABLE | SD_IE_BWR_ENABLE |
    154                 SD_IE_TC_ENABLE | SD_IE_CC_ENABLE;
    155 
    156         /* Configure the operating voltage to 3.0 V */
    157         MMC1_REG(SD_HCTL) &= ~(SD_HCTL_SDVS);
    158         MMC1_REG(SD_HCTL) |= SD_HCTL_SDVS_VS30;
    159 
    160         /* Turn on the bus */
    161         MMC1_REG(SD_HCTL) |= SD_HCTL_SDBP;
    162         while (!(MMC1_REG(SD_HCTL) & SD_HCTL_SDBP));
    163 
    164         /* Enable the internal clock */
    165         MMC1_REG(SD_SYSCTL) |= SD_SYSCTL_ICE;
    166 
    167         /* Configure Clock Frequency Select to 100 KHz */
    168         MMC1_REG(SD_SYSCTL) = (MMC1_REG(SD_SYSCTL) & ~SD_SYSCTL_CLKD) | (960 << 6);
    169 
    170         /* Wait for clock to stabilize */
    171         while (!(MMC1_REG(SD_SYSCTL) & SD_SYSCTL_ICS));
    172 
    173         /* Configure SD_SYSCONFIG */
    174         MMC1_REG(SD_SYSCONFIG) &= ~(SD_SYSCONFIG_CLOCKACTIVITY | SD_SYSCONFIG_SIDLEMODE);
    175         MMC1_REG(SD_SYSCONFIG) |= SD_SYSCONFIG_SIDLEMODE_WKUP | SD_SYSCONFIG_ENAWAKEUP_ENABLE |
    176                 SD_SYSCONFIG_AUTOIDLE_AUTOGATE;
    177 
    178         /* Enable the clock to the eMMC */
    179         MMC1_REG(SD_SYSCTL) |= SD_SYSCTL_CEN;
    180 
    181         /* Perform the Initialization Stream as specified in the AM335x TRM, Section 18.3.3.2
    182            "Card Detection, Identification, and Selection" */
    183         MMC1_REG(SD_CON) |= SD_CON_INIT;
    184         /* Clear the SD_STAT register */
    185         MMC1_REG(SD_STAT) = 0xFFFFFFFF;
    186         MMC1_REG(SD_ARG) = 0x00000000;
    187         MMC1_REG(SD_CMD) = 0x00000000;
    188         while (!(MMC1_REG(SD_STAT) & SD_STAT_CC));
    189         /* Clear CC flag in SD_STAT */
    190         MMC1_REG(SD_STAT) |= SD_STAT_CC;
    191         MMC1_REG(SD_CON) &= ~SD_CON_INIT;
    192 
    193         /* Clear the SD_STAT register */
    194         MMC1_REG(SD_STAT) = 0xFFFFFFFF;
    195 
    196         /* Enable open-drain mode until we enter Stand-by State as illustrated in the
    197            JEDEC JESD84-A43 Embedded MultiMediaCard Product Standard specification, Table 5 */
    198         MMC1_REG(SD_CON) |= SD_CON_OD;
    199 
    200         /* Send CMD0/GO_IDLE_STATE to reset the eMMC on MMC1 interface */
    201         arg = 0x00000000;
    202         cmd = SD_CMD_CMD0_GO_IDLE_STATE | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_NO_DATA_PRESENT |
    203                 SD_CMD_CICE_DISABLE | SD_CMD_CCCE_DISABLE | SD_CMD_RSP_TYPE_NO_RESPONSE;
    204         if (mmccmd(cmd, arg, resp) == -1)
    205                 return(-1);
    206 
    207         /* Send CMD1 and poll busy bit in response */
    208         do {
    209                 arg = 0x40FF8000;
    210                 cmd = SD_CMD_CMD1_SEND_OP_COND | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_NO_DATA_PRESENT |
    211                         SD_CMD_CICE_DISABLE | SD_CMD_CCCE_DISABLE | SD_CMD_RSP_TYPE_R3;
    212                 if (mmccmd(cmd, arg, resp) == -1)
    213                         return(-1);
    214         } while (!(MMC1_REG(SD_RSP10) & 0x80000000));
    215 
    216         /* Send CMD2, i.e. ALL_SEND_CID */
    217         arg = 0x00000000;
    218         cmd = SD_CMD_CMD2_ALL_SEND_CID | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_NO_DATA_PRESENT |
    219                 SD_CMD_CICE_DISABLE | SD_CMD_CCCE_ENABLE | SD_CMD_RSP_TYPE_R2;
    220         if (mmccmd(cmd, arg, resp) == -1)
    221                 return(-1);
    222 
    223         /* Set RCA of eMMC */
    224         mmcrca = 0x3A3A;
    225 
    226         /* Send CMD3 to set the relative card address (RCA) of the eMMC */
    227         arg = (mmcrca << 16) & 0xFFFF0000;
    228         cmd = SD_CMD_CMD3_SET_RELATIVE_ADDR | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_NO_DATA_PRESENT |
    229                 SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE | SD_CMD_RSP_TYPE_R1;
    230         if (mmccmd(cmd, arg, resp) == -1)
    231                 return(-1);
    232 
    233         /* Wait for the eMMC to enter Stand-by State */
    234         do {
    235                 /* Send CMD13 to get the status of the MMC */
    236                 arg = (mmcrca << 16) & 0xFFFF0000;
    237                 cmd = SD_CMD_CMD13_SEND_STATUS | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_NO_DATA_PRESENT |
    238                         SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE | SD_CMD_RSP_TYPE_R1;
    239                 if (mmccmd(cmd, arg, resp) == -1)
    240                         return(-1);
    241         } while ((resp[0] & SD_RSP10_R1_CURRENT_STATE) != SD_RSP10_R1_CURRENT_STATE_STANDBY);
    242 
    243         /* Disable open-drain mode */
    244         MMC1_REG(SD_CON) &= ~SD_CON_OD;
    245 
    246         /* Send CMD7 to put the eMMC into Transfer State */
    247         arg = (mmcrca << 16) & 0xFFFF0000;
    248         cmd = SD_CMD_CMD7_SELECT_DESELECT_CARD | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_NO_DATA_PRESENT |
    249                 SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE | SD_CMD_RSP_TYPE_R1;
    250         if (mmccmd(cmd, arg, resp) == -1)
    251                 return(-1);
    252 
    253         /* Wait for eMMC to enter Transfer State */
    254         do {
    255                 /* Send CMD13 to get the status of the eMMC */
    256                 arg = (mmcrca << 16) & 0xFFFF0000;
    257                 cmd = SD_CMD_CMD13_SEND_STATUS | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_NO_DATA_PRESENT |
    258                         SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE | SD_CMD_RSP_TYPE_R1;
    259                 if (mmccmd(cmd, arg, resp) == -1)
    260                         return(-1);
    261         } while ((resp[0] & SD_RSP10_R1_CURRENT_STATE) != SD_RSP10_R1_CURRENT_STATE_TRANSFER);
    262 
    263         /* Send CMD6 to change bus-width to 8-bits */
    264         arg = (3 << 24) | (183 << 16) | (2 << 8);
    265         cmd = SD_CMD_CMD6_SWITCH | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_NO_DATA_PRESENT |
    266                 SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE | SD_CMD_RSP_TYPE_R1B;
    267         if (mmccmd(cmd, arg, resp) == -1)
    268                 return(-1);
    269         while (!(MMC1_REG(SD_STAT) & SD_STAT_TC));
    270 
    271         /* Wait while CMD6 is still in effect, i.e. while eMMC is not in Transfer State */
    272         do {
    273                 arg = (mmcrca << 16) & 0xFFFF0000;
    274                 cmd = SD_CMD_CMD13_SEND_STATUS | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_NO_DATA_PRESENT |
    275                         SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE | SD_CMD_RSP_TYPE_R1;
    276                 if (mmccmd(cmd, arg, resp) == -1)
    277                         return(-1);
    278         } while ((resp[0] & SD_RSP10_R1_CURRENT_STATE) != SD_RSP10_R1_CURRENT_STATE_TRANSFER);
    279 
    280         /* Configure the MMC1 controller to use an 8-bit data width */
    281         MMC1_REG(SD_CON) |= SD_CON_DW8_8BIT;
    282 
    283         /* Send CMD6 to change to high-speed mode */
    284         arg = 0x03B90100;
    285         cmd = SD_CMD_CMD6_SWITCH | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_NO_DATA_PRESENT |
    286                 SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE | SD_CMD_RSP_TYPE_R1B;
    287         if (mmccmd(cmd, arg, resp) == -1)
    288                 return(-1);
    289         while (!(MMC1_REG(SD_STAT) & SD_STAT_TC));
    290 
    291         /* Wait while CMD6 is still in effect, i.e. while eMMC is not in Transfer State */
    292         do {
    293                 arg = (mmcrca << 16) & 0xFFFF0000;
    294                 cmd = SD_CMD_CMD13_SEND_STATUS | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_NO_DATA_PRESENT |
    295                         SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE | SD_CMD_RSP_TYPE_R1;
    296                 if (mmccmd(cmd, arg, resp) == -1)
    297                         return(-1);
    298         } while ((resp[0] & SD_RSP10_R1_CURRENT_STATE) != SD_RSP10_R1_CURRENT_STATE_TRANSFER);
    299 
    300         /* Change the clock frequency to 48 MHz and set the DTO to the maximum value setting */
    301         MMC1_REG(SD_SYSCTL) &= ~SD_SYSCTL_DTO;
    302         MMC1_REG(SD_SYSCTL) |= SD_SYSCTL_DTO_TCF_2_27;
    303         MMC1_REG(SD_SYSCTL) = (MMC1_REG(SD_SYSCTL) & ~SD_SYSCTL_CLKD) | (2 << 6);
    304 
    305         /* Wait for clock to stabilize */
    306         while ((MMC1_REG(SD_SYSCTL) & SD_SYSCTL_ICS) != SD_SYSCTL_ICS);
    307 
    308         /* Put the eMMC into Stand-by State */
    309         arg = 0x00000000;
    310         cmd = SD_CMD_CMD7_SELECT_DESELECT_CARD | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_NO_DATA_PRESENT |
    311                 SD_CMD_CICE_DISABLE | SD_CMD_CCCE_DISABLE | SD_CMD_RSP_TYPE_NO_RESPONSE;
    312         if (mmccmd(cmd, arg, resp) == -1)
    313                 return(-1);
    314 
    315         /* Wait for the eMMC to enter Stand-by State */
    316         do {
    317                 arg = (mmcrca << 16) & 0xFFFF0000;
    318                 cmd = SD_CMD_CMD13_SEND_STATUS | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_NO_DATA_PRESENT |
    319                         SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE | SD_CMD_RSP_TYPE_R1;
    320                 if (mmccmd(cmd, arg, resp) == -1)
    321                         return(-1);
    322         } while ((resp[0] & SD_RSP10_R1_CURRENT_STATE) != SD_RSP10_R1_CURRENT_STATE_STANDBY);
    323 
    324         return(0);
     137    uint32_t cmd, arg, resp[4];
     138
     139    /* Reset the MMC1 Controller */
     140    MMC1_REG(SD_SYSCONFIG) = SD_SYSCONFIG_SOFTRESET;
     141    while(!(MMC1_REG(SD_SYSSTATUS) & SD_SYSSTATUS_RESETDONE));
     142
     143    /* Reset the command and data lines */
     144    MMC1_REG(SD_SYSCTL) |= SD_SYSCTL_SRA;
     145    while(MMC1_REG(SD_SYSCTL) & SD_SYSCTL_SRA);
     146
     147    /* Configure the MMC1 controller capabilities to enable 3.0 V operating voltage */
     148    MMC1_REG(SD_CAPA) |= SD_CAPA_VS30;
     149
     150    /* Configure SD_IE register to update certain status bits in SD_STAT */
     151    MMC1_REG(SD_IE) = SD_IE_BADA_ENABLE | SD_IE_CERR_ENABLE | SD_IE_ACE_ENABLE |
     152                      SD_IE_DEB_ENABLE | SD_IE_DCRC_ENABLE | SD_IE_DTO_ENABLE | SD_IE_CIE_ENABLE |
     153                      SD_IE_CEB_ENABLE | SD_IE_CCRC_ENABLE | SD_IE_CIRQ_ENABLE | SD_IE_CREM_ENABLE |
     154                      SD_IE_CINS_ENABLE | SD_IE_BRR_ENABLE | SD_IE_BWR_ENABLE |
     155                      SD_IE_TC_ENABLE | SD_IE_CC_ENABLE;
     156
     157    /* Configure the operating voltage to 3.0 V */
     158    MMC1_REG(SD_HCTL) &= ~(SD_HCTL_SDVS);
     159    MMC1_REG(SD_HCTL) |= SD_HCTL_SDVS_VS30;
     160
     161    /* Turn on the bus */
     162    MMC1_REG(SD_HCTL) |= SD_HCTL_SDBP;
     163    while(!(MMC1_REG(SD_HCTL) & SD_HCTL_SDBP));
     164
     165    /* Enable the internal clock */
     166    MMC1_REG(SD_SYSCTL) |= SD_SYSCTL_ICE;
     167
     168    /* Configure Clock Frequency Select to 100 KHz */
     169    MMC1_REG(SD_SYSCTL) = (MMC1_REG(SD_SYSCTL) & ~SD_SYSCTL_CLKD) | (960 << 6);
     170
     171    /* Wait for clock to stabilize */
     172    while(!(MMC1_REG(SD_SYSCTL) & SD_SYSCTL_ICS));
     173
     174    /* Configure SD_SYSCONFIG */
     175    MMC1_REG(SD_SYSCONFIG) &= ~(SD_SYSCONFIG_CLOCKACTIVITY | SD_SYSCONFIG_SIDLEMODE);
     176    MMC1_REG(SD_SYSCONFIG) |= SD_SYSCONFIG_SIDLEMODE_WKUP | SD_SYSCONFIG_ENAWAKEUP_ENABLE |
     177                              SD_SYSCONFIG_AUTOIDLE_AUTOGATE;
     178
     179    /* Enable the clock to the eMMC */
     180    MMC1_REG(SD_SYSCTL) |= SD_SYSCTL_CEN;
     181
     182    /* Perform the Initialization Stream as specified in the AM335x TRM, Section 18.3.3.2
     183       "Card Detection, Identification, and Selection" */
     184    MMC1_REG(SD_CON) |= SD_CON_INIT;
     185    /* Clear the SD_STAT register */
     186    MMC1_REG(SD_STAT) = 0xFFFFFFFF;
     187    MMC1_REG(SD_ARG) = 0x00000000;
     188    MMC1_REG(SD_CMD) = 0x00000000;
     189    while(!(MMC1_REG(SD_STAT) & SD_STAT_CC));
     190    /* Clear CC flag in SD_STAT */
     191    MMC1_REG(SD_STAT) |= SD_STAT_CC;
     192    MMC1_REG(SD_CON) &= ~SD_CON_INIT;
     193
     194    /* Clear the SD_STAT register */
     195    MMC1_REG(SD_STAT) = 0xFFFFFFFF;
     196
     197    /* Enable open-drain mode until we enter Stand-by State as illustrated in the
     198       JEDEC JESD84-A43 Embedded MultiMediaCard Product Standard specification, Table 5 */
     199    MMC1_REG(SD_CON) |= SD_CON_OD;
     200
     201    /* Send CMD0/GO_IDLE_STATE to reset the eMMC on MMC1 interface */
     202    arg = 0x00000000;
     203    cmd = SD_CMD_CMD0_GO_IDLE_STATE | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_NO_DATA_PRESENT |
     204          SD_CMD_CICE_DISABLE | SD_CMD_CCCE_DISABLE | SD_CMD_RSP_TYPE_NO_RESPONSE;
     205    if(mmccmd(cmd, arg, resp) == -1) {
     206        return(-1);
     207    }
     208
     209    /* Send CMD1 and poll busy bit in response */
     210    do {
     211        arg = 0x40FF8000;
     212        cmd = SD_CMD_CMD1_SEND_OP_COND | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_NO_DATA_PRESENT |
     213              SD_CMD_CICE_DISABLE | SD_CMD_CCCE_DISABLE | SD_CMD_RSP_TYPE_R3;
     214        if(mmccmd(cmd, arg, resp) == -1) {
     215            return(-1);
     216        }
     217    } while(!(MMC1_REG(SD_RSP10) & 0x80000000));
     218
     219    /* Send CMD2, i.e. ALL_SEND_CID */
     220    arg = 0x00000000;
     221    cmd = SD_CMD_CMD2_ALL_SEND_CID | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_NO_DATA_PRESENT |
     222          SD_CMD_CICE_DISABLE | SD_CMD_CCCE_ENABLE | SD_CMD_RSP_TYPE_R2;
     223    if(mmccmd(cmd, arg, resp) == -1) {
     224        return(-1);
     225    }
     226
     227    /* Set RCA of eMMC */
     228    mmcrca = 0x3A3A;
     229
     230    /* Send CMD3 to set the relative card address (RCA) of the eMMC */
     231    arg = (mmcrca << 16) & 0xFFFF0000;
     232    cmd = SD_CMD_CMD3_SET_RELATIVE_ADDR | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_NO_DATA_PRESENT |
     233          SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE | SD_CMD_RSP_TYPE_R1;
     234    if(mmccmd(cmd, arg, resp) == -1) {
     235        return(-1);
     236    }
     237
     238    /* Wait for the eMMC to enter Stand-by State */
     239    do {
     240        /* Send CMD13 to get the status of the MMC */
     241        arg = (mmcrca << 16) & 0xFFFF0000;
     242        cmd = SD_CMD_CMD13_SEND_STATUS | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_NO_DATA_PRESENT |
     243              SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE | SD_CMD_RSP_TYPE_R1;
     244        if(mmccmd(cmd, arg, resp) == -1) {
     245            return(-1);
     246        }
     247    } while((resp[0] & SD_RSP10_R1_CURRENT_STATE) != SD_RSP10_R1_CURRENT_STATE_STANDBY);
     248
     249    /* Disable open-drain mode */
     250    MMC1_REG(SD_CON) &= ~SD_CON_OD;
     251
     252    /* Send CMD7 to put the eMMC into Transfer State */
     253    arg = (mmcrca << 16) & 0xFFFF0000;
     254    cmd = SD_CMD_CMD7_SELECT_DESELECT_CARD | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_NO_DATA_PRESENT |
     255          SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE | SD_CMD_RSP_TYPE_R1;
     256    if(mmccmd(cmd, arg, resp) == -1) {
     257        return(-1);
     258    }
     259
     260    /* Wait for eMMC to enter Transfer State */
     261    do {
     262        /* Send CMD13 to get the status of the eMMC */
     263        arg = (mmcrca << 16) & 0xFFFF0000;
     264        cmd = SD_CMD_CMD13_SEND_STATUS | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_NO_DATA_PRESENT |
     265              SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE | SD_CMD_RSP_TYPE_R1;
     266        if(mmccmd(cmd, arg, resp) == -1) {
     267            return(-1);
     268        }
     269    } while((resp[0] & SD_RSP10_R1_CURRENT_STATE) != SD_RSP10_R1_CURRENT_STATE_TRANSFER);
     270
     271    /* Send CMD6 to change bus-width to 8-bits */
     272    arg = (3 << 24) | (183 << 16) | (2 << 8);
     273    cmd = SD_CMD_CMD6_SWITCH | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_NO_DATA_PRESENT |
     274          SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE | SD_CMD_RSP_TYPE_R1B;
     275    if(mmccmd(cmd, arg, resp) == -1) {
     276        return(-1);
     277    }
     278    while(!(MMC1_REG(SD_STAT) & SD_STAT_TC));
     279
     280    /* Wait while CMD6 is still in effect, i.e. while eMMC is not in Transfer State */
     281    do {
     282        arg = (mmcrca << 16) & 0xFFFF0000;
     283        cmd = SD_CMD_CMD13_SEND_STATUS | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_NO_DATA_PRESENT |
     284              SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE | SD_CMD_RSP_TYPE_R1;
     285        if(mmccmd(cmd, arg, resp) == -1) {
     286            return(-1);
     287        }
     288    } while((resp[0] & SD_RSP10_R1_CURRENT_STATE) != SD_RSP10_R1_CURRENT_STATE_TRANSFER);
     289
     290    /* Configure the MMC1 controller to use an 8-bit data width */
     291    MMC1_REG(SD_CON) |= SD_CON_DW8_8BIT;
     292
     293    /* Send CMD6 to change to high-speed mode */
     294    arg = 0x03B90100;
     295    cmd = SD_CMD_CMD6_SWITCH | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_NO_DATA_PRESENT |
     296          SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE | SD_CMD_RSP_TYPE_R1B;
     297    if(mmccmd(cmd, arg, resp) == -1) {
     298        return(-1);
     299    }
     300    while(!(MMC1_REG(SD_STAT) & SD_STAT_TC));
     301
     302    /* Wait while CMD6 is still in effect, i.e. while eMMC is not in Transfer State */
     303    do {
     304        arg = (mmcrca << 16) & 0xFFFF0000;
     305        cmd = SD_CMD_CMD13_SEND_STATUS | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_NO_DATA_PRESENT |
     306              SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE | SD_CMD_RSP_TYPE_R1;
     307        if(mmccmd(cmd, arg, resp) == -1) {
     308            return(-1);
     309        }
     310    } while((resp[0] & SD_RSP10_R1_CURRENT_STATE) != SD_RSP10_R1_CURRENT_STATE_TRANSFER);
     311
     312    /* Change the clock frequency to 48 MHz and set the DTO to the maximum value setting */
     313    MMC1_REG(SD_SYSCTL) &= ~SD_SYSCTL_DTO;
     314    MMC1_REG(SD_SYSCTL) |= SD_SYSCTL_DTO_TCF_2_27;
     315    MMC1_REG(SD_SYSCTL) = (MMC1_REG(SD_SYSCTL) & ~SD_SYSCTL_CLKD) | (2 << 6);
     316
     317    /* Wait for clock to stabilize */
     318    while((MMC1_REG(SD_SYSCTL) & SD_SYSCTL_ICS) != SD_SYSCTL_ICS);
     319
     320    /* Put the eMMC into Stand-by State */
     321    arg = 0x00000000;
     322    cmd = SD_CMD_CMD7_SELECT_DESELECT_CARD | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_NO_DATA_PRESENT |
     323          SD_CMD_CICE_DISABLE | SD_CMD_CCCE_DISABLE | SD_CMD_RSP_TYPE_NO_RESPONSE;
     324    if(mmccmd(cmd, arg, resp) == -1) {
     325        return(-1);
     326    }
     327
     328    /* Wait for the eMMC to enter Stand-by State */
     329    do {
     330        arg = (mmcrca << 16) & 0xFFFF0000;
     331        cmd = SD_CMD_CMD13_SEND_STATUS | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_NO_DATA_PRESENT |
     332              SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE | SD_CMD_RSP_TYPE_R1;
     333        if(mmccmd(cmd, arg, resp) == -1) {
     334            return(-1);
     335        }
     336    } while((resp[0] & SD_RSP10_R1_CURRENT_STATE) != SD_RSP10_R1_CURRENT_STATE_STANDBY);
     337
     338    return(0);
    325339}
    326340
     
    328342mmcRead(int interface, char *buf, int blknum, int blkcnt)
    329343{
    330         uint32_t cmd, arg, resp[4];
    331         uint32_t *wordptr = (uint32_t *) buf;
    332         int byteindex;
    333 
    334         /* Get the SD card's status via CMD13 */
    335         arg = (mmcrca << 16) & 0xFFFF0000;
    336         cmd = SD_CMD_CMD13_SEND_STATUS | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_NO_DATA_PRESENT |
    337                 SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE | SD_CMD_RSP_TYPE_R1;
    338         if (mmccmd(cmd, arg, resp) == -1)
    339                 return(-1);
    340 
    341         /* Ensure that the card is in Transfer State before proceeding */
    342         if ((resp[0] & SD_RSP10_R1_CURRENT_STATE) != SD_RSP10_R1_CURRENT_STATE_TRANSFER) {
    343                 arg = (mmcrca << 16) & 0xFFFF0000;
    344                 cmd = SD_CMD_CMD7_SELECT_DESELECT_CARD | SD_CMD_CMD_TYPE_NORMAL |
    345                         SD_CMD_DP_NO_DATA_PRESENT | SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE |
    346                         SD_CMD_RSP_TYPE_R1B;
    347                 if (mmccmd(cmd, arg, resp) == -1)
    348                         return(-1);
    349 
    350                 /* Wait for the SD card to enter Transfer State */
    351                 do {
    352                         arg = (mmcrca << 16) & 0xFFFF0000;
    353                         cmd = SD_CMD_CMD13_SEND_STATUS | SD_CMD_CMD_TYPE_NORMAL |
    354                                 SD_CMD_DP_NO_DATA_PRESENT | SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE |
    355                                 SD_CMD_RSP_TYPE_R1;
    356                         if (mmccmd(cmd, arg, resp) == -1)
    357                                 return(-1);
    358                 } while ((resp[0] & SD_RSP10_R1_CURRENT_STATE) != SD_RSP10_R1_CURRENT_STATE_TRANSFER);
    359         }
    360 
    361         /* Set the block length and the number of blocks to read */
    362         MMC1_REG(SD_BLK) = 0x200 | (blkcnt << 16);
    363         /* Read multiple blocks via CMD18 */
    364         arg = blknum;
    365         cmd = SD_CMD_CMD18_READ_MULTIPLE_BLOCK | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_DATA_PRESENT |
    366                 SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE | SD_CMD_RSP_TYPE_R1 | SD_CMD_MSBS_MULTIPLE |
    367                 SD_CMD_DDIR_READ | SD_CMD_ACEN_CMD12_ENABLE | SD_CMD_BCE_ENABLE;
    368         if (mmccmd(cmd, arg, resp) == -1)
    369                 return(-1);
    370 
    371         /* Check the data buffer to see if there is data to be read */
    372         do {
    373                 while (!(MMC1_REG(SD_STAT) & SD_STAT_BRR));
    374 
    375                 /* Clear the BRR status bit in SD_STAT */
    376                 MMC1_REG(SD_STAT) |= SD_STAT_BRR;
    377 
    378                 for (byteindex = 0; byteindex < (0x200 / 4); byteindex++) {
    379                         *wordptr = MMC1_REG(SD_DATA);
    380                         wordptr++;
    381                 }
    382         } while (!(MMC1_REG(SD_STAT) & SD_STAT_TC));
    383 
    384         /* Put the eMMC into Stand-by State */
    385         arg = 0;
    386         cmd = SD_CMD_CMD7_SELECT_DESELECT_CARD | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_NO_DATA_PRESENT |
    387                 SD_CMD_CICE_DISABLE | SD_CMD_CCCE_DISABLE | SD_CMD_RSP_TYPE_NO_RESPONSE;
    388         if (mmccmd(cmd, arg, resp) == -1)
    389                 return(-1);
    390 
    391         /* Wait for the eMMC to enter Stand-by State */
    392         do {
    393                 arg = (mmcrca << 16) & 0xFFFF0000;
    394                 cmd = SD_CMD_CMD13_SEND_STATUS | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_NO_DATA_PRESENT |
    395                         SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE | SD_CMD_RSP_TYPE_R1;
    396                 if (mmccmd(cmd, arg, resp) == -1)
    397                         return(-1);
    398         } while ((resp[0] & SD_RSP10_R1_CURRENT_STATE) != SD_RSP10_R1_CURRENT_STATE_STANDBY);
    399 
    400         return(0);
     344    uint32_t cmd, arg, resp[4];
     345    uint32_t *wordptr = (uint32_t *) buf;
     346    int byteindex;
     347
     348    /* Get the SD card's status via CMD13 */
     349    arg = (mmcrca << 16) & 0xFFFF0000;
     350    cmd = SD_CMD_CMD13_SEND_STATUS | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_NO_DATA_PRESENT |
     351          SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE | SD_CMD_RSP_TYPE_R1;
     352    if(mmccmd(cmd, arg, resp) == -1) {
     353        return(-1);
     354    }
     355
     356    /* Ensure that the card is in Transfer State before proceeding */
     357    if((resp[0] & SD_RSP10_R1_CURRENT_STATE) != SD_RSP10_R1_CURRENT_STATE_TRANSFER) {
     358        arg = (mmcrca << 16) & 0xFFFF0000;
     359        cmd = SD_CMD_CMD7_SELECT_DESELECT_CARD | SD_CMD_CMD_TYPE_NORMAL |
     360              SD_CMD_DP_NO_DATA_PRESENT | SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE |
     361              SD_CMD_RSP_TYPE_R1B;
     362        if(mmccmd(cmd, arg, resp) == -1) {
     363            return(-1);
     364        }
     365
     366        /* Wait for the SD card to enter Transfer State */
     367        do {
     368            arg = (mmcrca << 16) & 0xFFFF0000;
     369            cmd = SD_CMD_CMD13_SEND_STATUS | SD_CMD_CMD_TYPE_NORMAL |
     370                  SD_CMD_DP_NO_DATA_PRESENT | SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE |
     371                  SD_CMD_RSP_TYPE_R1;
     372            if(mmccmd(cmd, arg, resp) == -1) {
     373                return(-1);
     374            }
     375        } while((resp[0] & SD_RSP10_R1_CURRENT_STATE) != SD_RSP10_R1_CURRENT_STATE_TRANSFER);
     376    }
     377
     378    /* Set the block length and the number of blocks to read */
     379    MMC1_REG(SD_BLK) = 0x200 | (blkcnt << 16);
     380    /* Read multiple blocks via CMD18 */
     381    arg = blknum;
     382    cmd = SD_CMD_CMD18_READ_MULTIPLE_BLOCK | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_DATA_PRESENT |
     383          SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE | SD_CMD_RSP_TYPE_R1 | SD_CMD_MSBS_MULTIPLE |
     384          SD_CMD_DDIR_READ | SD_CMD_ACEN_CMD12_ENABLE | SD_CMD_BCE_ENABLE;
     385    if(mmccmd(cmd, arg, resp) == -1) {
     386        return(-1);
     387    }
     388
     389    /* Check the data buffer to see if there is data to be read */
     390    do {
     391        while(!(MMC1_REG(SD_STAT) & SD_STAT_BRR));
     392
     393        /* Clear the BRR status bit in SD_STAT */
     394        MMC1_REG(SD_STAT) |= SD_STAT_BRR;
     395
     396        for(byteindex = 0; byteindex < (0x200 / 4); byteindex++) {
     397            *wordptr = MMC1_REG(SD_DATA);
     398            wordptr++;
     399        }
     400    } while(!(MMC1_REG(SD_STAT) & SD_STAT_TC));
     401
     402    /* Put the eMMC into Stand-by State */
     403    arg = 0;
     404    cmd = SD_CMD_CMD7_SELECT_DESELECT_CARD | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_NO_DATA_PRESENT |
     405          SD_CMD_CICE_DISABLE | SD_CMD_CCCE_DISABLE | SD_CMD_RSP_TYPE_NO_RESPONSE;
     406    if(mmccmd(cmd, arg, resp) == -1) {
     407        return(-1);
     408    }
     409
     410    /* Wait for the eMMC to enter Stand-by State */
     411    do {
     412        arg = (mmcrca << 16) & 0xFFFF0000;
     413        cmd = SD_CMD_CMD13_SEND_STATUS | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_NO_DATA_PRESENT |
     414              SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE | SD_CMD_RSP_TYPE_R1;
     415        if(mmccmd(cmd, arg, resp) == -1) {
     416            return(-1);
     417        }
     418    } while((resp[0] & SD_RSP10_R1_CURRENT_STATE) != SD_RSP10_R1_CURRENT_STATE_STANDBY);
     419
     420    return(0);
    401421}
    402422
     
    404424mmcWrite(int interface, char *buf, int blknum, int blkcnt)
    405425{
    406         uint32_t cmd, arg, resp[4];
    407         uint32_t *wordptr = (uint32_t *) buf;
    408         int byteindex;
    409 
    410         /* Get the eMMC status by sending CMD13 */
    411         arg = (mmcrca << 16) & 0xFFFF0000;
    412         cmd = SD_CMD_CMD13_SEND_STATUS | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_NO_DATA_PRESENT |
    413                 SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE | SD_CMD_RSP_TYPE_R1;
    414         if (mmccmd(cmd, arg, resp) == -1)
    415                 return(-1);
    416 
    417         /* Ensure that the eMMC is in the Transfer State before proceeding */
    418         if ((resp[0] & SD_RSP10_R1_CURRENT_STATE) != SD_RSP10_R1_CURRENT_STATE_TRANSFER) {
    419                 arg = (mmcrca << 16) & 0xFFFF0000;
    420                 cmd  = SD_CMD_CMD7_SELECT_DESELECT_CARD | SD_CMD_CMD_TYPE_NORMAL |
    421                         SD_CMD_DP_NO_DATA_PRESENT | SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE |
    422                         SD_CMD_RSP_TYPE_R1B;
    423                 if (mmccmd(cmd, arg, resp) == -1)
    424                         return(-1);
    425 
    426                 /* Wait for eMMC to enter Transfer State */
    427                 do {
    428                         arg = (mmcrca << 16) & 0xFFFF0000;
    429                         cmd = SD_CMD_CMD13_SEND_STATUS | SD_CMD_CMD_TYPE_NORMAL |
    430                                 SD_CMD_DP_NO_DATA_PRESENT | SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE |
    431                                 SD_CMD_RSP_TYPE_R1;
    432                         if (mmccmd(cmd, arg, resp) == -1)
    433                                 return(-1);
    434                 } while ((resp[0] & SD_RSP10_R1_CURRENT_STATE) != SD_RSP10_R1_CURRENT_STATE_TRANSFER);
    435         }
    436 
    437         /* Set the block length in bytes and the number of blocks to write to the SD card */
    438         MMC1_REG(SD_BLK) = 0x200 | (blkcnt << 16);
    439         /* Send CMD25, that is write the number of blocks specified in 'blkcount' from 'buf' to the
    440          * location that is 512 byte aligned in the SD card specified by the block number 'blknum'
    441          */
    442         arg = blknum;
    443         cmd = SD_CMD_CMD25_WRITE_MULTIPLE_BLOCK | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_DATA_PRESENT |
    444                 SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE | SD_CMD_RSP_TYPE_R1 | SD_CMD_MSBS_MULTIPLE |
    445                 SD_CMD_DDIR_WRITE | SD_CMD_ACEN_CMD12_ENABLE | SD_CMD_BCE_ENABLE;
    446         if (mmccmd(cmd, arg, resp) == -1)
    447                 return(-1);
    448 
    449         /* Write the data */
    450         do {
    451                 /* Wait until data is ready to be written */
    452                 while (!(MMC1_REG(SD_STAT) & (SD_STAT_BWR | SD_STAT_TC)));
    453 
    454                 if (MMC1_REG(SD_STAT) & SD_STAT_TC)
    455                         break;
    456 
    457                 /* Clear the BWR status bit in SD_STAT */
    458                 MMC1_REG(SD_STAT) |= SD_STAT_BWR;
    459 
    460                 for (byteindex = 0; byteindex < (0x200 / 4); byteindex++)
    461                         MMC1_REG(SD_DATA) = *wordptr++;
    462         } while (!(MMC1_REG(SD_STAT) & SD_STAT_TC));
    463 
    464         /* Put the eMMC into Stand-by State */
    465         arg = 0x00000000;
    466         cmd = SD_CMD_CMD7_SELECT_DESELECT_CARD | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_NO_DATA_PRESENT |
    467                 SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE | SD_CMD_RSP_TYPE_NO_RESPONSE;
    468         if (mmccmd(cmd, arg, resp) == -1)
    469                 return(-1);
    470 
    471         /* Wait for eMMC to enter Stand-by State */
    472         do {
    473                 arg = (mmcrca << 16) & 0xFFFF0000;
    474                 cmd  = SD_CMD_CMD13_SEND_STATUS | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_NO_DATA_PRESENT |
    475                         SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE | SD_CMD_RSP_TYPE_R1;
    476                 if (mmccmd(cmd, arg, resp) == -1)
    477                         return(-1);
    478         } while ((resp[0] & SD_RSP10_R1_CURRENT_STATE) != SD_RSP10_R1_CURRENT_STATE_STANDBY);
    479 
    480         return(0);
     426    uint32_t cmd, arg, resp[4];
     427    uint32_t *wordptr = (uint32_t *) buf;
     428    int byteindex;
     429
     430    /* Get the eMMC status by sending CMD13 */
     431    arg = (mmcrca << 16) & 0xFFFF0000;
     432    cmd = SD_CMD_CMD13_SEND_STATUS | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_NO_DATA_PRESENT |
     433          SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE | SD_CMD_RSP_TYPE_R1;
     434    if(mmccmd(cmd, arg, resp) == -1) {
     435        return(-1);
     436    }
     437
     438    /* Ensure that the eMMC is in the Transfer State before proceeding */
     439    if((resp[0] & SD_RSP10_R1_CURRENT_STATE) != SD_RSP10_R1_CURRENT_STATE_TRANSFER) {
     440        arg = (mmcrca << 16) & 0xFFFF0000;
     441        cmd  = SD_CMD_CMD7_SELECT_DESELECT_CARD | SD_CMD_CMD_TYPE_NORMAL |
     442               SD_CMD_DP_NO_DATA_PRESENT | SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE |
     443               SD_CMD_RSP_TYPE_R1B;
     444        if(mmccmd(cmd, arg, resp) == -1) {
     445            return(-1);
     446        }
     447
     448        /* Wait for eMMC to enter Transfer State */
     449        do {
     450            arg = (mmcrca << 16) & 0xFFFF0000;
     451            cmd = SD_CMD_CMD13_SEND_STATUS | SD_CMD_CMD_TYPE_NORMAL |
     452                  SD_CMD_DP_NO_DATA_PRESENT | SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE |
     453                  SD_CMD_RSP_TYPE_R1;
     454            if(mmccmd(cmd, arg, resp) == -1) {
     455                return(-1);
     456            }
     457        } while((resp[0] & SD_RSP10_R1_CURRENT_STATE) != SD_RSP10_R1_CURRENT_STATE_TRANSFER);
     458    }
     459
     460    /* Set the block length in bytes and the number of blocks to write to the SD card */
     461    MMC1_REG(SD_BLK) = 0x200 | (blkcnt << 16);
     462    /* Send CMD25, that is write the number of blocks specified in 'blkcount' from 'buf' to the
     463     * location that is 512 byte aligned in the SD card specified by the block number 'blknum'
     464     */
     465    arg = blknum;
     466    cmd = SD_CMD_CMD25_WRITE_MULTIPLE_BLOCK | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_DATA_PRESENT |
     467          SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE | SD_CMD_RSP_TYPE_R1 | SD_CMD_MSBS_MULTIPLE |
     468          SD_CMD_DDIR_WRITE | SD_CMD_ACEN_CMD12_ENABLE | SD_CMD_BCE_ENABLE;
     469    if(mmccmd(cmd, arg, resp) == -1) {
     470        return(-1);
     471    }
     472
     473    /* Write the data */
     474    do {
     475        /* Wait until data is ready to be written */
     476        while(!(MMC1_REG(SD_STAT) & (SD_STAT_BWR | SD_STAT_TC)));
     477
     478        if(MMC1_REG(SD_STAT) & SD_STAT_TC) {
     479            break;
     480        }
     481
     482        /* Clear the BWR status bit in SD_STAT */
     483        MMC1_REG(SD_STAT) |= SD_STAT_BWR;
     484
     485        for(byteindex = 0; byteindex < (0x200 / 4); byteindex++) {
     486            MMC1_REG(SD_DATA) = *wordptr++;
     487        }
     488    } while(!(MMC1_REG(SD_STAT) & SD_STAT_TC));
     489
     490    /* Put the eMMC into Stand-by State */
     491    arg = 0x00000000;
     492    cmd = SD_CMD_CMD7_SELECT_DESELECT_CARD | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_NO_DATA_PRESENT |
     493          SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE | SD_CMD_RSP_TYPE_NO_RESPONSE;
     494    if(mmccmd(cmd, arg, resp) == -1) {
     495        return(-1);
     496    }
     497
     498    /* Wait for eMMC to enter Stand-by State */
     499    do {
     500        arg = (mmcrca << 16) & 0xFFFF0000;
     501        cmd  = SD_CMD_CMD13_SEND_STATUS | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_NO_DATA_PRESENT |
     502               SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE | SD_CMD_RSP_TYPE_R1;
     503        if(mmccmd(cmd, arg, resp) == -1) {
     504            return(-1);
     505        }
     506    } while((resp[0] & SD_RSP10_R1_CURRENT_STATE) != SD_RSP10_R1_CURRENT_STATE_STANDBY);
     507
     508    return(0);
    481509}
    482510
     
    484512mmcInstalled(int interface)
    485513{
    486         return(1);
     514    return(1);
    487515}
  • ports/beagleboneblack/am335x_sd.c

    rd355df2 r976c170  
    1616sdcmd(uint32_t cmd, uint32_t arg, uint32_t resp[4])
    1717{
    18         /* Clear the SD_STAT register for proper update of status bits after CMD invocation */
    19         MMCHS0_REG(SD_STAT) = 0xFFFFFFFF;
    20 
    21         MMCHS0_REG(SD_ARG) = arg;
    22         MMCHS0_REG(SD_CMD) = cmd;
    23 
    24         /* CMDx complete? */
    25         while (!(MMCHS0_REG(SD_STAT) & (SD_STAT_CC | SD_STAT_ERRI)));
    26 
    27         resp[0] = MMCHS0_REG(SD_RSP10);
    28         resp[1] = MMCHS0_REG(SD_RSP32);
    29         resp[2] = MMCHS0_REG(SD_RSP54);
    30         resp[3] = MMCHS0_REG(SD_RSP76);
    31 
    32         /* CMDx error? */
    33         if (MMCHS0_REG(SD_STAT) & SD_STAT_ERRI)
    34                 return(-1);
    35         else
    36                 return(0);
     18    /* Clear the SD_STAT register for proper update of status bits after CMD invocation */
     19    MMCHS0_REG(SD_STAT) = 0xFFFFFFFF;
     20
     21    MMCHS0_REG(SD_ARG) = arg;
     22    MMCHS0_REG(SD_CMD) = cmd;
     23
     24    /* CMDx complete? */
     25    while(!(MMCHS0_REG(SD_STAT) & (SD_STAT_CC | SD_STAT_ERRI)));
     26
     27    resp[0] = MMCHS0_REG(SD_RSP10);
     28    resp[1] = MMCHS0_REG(SD_RSP32);
     29    resp[2] = MMCHS0_REG(SD_RSP54);
     30    resp[3] = MMCHS0_REG(SD_RSP76);
     31
     32    /* CMDx error? */
     33    if(MMCHS0_REG(SD_STAT) & SD_STAT_ERRI) {
     34        return(-1);
     35    } else {
     36        return(0);
     37    }
    3738}
    3839
     
    4041sdCardCmd(int interface, int cmd, unsigned long arg, unsigned char *resp)
    4142{
    42         return(-1);
     43    return(-1);
    4344}
    4445
     
    4647sdInit(int interface, int verbosity)
    4748{
    48         uint32_t cmd, arg, resp[4];
    49 
    50         /* Reset the MMC/SD controller */
    51         MMCHS0_REG(SD_SYSCONFIG) = SD_SYSCONFIG_SOFTRESET;
    52         while (!(MMCHS0_REG(SD_SYSSTATUS) & SD_SYSSTATUS_RESETDONE));
    53 
    54         /* Reset the command and data lines */
    55         MMCHS0_REG(SD_SYSCTL) |= SD_SYSCTL_SRA;
    56         while (MMCHS0_REG(SD_SYSCTL) & SD_SYSCTL_SRA);
    57 
    58         /* Configure the MMC/SD controller capabilities to enable 3.0 V operating voltage */
    59         MMCHS0_REG(SD_CAPA) = SD_CAPA_VS30;
    60 
    61         /* Configure SD_IE register to update certain status bits in SD_STAT */
    62         MMCHS0_REG(SD_IE) = SD_IE_BADA_ENABLE | SD_IE_CERR_ENABLE | SD_IE_ACE_ENABLE |
    63                 SD_IE_DEB_ENABLE | SD_IE_DCRC_ENABLE | SD_IE_DTO_ENABLE | SD_IE_CIE_ENABLE |
    64                 SD_IE_CEB_ENABLE | SD_IE_CCRC_ENABLE | SD_IE_CIRQ_ENABLE | SD_IE_CREM_ENABLE |
    65                 SD_IE_CINS_ENABLE | SD_IE_BRR_ENABLE | SD_IE_BWR_ENABLE |
    66                 SD_IE_TC_ENABLE | SD_IE_CC_ENABLE;
    67 
    68         /* Disable open-drain mode (only used for MMC cards) and 8-bit data width  */
    69         MMCHS0_REG(SD_CON) &= ~(SD_CON_OD | SD_CON_DW8);
    70 
    71         /* Configure the operating voltage to 3.0 V */
    72         MMCHS0_REG(SD_HCTL) &= ~(SD_HCTL_SDVS);
    73         MMCHS0_REG(SD_HCTL) |= SD_HCTL_SDVS_VS30;
    74 
    75         /* Set the data width to 4-bits */
    76         MMCHS0_REG(SD_HCTL) |= SD_HCTL_DTW;
    77 
    78         /* Turn on the bus */
    79         MMCHS0_REG(SD_HCTL) |= SD_HCTL_SDBP;
    80         while (!(MMCHS0_REG(SD_HCTL) & SD_HCTL_SDBP));
    81 
    82         /* Enable the internal clock */
    83         MMCHS0_REG(SD_SYSCTL) |= SD_SYSCTL_ICE;
    84 
    85         /* Configure Clock Frequency Select to 100 KHz */
    86         MMCHS0_REG(SD_SYSCTL) = (MMCHS0_REG(SD_SYSCTL) & ~(SD_SYSCTL_CLKD)) | (960 << 6);
    87 
    88         /* Wait for clock to stabilize */
    89         while (!(MMCHS0_REG(SD_SYSCTL) & SD_SYSCTL_ICS));
    90 
    91         /* Configure SD_SYSCONFIG */
    92         MMCHS0_REG(SD_SYSCONFIG) &= ~(SD_SYSCONFIG_CLOCKACTIVITY | SD_SYSCONFIG_SIDLEMODE);
    93         MMCHS0_REG(SD_SYSCONFIG) |= SD_SYSCONFIG_SIDLEMODE_WKUP | SD_SYSCONFIG_ENAWAKEUP_ENABLE |
    94                 SD_SYSCONFIG_AUTOIDLE_AUTOGATE;
    95 
    96         /* Enable the clock to the SD card */
    97         MMCHS0_REG(SD_SYSCTL) |= SD_SYSCTL_CEN_ENABLE;
    98 
    99         /* Perform the Initialization Stream as specified in the AM335x TRM, Section 18.3.3.2
    100            "Card Detection, Identicication, and Selection" */
    101         MMCHS0_REG(SD_CON) |= SD_CON_INIT;
    102         /* Clear the SD_STAT register */
    103         MMCHS0_REG(SD_STAT) = 0xFFFFFFFF;
    104         MMCHS0_REG(SD_ARG) = 0x00000000;
    105         MMCHS0_REG(SD_CMD) = 0x00000000;
    106         while (!(MMCHS0_REG(SD_STAT) & SD_STAT_CC));
    107         /* Clear CC flag in SD_STAT */
    108         MMCHS0_REG(SD_STAT) |= SD_STAT_CC;
    109         MMCHS0_REG(SD_CON) &= ~SD_CON_INIT;
    110 
    111         /* Change the clock frequency to 6 MHz and set the DTO to the maximum value setting */
    112         MMCHS0_REG(SD_SYSCTL) &= ~SD_SYSCTL_DTO;
    113         MMCHS0_REG(SD_SYSCTL) |= SD_SYSCTL_DTO_TCF_2_27;
    114         MMCHS0_REG(SD_SYSCTL) = (MMCHS0_REG(SD_SYSCTL) & ~SD_SYSCTL_CLKD) | (16 << 6);
    115 
    116         /* Wait for clock to stabilize */
    117         while ((MMCHS0_REG(SD_SYSCTL) & SD_SYSCTL_ICS) != SD_SYSCTL_ICS);
    118 
    119         /* Send CMD0/GO_IDLE_STATE to reset the SD card connected to MMC0 interface */
    120         arg = 0x00000000;
    121         cmd = SD_CMD_CMD0_GO_IDLE_STATE | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_NO_DATA_PRESENT |
    122                 SD_CMD_CICE_DISABLE | SD_CMD_CCCE_DISABLE | SD_CMD_RSP_TYPE_NO_RESPONSE;
    123         if (sdcmd(cmd, arg, resp) == -1)
    124                 return(-1);
    125 
    126         /* Send CMD8/SEND_IF_COND to verify that the SD card satisfies MMC/SD controller
    127            requirements */
    128         arg = 0x00000188;
    129         cmd = SD_CMD_CMD8_SEND_IF_COND | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_NO_DATA_PRESENT |
    130                 SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE | SD_CMD_RSP_TYPE_R7;
    131         if (sdcmd(cmd, arg, resp) == -1)
    132                 return(-1);
    133 
    134         /* Determine what type of SD card is connected, i.e. standard capacity, high capacity, etc.
    135          * We perform a CMD55/ACMD41 loop until the "Card power up status bit" is set in the OCR
    136          * register from the SD card to determine when we have a valid response */
    137         do {
    138                 arg = 0x00000000;
    139                 cmd = SD_CMD_CMD55_APP_CMD | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_NO_DATA_PRESENT |
    140                         SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE | SD_CMD_RSP_TYPE_R1;
    141                 if (sdcmd(cmd, arg, resp) == -1)
    142                         return(-1);
    143 
    144                 arg = 0x40060000;
    145                 cmd = SD_CMD_ACMD41_SD_SEND_OP_COND | SD_CMD_CMD_TYPE_NORMAL |
    146                         SD_CMD_DP_NO_DATA_PRESENT | SD_CMD_CICE_DISABLE | SD_CMD_CCCE_DISABLE |
    147                         SD_CMD_RSP_TYPE_R3;
    148                 if (sdcmd(cmd, arg, resp) == -1)
    149                         return(-1);
    150         } while (!(resp[0] & SD_RSP10_R3_CARD_POWER_UP_STATUS));
    151 
    152         /* Check SD_RSP10 to determine whether the card connected is high capacity or not */
    153         if (resp[0] & SD_RSP10_R3_CARD_CAPACITY_STATUS)
    154                 sdInfoTbl[interface].highcapacity = 1;
    155         else
    156                 sdInfoTbl[interface].highcapacity = 0;
    157 
    158         /* Send CMD2 to get SD's CID and to put the card into Identification State */
    159         arg = 0x00000000;
    160         cmd = SD_CMD_CMD2_ALL_SEND_CID | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_NO_DATA_PRESENT |
    161                 SD_CMD_CICE_DISABLE | SD_CMD_CCCE_ENABLE | SD_CMD_RSP_TYPE_R2;
    162         if (sdcmd(cmd, arg, resp) == -1)
    163                 return(-1);
    164 
    165         /* Send CMD3, i.e. request new relative address (RCA) and to put the card into
    166            Stand-by State */
    167         arg = 0x00000000;
    168         cmd = SD_CMD_CMD3_SEND_RELATIVE_ADDR | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_NO_DATA_PRESENT |
    169                 SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE | SD_CMD_RSP_TYPE_R6;
    170         if (sdcmd(cmd, arg, resp) == -1)
    171                 return(-1);
    172 
    173         /* Save the RCA published from the SD card, this will be used in future CMDx commands */
    174         sdrca = (MMCHS0_REG(SD_RSP10) >> 16) & 0xFFFF;
    175 
    176         /* Wait for the SD card to enter Stand-by State */
    177         do {
    178                 arg = (sdrca << 16) & 0xFFFF0000;
    179                 cmd = SD_CMD_CMD13_SEND_STATUS | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_NO_DATA_PRESENT |
    180                         SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE | SD_CMD_RSP_TYPE_R1;
    181                 if (sdcmd(cmd, arg, resp) == -1)
    182                         return(-1);
    183         } while ((resp[0] & SD_RSP10_R1_CURRENT_STATE) != SD_RSP10_R1_CURRENT_STATE_STANDBY);
    184 
    185         /* Put the card with the RCA obtained previously into Transfer State via CMD7 */
    186         arg = (sdrca << 16) & 0xFFFF0000;
    187         cmd = SD_CMD_CMD7_SELECT_DESELECT_CARD | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_NO_DATA_PRESENT |
    188                 SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE | SD_CMD_RSP_TYPE_R1B;
    189         if (sdcmd(cmd, arg, resp) == -1)
    190                 return(-1);
    191 
    192         /* Wait for the SD card to enter Transfer State */
    193         do {
    194                 arg = (sdrca << 16) & 0xFFFF0000;
    195                 cmd = SD_CMD_CMD13_SEND_STATUS | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_NO_DATA_PRESENT |
    196                         SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE | SD_CMD_RSP_TYPE_R1;
    197                 if (sdcmd(cmd, arg, resp) == -1)
    198                         return(-1);
    199         } while ((resp[0] & SD_RSP10_R1_CURRENT_STATE) != SD_RSP10_R1_CURRENT_STATE_TRANSFER);
    200 
    201         /* Set the bus-width to 4-bits */
    202 
    203         /* Send CMD55 to get ready to configure the bus-width via ACMD6 */
    204         arg = (sdrca << 16) & 0xFFFF0000;
    205         cmd = SD_CMD_CMD55_APP_CMD | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_NO_DATA_PRESENT |
    206                 SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE | SD_CMD_RSP_TYPE_R1;
    207         if (sdcmd(cmd, arg, resp) == -1)
    208                 return(-1);
    209 
    210         /* Send ACMD6, SET_BUS_WIDTH to set the bus-width to 4-bits */
    211         arg = 0x00000002;
    212         cmd = SD_CMD_ACMD6_SET_BUS_WIDTH | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_NO_DATA_PRESENT |
    213                 SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE | SD_CMD_RSP_TYPE_R1;
    214         if (sdcmd(cmd, arg, resp) == -1)
    215                 return(-1);
    216 
    217         /* Put the SD card into Stand-by State */
    218         arg = 0x00000000;
    219         cmd = SD_CMD_CMD7_SELECT_DESELECT_CARD | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_NO_DATA_PRESENT |
    220                 SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE | SD_CMD_RSP_TYPE_NO_RESPONSE;
    221         if (sdcmd(cmd, arg, resp) == -1)
    222                 return(-1);
    223 
    224         /* Wait for the SD card to enter Stand-by State */
    225         do {
    226                 arg = (sdrca << 16) & 0xFFFF0000;
    227                 cmd = SD_CMD_CMD13_SEND_STATUS | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_NO_DATA_PRESENT |
    228                         SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE | SD_CMD_RSP_TYPE_R1;
    229                 if (sdcmd(cmd, arg, resp) == -1)
    230                         return(-1);
    231         } while ((resp[0] & SD_RSP10_R1_CURRENT_STATE) != SD_RSP10_R1_CURRENT_STATE_STANDBY);
    232 
    233         /* This point is reached when SD controller initialization and SD card
    234            communication is successful */
    235         return(0);
     49    uint32_t cmd, arg, resp[4];
     50
     51    /* Reset the MMC/SD controller */
     52    MMCHS0_REG(SD_SYSCONFIG) = SD_SYSCONFIG_SOFTRESET;
     53    while(!(MMCHS0_REG(SD_SYSSTATUS) & SD_SYSSTATUS_RESETDONE));
     54
     55    /* Reset the command and data lines */
     56    MMCHS0_REG(SD_SYSCTL) |= SD_SYSCTL_SRA;
     57    while(MMCHS0_REG(SD_SYSCTL) & SD_SYSCTL_SRA);
     58
     59    /* Configure the MMC/SD controller capabilities to enable 3.0 V operating voltage */
     60    MMCHS0_REG(SD_CAPA) = SD_CAPA_VS30;
     61
     62    /* Configure SD_IE register to update certain status bits in SD_STAT */
     63    MMCHS0_REG(SD_IE) = SD_IE_BADA_ENABLE | SD_IE_CERR_ENABLE | SD_IE_ACE_ENABLE |
     64                        SD_IE_DEB_ENABLE | SD_IE_DCRC_ENABLE | SD_IE_DTO_ENABLE | SD_IE_CIE_ENABLE |
     65                        SD_IE_CEB_ENABLE | SD_IE_CCRC_ENABLE | SD_IE_CIRQ_ENABLE | SD_IE_CREM_ENABLE |
     66                        SD_IE_CINS_ENABLE | SD_IE_BRR_ENABLE | SD_IE_BWR_ENABLE |
     67                        SD_IE_TC_ENABLE | SD_IE_CC_ENABLE;
     68
     69    /* Disable open-drain mode (only used for MMC cards) and 8-bit data width  */
     70    MMCHS0_REG(SD_CON) &= ~(SD_CON_OD | SD_CON_DW8);
     71
     72    /* Configure the operating voltage to 3.0 V */
     73    MMCHS0_REG(SD_HCTL) &= ~(SD_HCTL_SDVS);
     74    MMCHS0_REG(SD_HCTL) |= SD_HCTL_SDVS_VS30;
     75
     76    /* Set the data width to 4-bits */
     77    MMCHS0_REG(SD_HCTL) |= SD_HCTL_DTW;
     78
     79    /* Turn on the bus */
     80    MMCHS0_REG(SD_HCTL) |= SD_HCTL_SDBP;
     81    while(!(MMCHS0_REG(SD_HCTL) & SD_HCTL_SDBP));
     82
     83    /* Enable the internal clock */
     84    MMCHS0_REG(SD_SYSCTL) |= SD_SYSCTL_ICE;
     85
     86    /* Configure Clock Frequency Select to 100 KHz */
     87    MMCHS0_REG(SD_SYSCTL) = (MMCHS0_REG(SD_SYSCTL) & ~(SD_SYSCTL_CLKD)) | (960 << 6);
     88
     89    /* Wait for clock to stabilize */
     90    while(!(MMCHS0_REG(SD_SYSCTL) & SD_SYSCTL_ICS));
     91
     92    /* Configure SD_SYSCONFIG */
     93    MMCHS0_REG(SD_SYSCONFIG) &= ~(SD_SYSCONFIG_CLOCKACTIVITY | SD_SYSCONFIG_SIDLEMODE);
     94    MMCHS0_REG(SD_SYSCONFIG) |= SD_SYSCONFIG_SIDLEMODE_WKUP | SD_SYSCONFIG_ENAWAKEUP_ENABLE |
     95                                SD_SYSCONFIG_AUTOIDLE_AUTOGATE;
     96
     97    /* Enable the clock to the SD card */
     98    MMCHS0_REG(SD_SYSCTL) |= SD_SYSCTL_CEN_ENABLE;
     99
     100    /* Perform the Initialization Stream as specified in the AM335x TRM, Section 18.3.3.2
     101       "Card Detection, Identicication, and Selection" */
     102    MMCHS0_REG(SD_CON) |= SD_CON_INIT;
     103    /* Clear the SD_STAT register */
     104    MMCHS0_REG(SD_STAT) = 0xFFFFFFFF;
     105    MMCHS0_REG(SD_ARG) = 0x00000000;
     106    MMCHS0_REG(SD_CMD) = 0x00000000;
     107    while(!(MMCHS0_REG(SD_STAT) & SD_STAT_CC));
     108    /* Clear CC flag in SD_STAT */
     109    MMCHS0_REG(SD_STAT) |= SD_STAT_CC;
     110    MMCHS0_REG(SD_CON) &= ~SD_CON_INIT;
     111
     112    /* Change the clock frequency to 6 MHz and set the DTO to the maximum value setting */
     113    MMCHS0_REG(SD_SYSCTL) &= ~SD_SYSCTL_DTO;
     114    MMCHS0_REG(SD_SYSCTL) |= SD_SYSCTL_DTO_TCF_2_27;
     115    MMCHS0_REG(SD_SYSCTL) = (MMCHS0_REG(SD_SYSCTL) & ~SD_SYSCTL_CLKD) | (16 << 6);
     116
     117    /* Wait for clock to stabilize */
     118    while((MMCHS0_REG(SD_SYSCTL) & SD_SYSCTL_ICS) != SD_SYSCTL_ICS);
     119
     120    /* Send CMD0/GO_IDLE_STATE to reset the SD card connected to MMC0 interface */
     121    arg = 0x00000000;
     122    cmd = SD_CMD_CMD0_GO_IDLE_STATE | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_NO_DATA_PRESENT |
     123          SD_CMD_CICE_DISABLE | SD_CMD_CCCE_DISABLE | SD_CMD_RSP_TYPE_NO_RESPONSE;
     124    if(sdcmd(cmd, arg, resp) == -1) {
     125        return(-1);
     126    }
     127
     128    /* Send CMD8/SEND_IF_COND to verify that the SD card satisfies MMC/SD controller
     129       requirements */
     130    arg = 0x00000188;
     131    cmd = SD_CMD_CMD8_SEND_IF_COND | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_NO_DATA_PRESENT |
     132          SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE | SD_CMD_RSP_TYPE_R7;
     133    if(sdcmd(cmd, arg, resp) == -1) {
     134        return(-1);
     135    }
     136
     137    /* Determine what type of SD card is connected, i.e. standard capacity, high capacity, etc.
     138     * We perform a CMD55/ACMD41 loop until the "Card power up status bit" is set in the OCR
     139     * register from the SD card to determine when we have a valid response */
     140    do {
     141        arg = 0x00000000;
     142        cmd = SD_CMD_CMD55_APP_CMD | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_NO_DATA_PRESENT |
     143              SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE | SD_CMD_RSP_TYPE_R1;
     144        if(sdcmd(cmd, arg, resp) == -1) {
     145            return(-1);
     146        }
     147
     148        arg = 0x40060000;
     149        cmd = SD_CMD_ACMD41_SD_SEND_OP_COND | SD_CMD_CMD_TYPE_NORMAL |
     150              SD_CMD_DP_NO_DATA_PRESENT | SD_CMD_CICE_DISABLE | SD_CMD_CCCE_DISABLE |
     151              SD_CMD_RSP_TYPE_R3;
     152        if(sdcmd(cmd, arg, resp) == -1) {
     153            return(-1);
     154        }
     155    } while(!(resp[0] & SD_RSP10_R3_CARD_POWER_UP_STATUS));
     156
     157    /* Check SD_RSP10 to determine whether the card connected is high capacity or not */
     158    if(resp[0] & SD_RSP10_R3_CARD_CAPACITY_STATUS) {
     159        sdInfoTbl[interface].highcapacity = 1;
     160    } else {
     161        sdInfoTbl[interface].highcapacity = 0;
     162    }
     163
     164    /* Send CMD2 to get SD's CID and to put the card into Identification State */
     165    arg = 0x00000000;
     166    cmd = SD_CMD_CMD2_ALL_SEND_CID | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_NO_DATA_PRESENT |
     167          SD_CMD_CICE_DISABLE | SD_CMD_CCCE_ENABLE | SD_CMD_RSP_TYPE_R2;
     168    if(sdcmd(cmd, arg, resp) == -1) {
     169        return(-1);
     170    }
     171
     172    /* Send CMD3, i.e. request new relative address (RCA) and to put the card into
     173       Stand-by State */
     174    arg = 0x00000000;
     175    cmd = SD_CMD_CMD3_SEND_RELATIVE_ADDR | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_NO_DATA_PRESENT |
     176          SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE | SD_CMD_RSP_TYPE_R6;
     177    if(sdcmd(cmd, arg, resp) == -1) {
     178        return(-1);
     179    }
     180
     181    /* Save the RCA published from the SD card, this will be used in future CMDx commands */
     182    sdrca = (MMCHS0_REG(SD_RSP10) >> 16) & 0xFFFF;
     183
     184    /* Wait for the SD card to enter Stand-by State */
     185    do {
     186        arg = (sdrca << 16) & 0xFFFF0000;
     187        cmd = SD_CMD_CMD13_SEND_STATUS | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_NO_DATA_PRESENT |
     188              SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE | SD_CMD_RSP_TYPE_R1;
     189        if(sdcmd(cmd, arg, resp) == -1) {
     190            return(-1);
     191        }
     192    } while((resp[0] & SD_RSP10_R1_CURRENT_STATE) != SD_RSP10_R1_CURRENT_STATE_STANDBY);
     193
     194    /* Put the card with the RCA obtained previously into Transfer State via CMD7 */
     195    arg = (sdrca << 16) & 0xFFFF0000;
     196    cmd = SD_CMD_CMD7_SELECT_DESELECT_CARD | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_NO_DATA_PRESENT |
     197          SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE | SD_CMD_RSP_TYPE_R1B;
     198    if(sdcmd(cmd, arg, resp) == -1) {
     199        return(-1);
     200    }
     201
     202    /* Wait for the SD card to enter Transfer State */
     203    do {
     204        arg = (sdrca << 16) & 0xFFFF0000;
     205        cmd = SD_CMD_CMD13_SEND_STATUS | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_NO_DATA_PRESENT |
     206              SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE | SD_CMD_RSP_TYPE_R1;
     207        if(sdcmd(cmd, arg, resp) == -1) {
     208            return(-1);
     209        }
     210    } while((resp[0] & SD_RSP10_R1_CURRENT_STATE) != SD_RSP10_R1_CURRENT_STATE_TRANSFER);
     211
     212    /* Set the bus-width to 4-bits */
     213
     214    /* Send CMD55 to get ready to configure the bus-width via ACMD6 */
     215    arg = (sdrca << 16) & 0xFFFF0000;
     216    cmd = SD_CMD_CMD55_APP_CMD | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_NO_DATA_PRESENT |
     217          SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE | SD_CMD_RSP_TYPE_R1;
     218    if(sdcmd(cmd, arg, resp) == -1) {
     219        return(-1);
     220    }
     221
     222    /* Send ACMD6, SET_BUS_WIDTH to set the bus-width to 4-bits */
     223    arg = 0x00000002;
     224    cmd = SD_CMD_ACMD6_SET_BUS_WIDTH | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_NO_DATA_PRESENT |
     225          SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE | SD_CMD_RSP_TYPE_R1;
     226    if(sdcmd(cmd, arg, resp) == -1) {
     227        return(-1);
     228    }
     229
     230    /* Put the SD card into Stand-by State */
     231    arg = 0x00000000;
     232    cmd = SD_CMD_CMD7_SELECT_DESELECT_CARD | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_NO_DATA_PRESENT |
     233          SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE | SD_CMD_RSP_TYPE_NO_RESPONSE;
     234    if(sdcmd(cmd, arg, resp) == -1) {
     235        return(-1);
     236    }
     237
     238    /* Wait for the SD card to enter Stand-by State */
     239    do {
     240        arg = (sdrca << 16) & 0xFFFF0000;
     241        cmd = SD_CMD_CMD13_SEND_STATUS | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_NO_DATA_PRESENT |
     242              SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE | SD_CMD_RSP_TYPE_R1;
     243        if(sdcmd(cmd, arg, resp) == -1) {
     244            return(-1);
     245        }
     246    } while((resp[0] & SD_RSP10_R1_CURRENT_STATE) != SD_RSP10_R1_CURRENT_STATE_STANDBY);
     247
     248    /* This point is reached when SD controller initialization and SD card
     249       communication is successful */
     250    return(0);
    236251}
    237252
     
    239254sdRead(int interface, char *buf, int blknum, int blkcount)
    240255{
    241         uint32_t cmd, arg, resp[4];
    242         uint32_t *wordptr = (uint32_t *) buf;
    243         int byteindex;
    244 
    245         /* Get the SD card's status via CMD13 */
    246         arg = (sdrca << 16) & 0xFFFF0000;
    247         cmd = SD_CMD_CMD13_SEND_STATUS | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_NO_DATA_PRESENT |
    248                 SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE | SD_CMD_RSP_TYPE_R1;
    249         if (sdcmd(cmd, arg, resp) == -1)
    250                 return(-1);
    251 
    252         /* Ensure that the card is in Transfer State before proceeding */
    253         if ((resp[0] & SD_RSP10_R1_CURRENT_STATE) != SD_RSP10_R1_CURRENT_STATE_TRANSFER) {
    254                 arg = (sdrca << 16) & 0xFFFF0000;
    255                 cmd = SD_CMD_CMD7_SELECT_DESELECT_CARD | SD_CMD_CMD_TYPE_NORMAL |
    256                         SD_CMD_DP_NO_DATA_PRESENT | SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE |
    257                         SD_CMD_RSP_TYPE_R1B;
    258                 if (sdcmd(cmd, arg, resp) == -1)
    259                         return(-1);
    260 
    261                 /* Wait for the SD card to enter Transfer State */
    262                 do {
    263                         arg = (sdrca << 16) & 0xFFFF0000;
    264                         cmd = SD_CMD_CMD13_SEND_STATUS | SD_CMD_CMD_TYPE_NORMAL |
    265                                 SD_CMD_DP_NO_DATA_PRESENT | SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE |
    266                                 SD_CMD_RSP_TYPE_R1;
    267                         if (sdcmd(cmd, arg, resp) == -1)
    268                                 return(-1);
    269                 } while ((resp[0] & SD_RSP10_R1_CURRENT_STATE) != SD_RSP10_R1_CURRENT_STATE_TRANSFER);
    270         }
    271 
    272         /* Set the block length and the number of blocks to read */
    273         MMCHS0_REG(SD_BLK) = SD_BLKSIZE | (blkcount << 16);
    274         /* Send CMD18, i.e. read multiple blocks */
    275         arg = blknum;
    276         cmd = SD_CMD_CMD18_READ_MULTIPLE_BLOCK | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_DATA_PRESENT |
    277                 SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE | SD_CMD_RSP_TYPE_R1 | SD_CMD_MSBS_MULTIPLE |
    278                 SD_CMD_DDIR_READ | SD_CMD_ACEN_CMD12_ENABLE | SD_CMD_BCE_ENABLE;
    279         if (sdcmd(cmd, arg, resp) == -1)
    280                 return(-1);
    281 
    282         /* Check the data buffer to see if there is data to be read */
    283         do {
    284                 while (!(MMCHS0_REG(SD_STAT) & SD_STAT_BRR));
    285 
    286                 /* Clear the BRR status bit in SD_STAT */
    287                 MMCHS0_REG(SD_STAT) |= SD_STAT_BRR;
    288 
    289                 for (byteindex = 0; byteindex < (SD_BLKSIZE / 4); byteindex++) {
    290                         *wordptr = (MMCHS0_REG(SD_DATA));
    291                         wordptr++;
    292                 }
    293         } while (!(MMCHS0_REG(SD_STAT) & SD_STAT_TC));
    294 
    295         /* Put the SD card into Stand-by State */
    296         arg = 0;
    297         cmd = SD_CMD_CMD7_SELECT_DESELECT_CARD | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_NO_DATA_PRESENT |
    298                 SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE | SD_CMD_RSP_TYPE_NO_RESPONSE;
    299         if (sdcmd(cmd, arg, resp) == -1)
    300                 return(-1);
    301 
    302         /* Wait for the SD card to enter Stand-by State */
    303         do {
    304                 arg = (sdrca << 16) & 0xFFFF0000;
    305                 cmd = SD_CMD_CMD13_SEND_STATUS | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_NO_DATA_PRESENT |
    306                         SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE | SD_CMD_RSP_TYPE_R1;
    307                 if (sdcmd(cmd, arg, resp) == -1)
    308                         return(-1);
    309         } while ((resp[0] & SD_RSP10_R1_CURRENT_STATE) != SD_RSP10_R1_CURRENT_STATE_STANDBY);
    310 
    311         return(0);
     256    uint32_t cmd, arg, resp[4];
     257    uint32_t *wordptr = (uint32_t *) buf;
     258    int byteindex;
     259
     260    /* Get the SD card's status via CMD13 */
     261    arg = (sdrca << 16) & 0xFFFF0000;
     262    cmd = SD_CMD_CMD13_SEND_STATUS | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_NO_DATA_PRESENT |
     263          SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE | SD_CMD_RSP_TYPE_R1;
     264    if(sdcmd(cmd, arg, resp) == -1) {
     265        return(-1);
     266    }
     267
     268    /* Ensure that the card is in Transfer State before proceeding */
     269    if((resp[0] & SD_RSP10_R1_CURRENT_STATE) != SD_RSP10_R1_CURRENT_STATE_TRANSFER) {
     270        arg = (sdrca << 16) & 0xFFFF0000;
     271        cmd = SD_CMD_CMD7_SELECT_DESELECT_CARD | SD_CMD_CMD_TYPE_NORMAL |
     272              SD_CMD_DP_NO_DATA_PRESENT | SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE |
     273              SD_CMD_RSP_TYPE_R1B;
     274        if(sdcmd(cmd, arg, resp) == -1) {
     275            return(-1);
     276        }
     277
     278        /* Wait for the SD card to enter Transfer State */
     279        do {
     280            arg = (sdrca << 16) & 0xFFFF0000;
     281            cmd = SD_CMD_CMD13_SEND_STATUS | SD_CMD_CMD_TYPE_NORMAL |
     282                  SD_CMD_DP_NO_DATA_PRESENT | SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE |
     283                  SD_CMD_RSP_TYPE_R1;
     284            if(sdcmd(cmd, arg, resp) == -1) {
     285                return(-1);
     286            }
     287        } while((resp[0] & SD_RSP10_R1_CURRENT_STATE) != SD_RSP10_R1_CURRENT_STATE_TRANSFER);
     288    }
     289
     290    /* Set the block length and the number of blocks to read */
     291    MMCHS0_REG(SD_BLK) = SD_BLKSIZE | (blkcount << 16);
     292    /* Send CMD18, i.e. read multiple blocks */
     293    arg = blknum;
     294    cmd = SD_CMD_CMD18_READ_MULTIPLE_BLOCK | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_DATA_PRESENT |
     295          SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE | SD_CMD_RSP_TYPE_R1 | SD_CMD_MSBS_MULTIPLE |
     296          SD_CMD_DDIR_READ | SD_CMD_ACEN_CMD12_ENABLE | SD_CMD_BCE_ENABLE;
     297    if(sdcmd(cmd, arg, resp) == -1) {
     298        return(-1);
     299    }
     300
     301    /* Check the data buffer to see if there is data to be read */
     302    do {
     303        while(!(MMCHS0_REG(SD_STAT) & SD_STAT_BRR));
     304
     305        /* Clear the BRR status bit in SD_STAT */
     306        MMCHS0_REG(SD_STAT) |= SD_STAT_BRR;
     307
     308        for(byteindex = 0; byteindex < (SD_BLKSIZE / 4); byteindex++) {
     309            *wordptr = (MMCHS0_REG(SD_DATA));
     310            wordptr++;
     311        }
     312    } while(!(MMCHS0_REG(SD_STAT) & SD_STAT_TC));
     313
     314    /* Put the SD card into Stand-by State */
     315    arg = 0;
     316    cmd = SD_CMD_CMD7_SELECT_DESELECT_CARD | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_NO_DATA_PRESENT |
     317          SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE | SD_CMD_RSP_TYPE_NO_RESPONSE;
     318    if(sdcmd(cmd, arg, resp) == -1) {
     319        return(-1);
     320    }
     321
     322    /* Wait for the SD card to enter Stand-by State */
     323    do {
     324        arg = (sdrca << 16) & 0xFFFF0000;
     325        cmd = SD_CMD_CMD13_SEND_STATUS | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_NO_DATA_PRESENT |
     326              SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE | SD_CMD_RSP_TYPE_R1;
     327        if(sdcmd(cmd, arg, resp) == -1) {
     328            return(-1);
     329        }
     330    } while((resp[0] & SD_RSP10_R1_CURRENT_STATE) != SD_RSP10_R1_CURRENT_STATE_STANDBY);
     331
     332    return(0);
    312333}
    313334
     
    315336sdWrite(int interface, char *buf, int blknum, int blkcount)
    316337{
    317         uint32_t cmd, arg, resp[4];
    318         uint32_t *wordptr = (uint32_t *) buf;
    319         int byteindex;
    320 
    321         /* Get the SD card's status by sending CMD13 */
    322         arg = (sdrca << 16) & 0xFFFF0000;
    323         cmd = SD_CMD_CMD13_SEND_STATUS | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_NO_DATA_PRESENT |
    324                 SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE | SD_CMD_RSP_TYPE_R1;
    325         if (sdcmd(cmd, arg, resp) == -1)
    326                 return(-1);
    327 
    328         /* Ensure that the card is in the Transfer State before proceeding */
    329         if ((resp[0] & SD_RSP10_R1_CURRENT_STATE) != SD_RSP10_R1_CURRENT_STATE_TRANSFER) {
    330                 arg = (sdrca << 16) & 0xFFFF0000;
    331                 cmd  = SD_CMD_CMD7_SELECT_DESELECT_CARD | SD_CMD_CMD_TYPE_NORMAL |
    332                         SD_CMD_DP_NO_DATA_PRESENT | SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE |
    333                         SD_CMD_RSP_TYPE_R1B;
    334                 if (sdcmd(cmd, arg, resp) == -1)
    335                         return(-1);
    336 
    337                 /* Wait for SD card to enter Transfer State */
    338                 do {
    339                         arg = (sdrca << 16) & 0xFFFF0000;
    340                         cmd = SD_CMD_CMD13_SEND_STATUS | SD_CMD_CMD_TYPE_NORMAL |
    341                                 SD_CMD_DP_NO_DATA_PRESENT | SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE |
    342                                 SD_CMD_RSP_TYPE_R1;
    343                         if (sdcmd(cmd, arg, resp) == -1)
    344                                 return(-1);
    345                 } while ((resp[0] & SD_RSP10_R1_CURRENT_STATE) != SD_RSP10_R1_CURRENT_STATE_TRANSFER);
    346         }
    347 
    348         /* Set the block length in bytes and the number of blocks to write to the SD card */
    349         MMCHS0_REG(SD_BLK) = SD_BLKSIZE | ( blkcount << 16);
    350         /* Send CMD25, that is write the number of blocks specified in 'blkcount' from 'buf' to the
    351          * location that is 512 byte aligned in the SD card specified by the block number 'blknum'
    352          */
    353         arg = blknum;
    354         cmd = SD_CMD_CMD25_WRITE_MULTIPLE_BLOCK | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_DATA_PRESENT |
    355                 SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE | SD_CMD_RSP_TYPE_R1 | SD_CMD_MSBS_MULTIPLE |
    356                 SD_CMD_DDIR_WRITE | SD_CMD_ACEN_CMD12_ENABLE | SD_CMD_BCE_ENABLE;
    357         if (sdcmd(cmd, arg, resp) == -1)
    358                 return(-1);
    359 
    360         /* Write the data */
    361         do {
    362                 /* Wait until data is ready to be written */
    363                 while (!(MMCHS0_REG(SD_STAT) & (SD_STAT_BWR | SD_STAT_TC)));
    364 
    365                 if (MMCHS0_REG(SD_STAT) & SD_STAT_TC)
    366                         break;
    367 
    368                 /* Clear the BWR status bit in SD_STAT */
    369                 MMCHS0_REG(SD_STAT) |= SD_STAT_BWR;
    370 
    371                 for (byteindex = 0; byteindex < (SD_BLKSIZE / 4); byteindex++)
    372                         MMCHS0_REG(SD_DATA) = *wordptr++;
    373         } while (!(MMCHS0_REG(SD_STAT) & SD_STAT_TC));
    374 
    375         /* Put the SD card into Stand-by State */
    376         arg = 0x00000000;
    377         cmd = SD_CMD_CMD7_SELECT_DESELECT_CARD | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_NO_DATA_PRESENT |
    378                 SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE | SD_CMD_RSP_TYPE_NO_RESPONSE;
    379         if (sdcmd(cmd, arg, resp) == -1)
    380                 return(-1);
    381 
    382         /* Wait for SD card to enter Stand-by State */
    383         do {
    384                 arg= (sdrca << 16) & 0xFFFF0000;
    385                 cmd  = SD_CMD_CMD13_SEND_STATUS | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_NO_DATA_PRESENT |
    386                         SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE | SD_CMD_RSP_TYPE_R1;
    387                 if (sdcmd(cmd, arg, resp) == -1)
    388                         return(-1);
    389         } while ((resp[0] & SD_RSP10_R1_CURRENT_STATE) != SD_RSP10_R1_CURRENT_STATE_STANDBY);
    390 
    391         return(0);
     338    uint32_t cmd, arg, resp[4];
     339    uint32_t *wordptr = (uint32_t *) buf;
     340    int byteindex;
     341
     342    /* Get the SD card's status by sending CMD13 */
     343    arg = (sdrca << 16) & 0xFFFF0000;
     344    cmd = SD_CMD_CMD13_SEND_STATUS | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_NO_DATA_PRESENT |
     345          SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE | SD_CMD_RSP_TYPE_R1;
     346    if(sdcmd(cmd, arg, resp) == -1) {
     347        return(-1);
     348    }
     349
     350    /* Ensure that the card is in the Transfer State before proceeding */
     351    if((resp[0] & SD_RSP10_R1_CURRENT_STATE) != SD_RSP10_R1_CURRENT_STATE_TRANSFER) {
     352        arg = (sdrca << 16) & 0xFFFF0000;
     353        cmd  = SD_CMD_CMD7_SELECT_DESELECT_CARD | SD_CMD_CMD_TYPE_NORMAL |
     354               SD_CMD_DP_NO_DATA_PRESENT | SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE |
     355               SD_CMD_RSP_TYPE_R1B;
     356        if(sdcmd(cmd, arg, resp) == -1) {
     357            return(-1);
     358        }
     359
     360        /* Wait for SD card to enter Transfer State */
     361        do {
     362            arg = (sdrca << 16) & 0xFFFF0000;
     363            cmd = SD_CMD_CMD13_SEND_STATUS | SD_CMD_CMD_TYPE_NORMAL |
     364                  SD_CMD_DP_NO_DATA_PRESENT | SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE |
     365                  SD_CMD_RSP_TYPE_R1;
     366            if(sdcmd(cmd, arg, resp) == -1) {
     367                return(-1);
     368            }
     369        } while((resp[0] & SD_RSP10_R1_CURRENT_STATE) != SD_RSP10_R1_CURRENT_STATE_TRANSFER);
     370    }
     371
     372    /* Set the block length in bytes and the number of blocks to write to the SD card */
     373    MMCHS0_REG(SD_BLK) = SD_BLKSIZE | (blkcount << 16);
     374    /* Send CMD25, that is write the number of blocks specified in 'blkcount' from 'buf' to the
     375     * location that is 512 byte aligned in the SD card specified by the block number 'blknum'
     376     */
     377    arg = blknum;
     378    cmd = SD_CMD_CMD25_WRITE_MULTIPLE_BLOCK | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_DATA_PRESENT |
     379          SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE | SD_CMD_RSP_TYPE_R1 | SD_CMD_MSBS_MULTIPLE |
     380          SD_CMD_DDIR_WRITE | SD_CMD_ACEN_CMD12_ENABLE | SD_CMD_BCE_ENABLE;
     381    if(sdcmd(cmd, arg, resp) == -1) {
     382        return(-1);
     383    }
     384
     385    /* Write the data */
     386    do {
     387        /* Wait until data is ready to be written */
     388        while(!(MMCHS0_REG(SD_STAT) & (SD_STAT_BWR | SD_STAT_TC)));
     389
     390        if(MMCHS0_REG(SD_STAT) & SD_STAT_TC) {
     391            break;
     392        }
     393
     394        /* Clear the BWR status bit in SD_STAT */
     395        MMCHS0_REG(SD_STAT) |= SD_STAT_BWR;
     396
     397        for(byteindex = 0; byteindex < (SD_BLKSIZE / 4); byteindex++) {
     398            MMCHS0_REG(SD_DATA) = *wordptr++;
     399        }
     400    } while(!(MMCHS0_REG(SD_STAT) & SD_STAT_TC));
     401
     402    /* Put the SD card into Stand-by State */
     403    arg = 0x00000000;
     404    cmd = SD_CMD_CMD7_SELECT_DESELECT_CARD | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_NO_DATA_PRESENT |
     405          SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE | SD_CMD_RSP_TYPE_NO_RESPONSE;
     406    if(sdcmd(cmd, arg, resp) == -1) {
     407        return(-1);
     408    }
     409
     410    /* Wait for SD card to enter Stand-by State */
     411    do {
     412        arg= (sdrca << 16) & 0xFFFF0000;
     413        cmd  = SD_CMD_CMD13_SEND_STATUS | SD_CMD_CMD_TYPE_NORMAL | SD_CMD_DP_NO_DATA_PRESENT |
     414               SD_CMD_CICE_ENABLE | SD_CMD_CCCE_ENABLE | SD_CMD_RSP_TYPE_R1;
     415        if(sdcmd(cmd, arg, resp) == -1) {
     416            return(-1);
     417        }
     418    } while((resp[0] & SD_RSP10_R1_CURRENT_STATE) != SD_RSP10_R1_CURRENT_STATE_STANDBY);
     419
     420    return(0);
    392421}
    393422
     
    395424sdInstalled(int interface)
    396425{
    397         if ((MMCHS0_REG(SD_CON) & SD_CON_CDP) == SD_CON_CDP_ACTIVE_HIGH)
    398                 if (MMCHS0_REG(SD_PSTATE) & SD_PSTATE_CINS)
    399                         return(1);
    400                 else
    401                         return(0);
    402         else
    403                 if (MMCHS0_REG(SD_PSTATE) & SD_PSTATE_CINS)
    404                         return(0);
    405                 else
    406                         return(1);
     426    if((MMCHS0_REG(SD_CON) & SD_CON_CDP) == SD_CON_CDP_ACTIVE_HIGH)
     427        if(MMCHS0_REG(SD_PSTATE) & SD_PSTATE_CINS) {
     428            return(1);
     429        } else {
     430            return(0);
     431        }
     432    else if(MMCHS0_REG(SD_PSTATE) & SD_PSTATE_CINS) {
     433        return(0);
     434    } else {
     435        return(1);
     436    }
    407437}
    408438
     
    410440sdPowerup(int tot)
    411441{
    412         return(-1);
     442    return(-1);
    413443}
    414444
     
    416446sdReadCxD(int interface, unsigned char *buf, int cmd)
    417447{
    418         return(-1);
    419 }
     448    return(-1);
     449}
  • ports/beagleboneblack/config.h

    rd355df2 r976c170  
    3030#define CONSOLE_UART_BASE UART0_BASE
    3131
    32 #define SIO_STEP 4
    33 #define IEN_DEFAULT 0x40
    34 #define MCTL_DEFAULT 0x01
     32#define SIO_STEP                4
     33#define IEN_DEFAULT             0x40
     34#define MCTL_DEFAULT            0x01
    3535
    36 #define TIMER_TICKS_PER_MSEC    545000
     36#define TIMER_TICKS_PER_MSEC    545000
    3737
    3838/* DEFAULT_ETHERADD & DEFAULT_IPADD:
     
    4141 * DEFAULT_IPADD could be set to "DHCP" or "BOOTP" as well.
    4242 */
    43 #define DEFAULT_ETHERADD "00:30:23:40:00:"      // Cogent Block
    44 #define DEFAULT_IPADD    "192.168.254.110"             
     43#define DEFAULT_ETHERADD "00:30:23:40:00:"      // Cogent Block
     44#define DEFAULT_IPADD    "192.168.254.110"
    4545
    4646#define CPU_LE
     
    5050// If this is defined, then the output similar to the following will
    5151// be printed just above the uMon header...
    52 //              Silicon ID: 1.0
    53 //              CPU Rev: 2, Variant: 1
    54 //              CM Rev: 1.0, PRM Rev: 1.0
     52//      Silicon ID: 1.0
     53//      CPU Rev: 2, Variant: 1
     54//      CM Rev: 1.0, PRM Rev: 1.0
    5555// #define USR_HEADER_FUNC show_revision
    5656
     
    6464 *  The total of XBUFCNT+RBUFCNT should not exceed MAXEBDS
    6565 */
    66 #define XBUFCNT         8
    67 #define RBUFCNT         8
    68 #define XBUFSIZE        2048
    69 #define RBUFSIZE        2048
     66#define XBUFCNT     8
     67#define RBUFCNT     8
     68#define XBUFSIZE    2048
     69#define RBUFSIZE    2048
    7070
    7171/* LOOPS_PER_SECOND:
     
    7474 * monitor command line.
    7575 */
    76 #define LOOPS_PER_SECOND    15000
     76#define LOOPS_PER_SECOND        15000
    7777
    78 #define INCLUDE_NANDCMD                 0
     78#define INCLUDE_NANDCMD         0
    7979
    8080#if INCLUDE_NANDCMD
    8181/* Needed for NAND to work with TFSRAM:
    8282 */
    83 #define NAND_TFS_BASE                   0x10000         // base of TFS in NAND
     83#define NAND_TFS_BASE           0x10000     // base of TFS in NAND
    8484
    85 #define FLASHRAM_BASE                   0x80300000
    86 #define FLASHRAM_END                    0x8037ffff
    87 #define FLASHRAM_SECTORSIZE             0x00010000
    88 #define FLASHRAM_SPARESIZE              FLASHRAM_SECTORSIZE
    89 #define FLASHRAM_BANKNUM                1
    90 #define FLASHRAM_SECTORCOUNT    8
     85#define FLASHRAM_BASE           0x80300000
     86#define FLASHRAM_END            0x8037ffff
     87#define FLASHRAM_SECTORSIZE     0x00010000
     88#define FLASHRAM_SPARESIZE      FLASHRAM_SECTORSIZE
     89#define FLASHRAM_BANKNUM        1
     90#define FLASHRAM_SECTORCOUNT    8
    9191#endif
    9292
     
    9494 */
    9595#ifdef FLASHRAM_BASE
    96 #define FLASHBANKS                              2
     96#define FLASHBANKS              2
    9797#else
    98 #define FLASHBANKS                              1
     98#define FLASHBANKS              1
    9999#endif
    100 #define SINGLE_FLASH_DEVICE     1
    101 #define FLASH_COPY_TO_RAM               1
    102 #define FLASH_BANK0_BASE_ADDR   0x08000000
    103 #define FLASH_PROTECT_RANGE     "0-2"
     100#define SINGLE_FLASH_DEVICE     1
     101#define FLASH_COPY_TO_RAM       1
     102#define FLASH_BANK0_BASE_ADDR   0x08000000
     103#define FLASH_PROTECT_RANGE     "0-2"
    104104#define FLASH_BANK0_WIDTH       2
    105105#define FLASH_LARGEST_SECTOR    0x20000
    106 #define FLASH_LOOP_TIMEOUT              10000000
     106#define FLASH_LOOP_TIMEOUT      10000000
    107107#define BUFFERED_WRITE
    108108
     
    116116 *                  the TFSSPARE sector.
    117117 */
    118 #define TFSSPARESIZE                    FLASH_LARGEST_SECTOR
    119 #define TFS_DEVTOT                      1
    120 #define TFSSTART                        (FLASH_BANK0_BASE_ADDR+0x060000)
    121 //#define TFSEND                        (FLASH_BANK0_BASE_ADDR+0x007dffff)      // 8MB Flash
    122 #define TFSEND                          (FLASH_BANK0_BASE_ADDR+0x00edffff)      // 16MB Flash
    123 //#define TFSEND                        (FLASH_BANK0_BASE_ADDR+0x03dfffff)      // 64MB Flash
    124 #define TFSSPARE                        (TFSEND+1)
    125 #define TFSSECTORCOUNT                  ((TFSSPARE-TFSSTART)/0x20000)
    126 #define TFS_EBIN_ELFMSBIN               1
    127 #define TFS_VERBOSE_STARTUP             1
    128 #define TFS_ALTDEVTBL_BASE              &alt_tfsdevtbl_base
     118#define TFSSPARESIZE            FLASH_LARGEST_SECTOR
     119#define TFS_DEVTOT              1
     120#define TFSSTART                (FLASH_BANK0_BASE_ADDR+0x060000)
     121//#define TFSEND                (FLASH_BANK0_BASE_ADDR+0x007dffff)  // 8MB Flash
     122#define TFSEND                  (FLASH_BANK0_BASE_ADDR+0x00edffff)  // 16MB Flash
     123//#define TFSEND                (FLASH_BANK0_BASE_ADDR+0x03dfffff)  // 64MB Flash
     124#define TFSSPARE                (TFSEND+1)
     125#define TFSSECTORCOUNT          ((TFSSPARE-TFSSTART)/0x20000)
     126#define TFS_EBIN_ELFMSBIN       1
     127#define TFS_VERBOSE_STARTUP     1
     128#define TFS_ALTDEVTBL_BASE      &alt_tfsdevtbl_base
    129129
    130130/* Specify CPU/PLATFORM type and name so that common code can be used
     
    142142 * increased using the heap extension option in the heap command.
    143143 */
    144 #define ALLOCSIZE       1024    // (64*1024)
    145 #define MONSTACKSIZE    (16*1024)
     144#define ALLOCSIZE           1024    // (64*1024)
     145#define MONSTACKSIZE        (16*1024)
    146146
    147147
     
    150150 * each of these macros.
    151151 */
    152                                                
    153 #define INCLUDE_MEMTRACE        0
     152
     153#define INCLUDE_MEMTRACE        0
    154154#define INCLUDE_MEMCMDS         1
    155155#define INCLUDE_EDIT            0
     
    157157#define INCLUDE_UNZIP           0
    158158#define INCLUDE_ETHERNET        0
    159 #define INCLUDE_ICMP            0
     159#define INCLUDE_ICMP            0
    160160#define INCLUDE_TFTP            0
    161161#define INCLUDE_DHCPBOOT        0
     
    177177#define INCLUDE_BBC             0
    178178#define INCLUDE_STOREMAC        0
    179 #define INCLUDE_SHELLVARS       0
    180 #define INCLUDE_MALLOC          0
    181 #define INCLUDE_PORTCMD         0
    182 #define INCLUDE_SYSLOG          0
    183 #define INCLUDE_HWTMR           0
     179#define INCLUDE_SHELLVARS       0
     180#define INCLUDE_MALLOC          0
     181#define INCLUDE_PORTCMD         0
     182#define INCLUDE_SYSLOG          0
     183#define INCLUDE_HWTMR           0
    184184#define INCLUDE_VERBOSEHELP     0
    185 #define INCLUDE_GDB             0
    186 #define INCLUDE_USRLVL          0
    187 #define INCLUDE_JFFS2           0
    188 #define INCLUDE_JFFS2ZLIB       0
    189 #define INCLUDE_FBI             0
    190 #define INCLUDE_TSI             0
    191 #define INCLUDE_SD              1
    192 #define INCLUDE_DNS             0
    193 #define INCLUDE_BLINKLED        1
    194 #define TARGET_BLINKLED target_blinkled
     185#define INCLUDE_GDB             0
     186#define INCLUDE_USRLVL          0
     187#define INCLUDE_JFFS2           0
     188#define INCLUDE_JFFS2ZLIB       0
     189#define INCLUDE_FBI             0
     190#define INCLUDE_TSI             0
     191#define INCLUDE_SD              1
     192#define INCLUDE_DNS             0
     193#define INCLUDE_BLINKLED        1
     194#define TARGET_BLINKLED         target_blinkled
    195195
    196196/* Inclusion of this next file will make sure that all of the above
  • ports/beagleboneblack/cpuio.c

    rd355df2 r976c170  
    1313getUartDivisor(int baud, unsigned char *hi, unsigned char *lo)
    1414{
    15         *lo = ((48000000/16)/baud) & 0x00ff;
    16         *hi = (((48000000/16)/baud) & 0xff00) >> 8;
    17         return(0);
     15    *lo = ((48000000/16)/baud) & 0x00ff;
     16    *hi = (((48000000/16)/baud) & 0xff00) >> 8;
     17    return(0);
    1818}
    1919
     
    2525devInit(int baud)
    2626{
    27         return(0);
     27    return(0);
    2828}
    2929
     
    3838ConsoleBaudSet(int baud)
    3939{
    40         // ADD_CODE_HERE
    41         return(0);
     40    // ADD_CODE_HERE
     41    return(0);
    4242}*/
    4343
     
    5252target_console_empty(void)
    5353{
    54         // if (UART_OUTPUT_BUFFER_IS_EMPTY())  <- FIX CODE HERE
    55                 return(0);
    56         return(1);
     54    // if (UART_OUTPUT_BUFFER_IS_EMPTY())  <- FIX CODE HERE
     55        return(0);
     56    return(1);
    5757}*/
    5858
     
    6464intsoff(void)
    6565{
    66         ulong status = 0;
    67 
    68         /* ADD_CODE_HERE */
    69         return(status);
     66    ulong status = 0;
     67
     68    /* ADD_CODE_HERE */
     69    return(status);
    7070}
    7171
     
    7777intsrestore(ulong status)
    7878{
    79         /* ADD_CODE_HERE */
     79    /* ADD_CODE_HERE */
    8080}
    8181
     
    9494cacheInitForTarget(void)
    9595{
    96         /* ADD_CODE_HERE */
     96    /* ADD_CODE_HERE */
    9797}
    9898
     
    106106target_reset(void)
    107107{
    108 //      flushDcache(0,0);
    109 //      disableDcache();
    110 //      invalidateIcache(0,0);
    111 //      disableIcache();
    112         monrestart(INITIALIZE);
     108//  flushDcache(0,0);
     109//  disableDcache();
     110//  invalidateIcache(0,0);
     111//  disableIcache();
     112    monrestart(INITIALIZE);
    113113}
    114114
     
    119119ram_vector_install(void)
    120120{
    121         extern unsigned long abort_data;
    122         extern unsigned long abort_prefetch;
    123         extern unsigned long undefined_instruction;
    124         extern unsigned long software_interrupt;
    125         extern unsigned long interrupt_request;
    126         extern unsigned long fast_interrupt_request;
    127         extern unsigned long not_assigned;
    128 
    129         *(ulong **)0x4030ce24 = &undefined_instruction;
    130         *(ulong **)0x4030ce28 = &software_interrupt;
    131         *(ulong **)0x4030ce2c = &abort_prefetch;
    132         *(ulong **)0x4030ce30 = &abort_data;
    133         *(ulong **)0x4030ce34 = &not_assigned;
    134         *(ulong **)0x4030ce38 = &interrupt_request;
    135         *(ulong **)0x4030ce3c = &fast_interrupt_request;
     121    extern unsigned long abort_data;
     122    extern unsigned long abort_prefetch;
     123    extern unsigned long undefined_instruction;
     124    extern unsigned long software_interrupt;
     125    extern unsigned long interrupt_request;
     126    extern unsigned long fast_interrupt_request;
     127    extern unsigned long not_assigned;
     128
     129    *(ulong **)0x4030ce24 = &undefined_instruction;
     130    *(ulong **)0x4030ce28 = &software_interrupt;
     131    *(ulong **)0x4030ce2c = &abort_prefetch;
     132    *(ulong **)0x4030ce30 = &abort_data;
     133    *(ulong **)0x4030ce34 = &not_assigned;
     134    *(ulong **)0x4030ce38 = &interrupt_request;
     135    *(ulong **)0x4030ce3c = &fast_interrupt_request;
    136136}
    137137
     
    139139pinMuxInit(void)
    140140{
    141         // Set pin mux configuration for UART0 RX/TX pins
    142         CNTL_MODULE_REG(CONF_UART0_RXD) = SLEWSLOW | RX_ON |
    143                 PULL_OFF | MUXMODE_0;
    144         CNTL_MODULE_REG(CONF_UART0_TXD) = SLEWSLOW | RX_OFF |
    145                 PULL_OFF | MUXMODE_0;
    146 
    147         // Configure GPIO pins tied to four USR LEDS...
    148         // GPIO1_21: USER0 LED (D2)
    149         CNTL_MODULE_REG(CONF_GPMC_A5) = SLEWSLOW | RX_ON |
    150                 PULL_OFF | MUXMODE_7;
    151         // GPIO1_22: USER1 LED (D3)
    152         CNTL_MODULE_REG(CONF_GPMC_A6) = SLEWSLOW | RX_ON |
    153                 PULL_OFF | MUXMODE_7;
    154         // GPIO1_23: USER2 LED (D4)
    155         CNTL_MODULE_REG(CONF_GPMC_A7) = SLEWSLOW | RX_ON |
    156                 PULL_OFF | MUXMODE_7;
    157         // GPIO1_24: USER3 LED (D5)
    158         CNTL_MODULE_REG(CONF_GPMC_A8) = SLEWSLOW | RX_ON |
    159                 PULL_OFF | MUXMODE_7;
    160 
    161         // Configure the pins for the MMC0 interface
    162         CNTL_MODULE_REG(CONF_MMC0_DAT0) = RX_ON | PULL_ON |
    163                 PULLUP | MUXMODE_0;
    164         CNTL_MODULE_REG(CONF_MMC0_DAT1) = RX_ON | PULL_ON |
    165                 PULLUP | MUXMODE_0;
    166         CNTL_MODULE_REG(CONF_MMC0_DAT2) = RX_ON | PULL_ON |
    167                 PULLUP | MUXMODE_0;
    168         CNTL_MODULE_REG(CONF_MMC0_DAT3) = RX_ON | PULL_ON |
    169                 PULLUP | MUXMODE_0;
    170         CNTL_MODULE_REG(CONF_MMC0_CLK) = RX_ON | PULL_OFF |
    171                 MUXMODE_0;
    172         CNTL_MODULE_REG(CONF_MMC0_CMD) = RX_ON | PULL_ON |
    173                 PULLUP | MUXMODE_0;
    174         CNTL_MODULE_REG(CONF_SPI0_CS1) = RX_ON | PULL_ON |
    175                 PULLUP | MUXMODE_5;
    176 
    177         // Configure the pins for the MMC1 interface
    178         /* MMC1_DAT0 */
    179         CNTL_MODULE_REG(CONF_GPMC_AD0) = RX_ON | PULL_ON |
    180                 PULLUP | MUXMODE_1;
    181         /* MMC1_DAT1 */
    182         CNTL_MODULE_REG(CONF_GPMC_AD1) = RX_ON | PULL_ON |
    183                 PULLUP | MUXMODE_1;
    184         /* MMC1_DAT2 */
    185         CNTL_MODULE_REG(CONF_GPMC_AD2) = RX_ON | PULL_ON |
    186                 PULLUP | MUXMODE_1;
    187         /* MMC1_DAT3 */
    188         CNTL_MODULE_REG(CONF_GPMC_AD3) = RX_ON | PULL_ON |
    189                 PULLUP | MUXMODE_1;
    190         /* MMC1_DAT4 */
    191         CNTL_MODULE_REG(CONF_GPMC_AD4) = RX_ON | PULL_ON |
    192                 PULLUP | MUXMODE_1;
    193         /* MMC1_DAT5 */
    194         CNTL_MODULE_REG(CONF_GPMC_AD5) = RX_ON | PULL_ON |
    195                 PULLUP | MUXMODE_1;
    196         /* MMC1_DAT6 */
    197         CNTL_MODULE_REG(CONF_GPMC_AD6) = RX_ON | PULL_ON |
    198                 PULLUP | MUXMODE_1;
    199         /* MMC1_DAT7 */
    200         CNTL_MODULE_REG(CONF_GPMC_AD7) = RX_ON | PULL_ON |
    201                 PULLUP | MUXMODE_1;
    202         /* MMC1_CLK */
    203         CNTL_MODULE_REG(CONF_GPMC_CSN1) = RX_ON | PULL_OFF |
    204                 MUXMODE_2;
    205         /* MMC1_CMD */
    206         CNTL_MODULE_REG(CONF_GPMC_CSN2) = RX_ON | PULL_ON |
    207                 PULLUP | MUXMODE_2;
     141    // Set pin mux configuration for UART0 RX/TX pins
     142    CNTL_MODULE_REG(CONF_UART0_RXD) = SLEWSLOW | RX_ON |
     143                                      PULL_OFF | MUXMODE_0;
     144    CNTL_MODULE_REG(CONF_UART0_TXD) = SLEWSLOW | RX_OFF |
     145                                      PULL_OFF | MUXMODE_0;
     146
     147    // Configure GPIO pins tied to four USR LEDS...
     148    // GPIO1_21: USER0 LED (D2)
     149    CNTL_MODULE_REG(CONF_GPMC_A5) = SLEWSLOW | RX_ON |
     150                                    PULL_OFF | MUXMODE_7;
     151    // GPIO1_22: USER1 LED (D3)
     152    CNTL_MODULE_REG(CONF_GPMC_A6) = SLEWSLOW | RX_ON |
     153                                    PULL_OFF | MUXMODE_7;
     154    // GPIO1_23: USER2 LED (D4)
     155    CNTL_MODULE_REG(CONF_GPMC_A7) = SLEWSLOW | RX_ON |
     156                                    PULL_OFF | MUXMODE_7;
     157    // GPIO1_24: USER3 LED (D5)
     158    CNTL_MODULE_REG(CONF_GPMC_A8) = SLEWSLOW | RX_ON |
     159                                    PULL_OFF | MUXMODE_7;
     160
     161    // Configure the pins for the MMC0 interface
     162    CNTL_MODULE_REG(CONF_MMC0_DAT0) = RX_ON | PULL_ON |
     163                                      PULLUP | MUXMODE_0;
     164    CNTL_MODULE_REG(CONF_MMC0_DAT1) = RX_ON | PULL_ON |
     165                                      PULLUP | MUXMODE_0;
     166    CNTL_MODULE_REG(CONF_MMC0_DAT2) = RX_ON | PULL_ON |
     167                                      PULLUP | MUXMODE_0;
     168    CNTL_MODULE_REG(CONF_MMC0_DAT3) = RX_ON | PULL_ON |
     169                                      PULLUP | MUXMODE_0;
     170    CNTL_MODULE_REG(CONF_MMC0_CLK) = RX_ON | PULL_OFF |
     171                                     MUXMODE_0;
     172    CNTL_MODULE_REG(CONF_MMC0_CMD) = RX_ON | PULL_ON |
     173                                     PULLUP | MUXMODE_0;
     174    CNTL_MODULE_REG(CONF_SPI0_CS1) = RX_ON | PULL_ON |
     175                                     PULLUP | MUXMODE_5;
     176
     177    // Configure the pins for the MMC1 interface
     178    /* MMC1_DAT0 */
     179    CNTL_MODULE_REG(CONF_GPMC_AD0) = RX_ON | PULL_ON |
     180                                     PULLUP | MUXMODE_1;
     181    /* MMC1_DAT1 */
     182    CNTL_MODULE_REG(CONF_GPMC_AD1) = RX_ON | PULL_ON |
     183                                     PULLUP | MUXMODE_1;
     184    /* MMC1_DAT2 */
     185    CNTL_MODULE_REG(CONF_GPMC_AD2) = RX_ON | PULL_ON |
     186                                     PULLUP | MUXMODE_1;
     187    /* MMC1_DAT3 */
     188    CNTL_MODULE_REG(CONF_GPMC_AD3) = RX_ON | PULL_ON |
     189                                     PULLUP | MUXMODE_1;
     190    /* MMC1_DAT4 */
     191    CNTL_MODULE_REG(CONF_GPMC_AD4) = RX_ON | PULL_ON |
     192                                     PULLUP | MUXMODE_1;
     193    /* MMC1_DAT5 */
     194    CNTL_MODULE_REG(CONF_GPMC_AD5) = RX_ON | PULL_ON |
     195                                     PULLUP | MUXMODE_1;
     196    /* MMC1_DAT6 */
     197    CNTL_MODULE_REG(CONF_GPMC_AD6) = RX_ON | PULL_ON |
     198                                     PULLUP | MUXMODE_1;
     199    /* MMC1_DAT7 */
     200    CNTL_MODULE_REG(CONF_GPMC_AD7) = RX_ON | PULL_ON |
     201                                     PULLUP | MUXMODE_1;
     202    /* MMC1_CLK */
     203    CNTL_MODULE_REG(CONF_GPMC_CSN1) = RX_ON | PULL_OFF |
     204                                      MUXMODE_2;
     205    /* MMC1_CMD */
     206    CNTL_MODULE_REG(CONF_GPMC_CSN2) = RX_ON | PULL_ON |
     207                                      PULLUP | MUXMODE_2;
    208208}
    209209
     
    211211InitGPIO1(void)
    212212{
    213         // GPIO_CTRL: Enable GPIO1 module
    214         GPIO1_REG(0x130) = 0;
    215 
    216         // GPIO_OE: 25-24 are outputs...
    217         GPIO1_REG(0x134) &= ~(USR0_LED | USR1_LED | USR2_LED | USR3_LED);
    218 
    219         // All LEDs off...
    220         GPIO1_REG(0x13c) &= ~(USR0_LED | USR1_LED | USR2_LED | USR3_LED);
     213    // GPIO_CTRL: Enable GPIO1 module
     214    GPIO1_REG(0x130) = 0;
     215
     216    // GPIO_OE: 25-24 are outputs...
     217    GPIO1_REG(0x134) &= ~(USR0_LED | USR1_LED | USR2_LED | USR3_LED);
     218
     219    // All LEDs off...
     220    GPIO1_REG(0x13c) &= ~(USR0_LED | USR1_LED | USR2_LED | USR3_LED);
    221221}
    222222
    223223/* If any CPU IO wasn't initialized in reset.S, do it here...
    224  * This just provides a "C-level" IO init opportunity. 
     224 * This just provides a "C-level" IO init opportunity.
    225225 */
    226226void
    227227initCPUio(void)
    228228{
    229         ram_vector_install();
    230 
    231         // Enable the control module:
    232         CM_WKUP_REG(CM_WKUP_CONTROL_CLKCTRL) |= 2;
    233 
    234         // Enable clock for UART0:
    235         CM_WKUP_REG(CM_WKUP_UART0_CLKCTRL) |= 2;
    236 
    237         // Enable clock for GPIO1:
    238         CM_PER_REG(CM_PER_GPIO1_CLKCTRL) |= 2;
    239 
    240         /* Enable MMC0 clocks */
    241         CM_PER_REG(CM_PER_MMC0_CLKCTRL) |= CM_PER_MMC0_CLKCTRL_MODULEMODE_ENABLE;
    242         while (CM_PER_REG(CM_PER_MMC0_CLKCTRL) & CM_PER_MMC0_CLKCTRL_IDLEST);
    243 
    244         /* Enable MMC1 clocks */
    245         CM_PER_REG(CM_PER_MMC1_CLKCTRL) |= CM_PER_MMC1_CLKCTRL_MODULEMODE_ENABLE;
    246         while (CM_PER_REG(CM_PER_MMC1_CLKCTRL) & CM_PER_MMC0_CLKCTRL_IDLEST);
    247 
    248         pinMuxInit();
    249 
    250         InitUART(DEFAULT_BAUD_RATE);
    251         InitGPIO1();
    252 
    253         // Set UART0 mode to 16x
    254         UART0_REG(UART_MDR1) &= ~7;
     229    ram_vector_install();
     230
     231    // Enable the control module:
     232    CM_WKUP_REG(CM_WKUP_CONTROL_CLKCTRL) |= 2;
     233
     234    // Enable clock for UART0:
     235    CM_WKUP_REG(CM_WKUP_UART0_CLKCTRL) |= 2;
     236
     237    // Enable clock for GPIO1:
     238    CM_PER_REG(CM_PER_GPIO1_CLKCTRL) |= 2;
     239
     240    /* Enable MMC0 clocks */
     241    CM_PER_REG(CM_PER_MMC0_CLKCTRL) |= CM_PER_MMC0_CLKCTRL_MODULEMODE_ENABLE;
     242    while(CM_PER_REG(CM_PER_MMC0_CLKCTRL) & CM_PER_MMC0_CLKCTRL_IDLEST);
     243
     244    /* Enable MMC1 clocks */
     245    CM_PER_REG(CM_PER_MMC1_CLKCTRL) |= CM_PER_MMC1_CLKCTRL_MODULEMODE_ENABLE;
     246    while(CM_PER_REG(CM_PER_MMC1_CLKCTRL) & CM_PER_MMC0_CLKCTRL_IDLEST);
     247
     248    pinMuxInit();
     249
     250    InitUART(DEFAULT_BAUD_RATE);
     251    InitGPIO1();
     252
     253    // Set UART0 mode to 16x
     254    UART0_REG(UART_MDR1) &= ~7;
    255255}
    256256
     
    258258led(int num, int on)
    259259{
    260         unsigned long bit;
    261 
    262         switch(num) {
    263                 case 0: // D0
    264                         bit = USR0_LED;
    265                         break;
    266                 case 1: // D1
    267                         bit = USR1_LED;
    268                         break;
    269                 case 2: // D2
    270                         bit = USR2_LED;
    271                         break;
    272                 case 3: // D3
    273                         bit = USR3_LED;
    274                         break;
    275                 default:
    276                         return(-1);
    277         }
    278 
    279         // GPIO21-24:
    280         if (on)
    281             GPIO1_REG(0x13c) |= bit;
    282         else
    283             GPIO1_REG(0x13c) &= ~bit;
    284         return(0);
     260    unsigned long bit;
     261
     262    switch(num) {
     263    case 0: // D0
     264        bit = USR0_LED;
     265        break;
     266    case 1: // D1
     267        bit = USR1_LED;
     268        break;
     269    case 2: // D2
     270        bit = USR2_LED;
     271        break;
     272    case 3: // D3
     273        bit = USR3_LED;
     274        break;
     275    default:
     276        return(-1);
     277    }
     278
     279    // GPIO21-24:
     280    if(on) {
     281        GPIO1_REG(0x13c) |= bit;
     282    } else {
     283        GPIO1_REG(0x13c) &= ~bit;
     284    }
     285    return(0);
    285286}
    286287
     
    289290{
    290291#if INCLUDE_BLINKLED
    291         static uint8_t ledstate;
    292         static struct elapsed_tmr tmr;
    293 
    294 #define STATLED_ON()    led(0,1)
    295 #define STATLED_OFF()   led(0,0)
     292    static uint8_t ledstate;
     293    static struct elapsed_tmr tmr;
     294
     295#define STATLED_ON()    led(0,1)
     296#define STATLED_OFF()   led(0,0)
    296297#ifndef BLINKON_MSEC
    297298#define BLINKON_MSEC 10000
     
    299300#endif
    300301
    301         switch(ledstate) {
    302                 case 0:
    303                         startElapsedTimer(&tmr,BLINKON_MSEC);
    304                         STATLED_ON();
    305                         ledstate = 1;
    306                         break;
    307                 case 1:
    308                         if(msecElapsed(&tmr)) {
    309                                 STATLED_OFF();
    310                                 ledstate = 2;
    311                                 startElapsedTimer(&tmr,BLINKOFF_MSEC);
    312                         }
    313                         break;
    314                 case 2:
    315                         if(msecElapsed(&tmr)) {
    316                                 STATLED_ON();
    317                                 ledstate = 1;
    318                                 startElapsedTimer(&tmr,BLINKON_MSEC);
    319                         }
    320                         break;
    321         }
     302    switch(ledstate) {
     303    case 0:
     304        startElapsedTimer(&tmr,BLINKON_MSEC);
     305        STATLED_ON();
     306        ledstate = 1;
     307        break;
     308    case 1:
     309        if(msecElapsed(&tmr)) {
     310            STATLED_OFF();
     311            ledstate = 2;
     312            startElapsedTimer(&tmr,BLINKOFF_MSEC);
     313        }
     314        break;
     315    case 2:
     316        if(msecElapsed(&tmr)) {
     317            STATLED_ON();
     318            ledstate = 1;
     319            startElapsedTimer(&tmr,BLINKON_MSEC);
     320        }
     321        break;
     322    }
    322323#endif
    323324}
     
    326327mpu_pll_init(void)
    327328{
    328         uint32_t cm_clkmode_dpll_mpu;
    329         uint32_t cm_clksel_dpll_mpu;
    330         uint32_t cm_div_m2_dpll_mpu;
    331 
    332         // Put MPU PLL in MN Bypass mode
    333         cm_clkmode_dpll_mpu = CM_WKUP_REG(CM_CLKMODE_DPLL_MPU);
    334         cm_clkmode_dpll_mpu &= ~0x00000007;
    335         cm_clkmode_dpll_mpu |= 0x00000004;
    336         CM_WKUP_REG(CM_CLKMODE_DPLL_MPU) = cm_clkmode_dpll_mpu;
    337         // Wait for MPU PLL to enter MN Bypass mode
    338         while ((CM_WKUP_REG(CM_IDLEST_DPLL_MPU) & 0x00000101) != 0x00000100);
    339 
    340         // Set the ARM core frequency to 1 GHz
    341         cm_clksel_dpll_mpu = CM_WKUP_REG(CM_CLKSEL_DPLL_MPU);
    342         cm_clksel_dpll_mpu &= ~0x0007FF7F;
    343         cm_clksel_dpll_mpu |= 1000 << 8;
    344         cm_clksel_dpll_mpu |= 23;
    345         CM_WKUP_REG(CM_CLKSEL_DPLL_MPU) = cm_clksel_dpll_mpu;
    346         cm_div_m2_dpll_mpu = CM_WKUP_REG(CM_DIV_M2_DPLL_MPU);
    347         cm_div_m2_dpll_mpu &= ~0x0000001F;
    348         cm_div_m2_dpll_mpu |= 0x00000001;
    349         CM_WKUP_REG(CM_DIV_M2_DPLL_MPU) = cm_div_m2_dpll_mpu;
    350 
    351         // Lock MPU PLL
    352         cm_clkmode_dpll_mpu = CM_WKUP_REG(CM_CLKMODE_DPLL_MPU);
    353         cm_clkmode_dpll_mpu &= ~0x00000007;
    354         cm_clkmode_dpll_mpu |= 0x00000007;
    355         CM_WKUP_REG(CM_CLKMODE_DPLL_MPU) = cm_clkmode_dpll_mpu;
    356         // Wait for MPU PLL to lock
    357         while ((CM_WKUP_REG(CM_IDLEST_DPLL_MPU) & 0x00000001) != 0x00000001);
     329    uint32_t cm_clkmode_dpll_mpu;
     330    uint32_t cm_clksel_dpll_mpu;
     331    uint32_t cm_div_m2_dpll_mpu;
     332
     333    // Put MPU PLL in MN Bypass mode
     334    cm_clkmode_dpll_mpu = CM_WKUP_REG(CM_CLKMODE_DPLL_MPU);
     335    cm_clkmode_dpll_mpu &= ~0x00000007;
     336    cm_clkmode_dpll_mpu |= 0x00000004;
     337    CM_WKUP_REG(CM_CLKMODE_DPLL_MPU) = cm_clkmode_dpll_mpu;
     338    // Wait for MPU PLL to enter MN Bypass mode
     339    while((CM_WKUP_REG(CM_IDLEST_DPLL_MPU) & 0x00000101) != 0x00000100);
     340
     341    // Set the ARM core frequency to 1 GHz
     342    cm_clksel_dpll_mpu = CM_WKUP_REG(CM_CLKSEL_DPLL_MPU);
     343    cm_clksel_dpll_mpu &= ~0x0007FF7F;
     344    cm_clksel_dpll_mpu |= 1000 << 8;
     345    cm_clksel_dpll_mpu |= 23;
     346    CM_WKUP_REG(CM_CLKSEL_DPLL_MPU) = cm_clksel_dpll_mpu;
     347    cm_div_m2_dpll_mpu = CM_WKUP_REG(CM_DIV_M2_DPLL_MPU);
     348    cm_div_m2_dpll_mpu &= ~0x0000001F;
     349    cm_div_m2_dpll_mpu |= 0x00000001;
     350    CM_WKUP_REG(CM_DIV_M2_DPLL_MPU) = cm_div_m2_dpll_mpu;
     351
     352    // Lock MPU PLL
     353    cm_clkmode_dpll_mpu = CM_WKUP_REG(CM_CLKMODE_DPLL_MPU);
     354    cm_clkmode_dpll_mpu &= ~0x00000007;
     355    cm_clkmode_dpll_mpu |= 0x00000007;
     356    CM_WKUP_REG(CM_CLKMODE_DPLL_MPU) = cm_clkmode_dpll_mpu;
     357    // Wait for MPU PLL to lock
     358    while((CM_WKUP_REG(CM_IDLEST_DPLL_MPU) & 0x00000001) != 0x00000001);
    358359}
    359360
     
    361362core_pll_init(void)
    362363{
    363         uint32_t cm_clkmode_dpll_core;
    364         uint32_t cm_clksel_dpll_core;
    365         uint32_t cm_div_m4_dpll_core;
    366         uint32_t cm_div_m5_dpll_core;
    367         uint32_t cm_div_m6_dpll_core;
    368 
    369         // Put Core PLL in MN Bypass mode
    370         cm_clkmode_dpll_core = CM_WKUP_REG(CM_CLKMODE_DPLL_CORE);
    371         cm_clkmode_dpll_core &= ~0x00000007;
    372         cm_clkmode_dpll_core |= 0x00000004;
    373         CM_WKUP_REG(CM_CLKMODE_DPLL_CORE) = cm_clkmode_dpll_core;
    374         // Wait for Core PLL to enter MN Bypass mode
    375         while ((CM_WKUP_REG(CM_IDLEST_DPLL_CORE) & 0x00000101) != 0x00000100);
    376 
    377         // Configure the multiplier and divider
    378         cm_clksel_dpll_core = CM_WKUP_REG(CM_CLKSEL_DPLL_CORE);
    379         cm_clksel_dpll_core &= ~0x0007FF7F;
    380         cm_clksel_dpll_core |= 1000 << 8;
    381         cm_clksel_dpll_core |= 23;
    382         CM_WKUP_REG(CM_CLKSEL_DPLL_CORE) = cm_clksel_dpll_core;
    383         // Configure the M4, M5, and M6 dividers
    384         cm_div_m4_dpll_core = CM_WKUP_REG(CM_DIV_M4_DPLL_CORE);
    385         cm_div_m4_dpll_core &= ~0x0000001F;
    386         cm_div_m4_dpll_core |= 10;
    387         CM_WKUP_REG(CM_DIV_M4_DPLL_CORE) = cm_div_m4_dpll_core;
    388         cm_div_m5_dpll_core = CM_WKUP_REG(CM_DIV_M5_DPLL_CORE);
    389         cm_div_m5_dpll_core &= ~0x0000001F;
    390         cm_div_m5_dpll_core |= 8;
    391         CM_WKUP_REG(CM_DIV_M5_DPLL_CORE) = cm_div_m5_dpll_core;
    392         cm_div_m6_dpll_core = CM_WKUP_REG(CM_DIV_M6_DPLL_CORE);
    393         cm_div_m6_dpll_core &= ~0x0000001F;
    394         cm_div_m6_dpll_core |= 4;
    395         CM_WKUP_REG(CM_DIV_M6_DPLL_CORE) = cm_div_m6_dpll_core;
    396 
    397         // Lock Core PLL
    398         cm_clkmode_dpll_core = CM_WKUP_REG(CM_CLKMODE_DPLL_CORE);
    399         cm_clkmode_dpll_core &= ~0x00000007;
    400         cm_clkmode_dpll_core |= 0x00000007;
    401         CM_WKUP_REG(CM_CLKMODE_DPLL_CORE) = cm_clkmode_dpll_core;
    402         // Wait for Core PLL to lock
    403         while ((CM_WKUP_REG(CM_IDLEST_DPLL_CORE) & 0x00000001) != 0x00000001);
     364    uint32_t cm_clkmode_dpll_core;
     365    uint32_t cm_clksel_dpll_core;
     366    uint32_t cm_div_m4_dpll_core;
     367    uint32_t cm_div_m5_dpll_core;
     368    uint32_t cm_div_m6_dpll_core;
     369
     370    // Put Core PLL in MN Bypass mode
     371    cm_clkmode_dpll_core = CM_WKUP_REG(CM_CLKMODE_DPLL_CORE);
     372    cm_clkmode_dpll_core &= ~0x00000007;
     373    cm_clkmode_dpll_core |= 0x00000004;
     374    CM_WKUP_REG(CM_CLKMODE_DPLL_CORE) = cm_clkmode_dpll_core;
     375    // Wait for Core PLL to enter MN Bypass mode
     376    while((CM_WKUP_REG(CM_IDLEST_DPLL_CORE) & 0x00000101) != 0x00000100);
     377
     378    // Configure the multiplier and divider
     379    cm_clksel_dpll_core = CM_WKUP_REG(CM_CLKSEL_DPLL_CORE);
     380    cm_clksel_dpll_core &= ~0x0007FF7F;
     381    cm_clksel_dpll_core |= 1000 << 8;
     382    cm_clksel_dpll_core |= 23;
     383    CM_WKUP_REG(CM_CLKSEL_DPLL_CORE) = cm_clksel_dpll_core;
     384    // Configure the M4, M5, and M6 dividers
     385    cm_div_m4_dpll_core = CM_WKUP_REG(CM_DIV_M4_DPLL_CORE);
     386    cm_div_m4_dpll_core &= ~0x0000001F;
     387    cm_div_m4_dpll_core |= 10;
     388    CM_WKUP_REG(CM_DIV_M4_DPLL_CORE) = cm_div_m4_dpll_core;
     389    cm_div_m5_dpll_core = CM_WKUP_REG(CM_DIV_M5_DPLL_CORE);
     390    cm_div_m5_dpll_core &= ~0x0000001F;
     391    cm_div_m5_dpll_core |= 8;
     392    CM_WKUP_REG(CM_DIV_M5_DPLL_CORE) = cm_div_m5_dpll_core;
     393    cm_div_m6_dpll_core = CM_WKUP_REG(CM_DIV_M6_DPLL_CORE);
     394    cm_div_m6_dpll_core &= ~0x0000001F;
     395    cm_div_m6_dpll_core |= 4;
     396    CM_WKUP_REG(CM_DIV_M6_DPLL_CORE) = cm_div_m6_dpll_core;
     397
     398    // Lock Core PLL
     399    cm_clkmode_dpll_core = CM_WKUP_REG(CM_CLKMODE_DPLL_CORE);
     400    cm_clkmode_dpll_core &= ~0x00000007;
     401    cm_clkmode_dpll_core |= 0x00000007;
     402    CM_WKUP_REG(CM_CLKMODE_DPLL_CORE) = cm_clkmode_dpll_core;
     403    // Wait for Core PLL to lock
     404    while((CM_WKUP_REG(CM_IDLEST_DPLL_CORE) & 0x00000001) != 0x00000001);
    404405}
    405406
     
    407408ddr_pll_init(void)
    408409{
    409         uint32_t cm_clkmode_dpll_ddr;
    410         uint32_t cm_clksel_dpll_ddr;
    411         uint32_t cm_div_m2_dpll_ddr;
    412 
    413         // Put DDR PLL in MN Bypass mode
    414         cm_clkmode_dpll_ddr = CM_WKUP_REG(CM_CLKMODE_DPLL_DDR);
    415         cm_clkmode_dpll_ddr &= ~0x00000007;
    416         cm_clkmode_dpll_ddr |= 0x00000004;
    417         CM_WKUP_REG(CM_CLKMODE_DPLL_DDR) = cm_clkmode_dpll_ddr;
    418         // Wait for DDR PLL to enter MN Bypass mode
    419         while ((CM_WKUP_REG(CM_IDLEST_DPLL_DDR) & 0x00000101) != 0x00000100);
    420 
    421         // Set the DDR frequency to 400 MHz
    422         cm_clksel_dpll_ddr = CM_WKUP_REG(CM_CLKSEL_DPLL_DDR);
    423         cm_clksel_dpll_ddr &= ~0x0007FF7F;
    424         cm_clksel_dpll_ddr |= 400 << 8;
    425         cm_clksel_dpll_ddr |= 23;
    426         CM_WKUP_REG(CM_CLKSEL_DPLL_DDR) = cm_clksel_dpll_ddr;
    427         // Set M2 divider
    428         cm_div_m2_dpll_ddr = CM_WKUP_REG(CM_DIV_M2_DPLL_DDR);
    429         cm_div_m2_dpll_ddr &= ~0x0000001F;
    430         cm_div_m2_dpll_ddr |= 1;
    431         CM_WKUP_REG(CM_DIV_M2_DPLL_DDR) = cm_div_m2_dpll_ddr;
    432 
    433         // Lock the DDR PLL
    434         cm_clkmode_dpll_ddr = CM_WKUP_REG(CM_CLKMODE_DPLL_DDR);
    435         cm_clkmode_dpll_ddr &= ~0x00000007;
    436         cm_clkmode_dpll_ddr |= 0x00000007;
    437         CM_WKUP_REG(CM_CLKMODE_DPLL_DDR) = cm_clkmode_dpll_ddr;
    438         // Wait for DDR PLL to lock
    439         while ((CM_WKUP_REG(CM_IDLEST_DPLL_DDR) & 0x00000001) != 0x00000001);
     410    uint32_t cm_clkmode_dpll_ddr;
     411    uint32_t cm_clksel_dpll_ddr;
     412    uint32_t cm_div_m2_dpll_ddr;
     413
     414    // Put DDR PLL in MN Bypass mode
     415    cm_clkmode_dpll_ddr = CM_WKUP_REG(CM_CLKMODE_DPLL_DDR);
     416    cm_clkmode_dpll_ddr &= ~0x00000007;
     417    cm_clkmode_dpll_ddr |= 0x00000004;
     418    CM_WKUP_REG(CM_CLKMODE_DPLL_DDR) = cm_clkmode_dpll_ddr;
     419    // Wait for DDR PLL to enter MN Bypass mode
     420    while((CM_WKUP_REG(CM_IDLEST_DPLL_DDR) & 0x00000101) != 0x00000100);
     421
     422    // Set the DDR frequency to 400 MHz
     423    cm_clksel_dpll_ddr = CM_WKUP_REG(CM_CLKSEL_DPLL_DDR);
     424    cm_clksel_dpll_ddr &= ~0x0007FF7F;
     425    cm_clksel_dpll_ddr |= 400 << 8;
     426    cm_clksel_dpll_ddr |= 23;
     427    CM_WKUP_REG(CM_CLKSEL_DPLL_DDR) = cm_clksel_dpll_ddr;
     428    // Set M2 divider
     429    cm_div_m2_dpll_ddr = CM_WKUP_REG(CM_DIV_M2_DPLL_DDR);
     430    cm_div_m2_dpll_ddr &= ~0x0000001F;
     431    cm_div_m2_dpll_ddr |= 1;
     432    CM_WKUP_REG(CM_DIV_M2_DPLL_DDR) = cm_div_m2_dpll_ddr;
     433
     434    // Lock the DDR PLL
     435    cm_clkmode_dpll_ddr = CM_WKUP_REG(CM_CLKMODE_DPLL_DDR);
     436    cm_clkmode_dpll_ddr &= ~0x00000007;
     437    cm_clkmode_dpll_ddr |= 0x00000007;
     438    CM_WKUP_REG(CM_CLKMODE_DPLL_DDR) = cm_clkmode_dpll_ddr;
     439    // Wait for DDR PLL to lock
     440    while((CM_WKUP_REG(CM_IDLEST_DPLL_DDR) & 0x00000001) != 0x00000001);
    440441}
    441442
     
    443444per_pll_init(void)
    444445{
    445         uint32_t cm_clkmode_dpll_per;
    446         uint32_t cm_clksel_dpll_per;
    447         uint32_t cm_div_m2_dpll_per;
    448 
    449         // Put Per PLL in MN Bypass mode
    450         cm_clkmode_dpll_per = CM_WKUP_REG(CM_CLKMODE_DPLL_PER);
    451         cm_clkmode_dpll_per &= ~0x00000007;
    452         cm_clkmode_dpll_per |= 0x00000004;
    453         CM_WKUP_REG(CM_CLKMODE_DPLL_PER) = cm_clkmode_dpll_per;
    454         // Wait for Per PLL to enter MN Bypass mode
    455         while ((CM_WKUP_REG(CM_IDLEST_DPLL_PER) & 0x00000101) != 0x00000100);
    456 
    457         // Configure the multiplier and divider
    458         cm_clksel_dpll_per = CM_WKUP_REG(CM_CLKSEL_DPLL_PER);
    459         cm_clksel_dpll_per &= ~0xFF0FFFFF;
    460         cm_clksel_dpll_per |= CM_CLKSEL_DPLL_PER_DPLL_SD_DIV | CM_CLKSEL_DPLL_PER_DPLL_MULT |
    461                 CM_CLKSEL_DPLL_PER_DPLL_DIV;
    462         CM_WKUP_REG(CM_CLKSEL_DPLL_PER) = cm_clksel_dpll_per;
    463         // Set M2 divider
    464         cm_div_m2_dpll_per = CM_WKUP_REG(CM_DIV_M2_DPLL_PER);
    465         cm_div_m2_dpll_per &= ~0x0000007F;
    466         cm_div_m2_dpll_per |= 5;
    467         CM_WKUP_REG(CM_DIV_M2_DPLL_PER) = cm_div_m2_dpll_per;
    468 
    469         // Lock the Per PLL
    470         cm_clkmode_dpll_per = CM_WKUP_REG(CM_CLKMODE_DPLL_PER);
    471         cm_clkmode_dpll_per &= ~0x00000007;
    472         cm_clkmode_dpll_per |= 0x00000007;
    473         CM_WKUP_REG(CM_CLKMODE_DPLL_PER) = cm_clkmode_dpll_per;
    474         // Wait for Per PLL to lock
    475         while ((CM_WKUP_REG(CM_IDLEST_DPLL_PER) & 0x00000001) != 0x00000001);
     446    uint32_t cm_clkmode_dpll_per;
     447    uint32_t cm_clksel_dpll_per;
     448    uint32_t cm_div_m2_dpll_per;
     449
     450    // Put Per PLL in MN Bypass mode
     451    cm_clkmode_dpll_per = CM_WKUP_REG(CM_CLKMODE_DPLL_PER);
     452    cm_clkmode_dpll_per &= ~0x00000007;
     453    cm_clkmode_dpll_per |= 0x00000004;
     454    CM_WKUP_REG(CM_CLKMODE_DPLL_PER) = cm_clkmode_dpll_per;
     455    // Wait for Per PLL to enter MN Bypass mode
     456    while((CM_WKUP_REG(CM_IDLEST_DPLL_PER) & 0x00000101) != 0x00000100);
     457
     458    // Configure the multiplier and divider
     459    cm_clksel_dpll_per = CM_WKUP_REG(CM_CLKSEL_DPLL_PER);
     460    cm_clksel_dpll_per &= ~0xFF0FFFFF;
     461    cm_clksel_dpll_per |= CM_CLKSEL_DPLL_PER_DPLL_SD_DIV | CM_CLKSEL_DPLL_PER_DPLL_MULT |
     462                          CM_CLKSEL_DPLL_PER_DPLL_DIV;
     463    CM_WKUP_REG(CM_CLKSEL_DPLL_PER) = cm_clksel_dpll_per;
     464    // Set M2 divider
     465    cm_div_m2_dpll_per = CM_WKUP_REG(CM_DIV_M2_DPLL_PER);
     466    cm_div_m2_dpll_per &= ~0x0000007F;
     467    cm_div_m2_dpll_per |= 5;
     468    CM_WKUP_REG(CM_DIV_M2_DPLL_PER) = cm_div_m2_dpll_per;
     469
     470    // Lock the Per PLL
     471    cm_clkmode_dpll_per = CM_WKUP_REG(CM_CLKMODE_DPLL_PER);
     472    cm_clkmode_dpll_per &= ~0x00000007;
     473    cm_clkmode_dpll_per |= 0x00000007;
     474    CM_WKUP_REG(CM_CLKMODE_DPLL_PER) = cm_clkmode_dpll_per;
     475    // Wait for Per PLL to lock
     476    while((CM_WKUP_REG(CM_IDLEST_DPLL_PER) & 0x00000001) != 0x00000001);
    476477}
    477478
     
    479480pll_init(void)
    480481{
    481         mpu_pll_init();
    482         core_pll_init();
    483         ddr_pll_init();
    484         per_pll_init();
     482    mpu_pll_init();
     483    core_pll_init();
     484    ddr_pll_init();
     485    per_pll_init();
    485486}
    486487
     
    488489ddr_init(void)
    489490{
    490         uint32_t reg;
    491 
    492         // Enable the control module:
    493         CM_WKUP_REG(CM_WKUP_CONTROL_CLKCTRL) |= 2;
    494 
    495         // Enable EMIF module
    496         reg = CM_PER_REG(CM_PER_EMIF_CLKCTRL);
    497         reg &= ~3;
    498         reg |= 2;
    499         CM_PER_REG(CM_PER_EMIF_CLKCTRL) = reg;
    500         while ((CM_PER_REG(CM_PER_L3_CLKSTCTRL) & 0x00000004) != 0x00000004);
    501 
    502         // Configure VTP control
    503         CNTL_MODULE_REG(VTP_CTRL) |= 0x00000040;
    504         CNTL_MODULE_REG(VTP_CTRL) &= ~1;
    505         CNTL_MODULE_REG(VTP_CTRL) |= 1;
    506         // Wait for VTP control to be ready
    507         while ((CNTL_MODULE_REG(VTP_CTRL) & 0x00000020) != 0x00000020);
    508 
    509         // Configure the DDR PHY CMDx/DATAx registers
    510         DDR_PHY_REG(CMD0_REG_PHY_CTRL_SLAVE_RATIO_0) = 0x80;
    511         DDR_PHY_REG(CMD0_REG_PHY_INVERT_CLKOUT_0) = 0;
    512         DDR_PHY_REG(CMD1_REG_PHY_CTRL_SLAVE_RATIO_0) = 0x80;
    513         DDR_PHY_REG(CMD1_REG_PHY_INVERT_CLKOUT_0) = 0;
    514         DDR_PHY_REG(CMD2_REG_PHY_CTRL_SLAVE_RATIO_0) = 0x80;
    515         DDR_PHY_REG(CMD2_REG_PHY_INVERT_CLKOUT_0) = 0;
    516 
    517         DDR_PHY_REG(DATA0_REG_PHY_RD_DQS_SLAVE_RATIO_0) = 0x3A;
    518         DDR_PHY_REG(DATA0_REG_PHY_WR_DQS_SLAVE_RATIO_0) = 0x45;
    519         DDR_PHY_REG(DATA0_REG_PHY_WR_DATA_SLAVE_RATIO_0) = 0x7C;
    520         DDR_PHY_REG(DATA0_REG_PHY_FIFO_WE_SLAVE_RATIO_0) = 0x96;
    521 
    522         DDR_PHY_REG(DATA1_REG_PHY_RD_DQS_SLAVE_RATIO_0) = 0x3A;
    523         DDR_PHY_REG(DATA1_REG_PHY_WR_DQS_SLAVE_RATIO_0) = 0x45;
    524         DDR_PHY_REG(DATA1_REG_PHY_WR_DATA_SLAVE_RATIO_0) = 0x7C;
    525         DDR_PHY_REG(DATA1_REG_PHY_FIFO_WE_SLAVE_RATIO_0) = 0x96;
    526 
    527         CNTL_MODULE_REG(DDR_CMD0_IOCTRL) = 0x018B;
    528         CNTL_MODULE_REG(DDR_CMD1_IOCTRL) = 0x018B;
    529         CNTL_MODULE_REG(DDR_CMD2_IOCTRL) = 0x018B;
    530         CNTL_MODULE_REG(DDR_DATA0_IOCTRL) = 0x018B;
    531         CNTL_MODULE_REG(DDR_DATA1_IOCTRL) = 0x018B;
    532 
    533         CNTL_MODULE_REG(DDR_IO_CTRL) &= ~0x10000000;
    534 
    535         CNTL_MODULE_REG(DDR_CKE_CTRL) |= 0x00000001;
    536 
    537         // Enable dynamic power down when no read is being performed and set read latency
    538         // to CAS Latency + 2 - 1
    539         EMIF0_REG(DDR_PHY_CTRL_1) = 0x00100007;
    540         EMIF0_REG(DDR_PHY_CTRL_1_SHDW) = 0x00100007;
    541 
    542         // Configure the AC timing characteristics
    543         EMIF0_REG(SDRAM_TIM_1) = 0x0AAAD4DB;
    544         EMIF0_REG(SDRAM_TIM_1_SHDW) = 0x0AAAD4DB;
    545         EMIF0_REG(SDRAM_TIM_2) = 0x266B7FDA;
    546         EMIF0_REG(SDRAM_TIM_2_SHDW) = 0x266B7FDA;
    547         EMIF0_REG(SDRAM_TIM_3) = 0x501F867F;
    548         EMIF0_REG(SDRAM_TIM_3_SHDW) = 0x501F867F;
    549 
    550         // Set the refresh rate, 400,000,000 * 7.8 * 10^-6 = 3120 = 0x0C30
    551         EMIF0_REG(SDRAM_REF_CTRL) = 0x00000C30;
    552         // set the referesh rate shadow register to the same value as previous
    553         EMIF0_REG(SDRAM_REF_CTRL_SHDW) = 0x00000C30;
    554 
    555         // Configure the ZQ Calibration
    556         EMIF0_REG(ZQ_CONFIG) = 0x50074BE4;
    557 
    558         // Configure the SDRAM characteristics
    559         reg |= SDRAM_CONFIG_REG_SDRAM_TYPE_DDR3 | SDRAM_CONFIG_REG_IBANK_POS_0 |
    560                 SDRAM_CONFIG_REG_DDR_TERM_DDR3_RZQ_4 | SDRAM_CONFIG_REG_DDR2_DDQS_DIFF_DQS |
    561                 SDRAM_CONFIG_REG_DYN_ODT_RZQ_2 | SDRAM_CONFIG_REG_DDR_DISABLE_DLL_ENABLE |
    562                 SDRAM_CONFIG_REG_SDRAM_DRIVE_RZQ_6 | SDRAM_CONFIG_REG_CAS_WR_LATENCY_5 |
    563                 SDRAM_CONFIG_REG_NARROW_MODE_16BIT | SDRAM_CONFIG_REG_CAS_LATENCY_6 |
    564                 SDRAM_CONFIG_REG_ROWSIZE_15BIT | SDRAM_CONFIG_REG_IBANK_8 |
    565                 SDRAM_CONFIG_REG_EBANK_1 | SDRAM_CONFIG_REG_PAGESIZE_1024_WORD;
    566         EMIF0_REG(SDRAM_CONFIG) = reg;
    567         CNTL_MODULE_REG(CONTROL_EMIF_SDRAM_CONFIG) = reg;
    568 
    569         // Set the external bank position to 0
    570         EMIF0_REG(SDRAM_CONFIG_2) |= SDRAM_CONFIG_2_REG_EBANK_POS_0;
    571 }
     491    uint32_t reg;
     492
     493    // Enable the control module:
     494    CM_WKUP_REG(CM_WKUP_CONTROL_CLKCTRL) |= 2;
     495
     496    // Enable EMIF module
     497    reg = CM_PER_REG(CM_PER_EMIF_CLKCTRL);
     498    reg &= ~3;
     499    reg |= 2;
     500    CM_PER_REG(CM_PER_EMIF_CLKCTRL) = reg;
     501    while((CM_PER_REG(CM_PER_L3_CLKSTCTRL) & 0x00000004) != 0x00000004);
     502
     503    // Configure VTP control
     504    CNTL_MODULE_REG(VTP_CTRL) |= 0x00000040;
     505    CNTL_MODULE_REG(VTP_CTRL) &= ~1;
     506    CNTL_MODULE_REG(VTP_CTRL) |= 1;
     507    // Wait for VTP control to be ready
     508    while((CNTL_MODULE_REG(VTP_CTRL) & 0x00000020) != 0x00000020);
     509
     510    // Configure the DDR PHY CMDx/DATAx registers
     511    DDR_PHY_REG(CMD0_REG_PHY_CTRL_SLAVE_RATIO_0) = 0x80;
     512    DDR_PHY_REG(CMD0_REG_PHY_INVERT_CLKOUT_0) = 0;
     513    DDR_PHY_REG(CMD1_REG_PHY_CTRL_SLAVE_RATIO_0) = 0x80;
     514    DDR_PHY_REG(CMD1_REG_PHY_INVERT_CLKOUT_0) = 0;
     515    DDR_PHY_REG(CMD2_REG_PHY_CTRL_SLAVE_RATIO_0) = 0x80;
     516    DDR_PHY_REG(CMD2_REG_PHY_INVERT_CLKOUT_0) = 0;
     517
     518    DDR_PHY_REG(DATA0_REG_PHY_RD_DQS_SLAVE_RATIO_0) = 0x3A;
     519    DDR_PHY_REG(DATA0_REG_PHY_WR_DQS_SLAVE_RATIO_0) = 0x45;
     520    DDR_PHY_REG(DATA0_REG_PHY_WR_DATA_SLAVE_RATIO_0) = 0x7C;
     521    DDR_PHY_REG(DATA0_REG_PHY_FIFO_WE_SLAVE_RATIO_0) = 0x96;
     522
     523    DDR_PHY_REG(DATA1_REG_PHY_RD_DQS_SLAVE_RATIO_0) = 0x3A;
     524    DDR_PHY_REG(DATA1_REG_PHY_WR_DQS_SLAVE_RATIO_0) = 0x45;
     525    DDR_PHY_REG(DATA1_REG_PHY_WR_DATA_SLAVE_RATIO_0) = 0x7C;
     526    DDR_PHY_REG(DATA1_REG_PHY_FIFO_WE_SLAVE_RATIO_0) = 0x96;
     527
     528    CNTL_MODULE_REG(DDR_CMD0_IOCTRL) = 0x018B;
     529    CNTL_MODULE_REG(DDR_CMD1_IOCTRL) = 0x018B;
     530    CNTL_MODULE_REG(DDR_CMD2_IOCTRL) = 0x018B;
     531    CNTL_MODULE_REG(DDR_DATA0_IOCTRL) = 0x018B;
     532    CNTL_MODULE_REG(DDR_DATA1_IOCTRL) = 0x018B;
     533
     534    CNTL_MODULE_REG(DDR_IO_CTRL) &= ~0x10000000;
     535
     536    CNTL_MODULE_REG(DDR_CKE_CTRL) |= 0x00000001;
     537
     538    // Enable dynamic power down when no read is being performed and set read latency
     539    // to CAS Latency + 2 - 1
     540    EMIF0_REG(DDR_PHY_CTRL_1) = 0x00100007;
     541    EMIF0_REG(DDR_PHY_CTRL_1_SHDW) = 0x00100007;
     542
     543    // Configure the AC timing characteristics
     544    EMIF0_REG(SDRAM_TIM_1) = 0x0AAAD4DB;
     545    EMIF0_REG(SDRAM_TIM_1_SHDW) = 0x0AAAD4DB;
     546    EMIF0_REG(SDRAM_TIM_2) = 0x266B7FDA;
     547    EMIF0_REG(SDRAM_TIM_2_SHDW) = 0x266B7FDA;
     548    EMIF0_REG(SDRAM_TIM_3) = 0x501F867F;
     549    EMIF0_REG(SDRAM_TIM_3_SHDW) = 0x501F867F;
     550
     551    // Set the refresh rate, 400,000,000 * 7.8 * 10^-6 = 3120 = 0x0C30
     552    EMIF0_REG(SDRAM_REF_CTRL) = 0x00000C30;
     553    // set the referesh rate shadow register to the same value as previous
     554    EMIF0_REG(SDRAM_REF_CTRL_SHDW) = 0x00000C30;
     555
     556    // Configure the ZQ Calibration
     557    EMIF0_REG(ZQ_CONFIG) = 0x50074BE4;
     558
     559    // Configure the SDRAM characteristics
     560    reg |= SDRAM_CONFIG_REG_SDRAM_TYPE_DDR3 | SDRAM_CONFIG_REG_IBANK_POS_0 |
     561           SDRAM_CONFIG_REG_DDR_TERM_DDR3_RZQ_4 | SDRAM_CONFIG_REG_DDR2_DDQS_DIFF_DQS |
     562           SDRAM_CONFIG_REG_DYN_ODT_RZQ_2 | SDRAM_CONFIG_REG_DDR_DISABLE_DLL_ENABLE |
     563           SDRAM_CONFIG_REG_SDRAM_DRIVE_RZQ_6 | SDRAM_CONFIG_REG_CAS_WR_LATENCY_5 |
     564           SDRAM_CONFIG_REG_NARROW_MODE_16BIT | SDRAM_CONFIG_REG_CAS_LATENCY_6 |
     565           SDRAM_CONFIG_REG_ROWSIZE_15BIT | SDRAM_CONFIG_REG_IBANK_8 |
     566           SDRAM_CONFIG_REG_EBANK_1 | SDRAM_CONFIG_REG_PAGESIZE_1024_WORD;
     567    EMIF0_REG(SDRAM_CONFIG) = reg;
     568    CNTL_MODULE_REG(CONTROL_EMIF_SDRAM_CONFIG) = reg;
     569
     570    // Set the external bank position to 0
     571    EMIF0_REG(SDRAM_CONFIG_2) |= SDRAM_CONFIG_2_REG_EBANK_POS_0;
     572}
  • ports/beagleboneblack/cpuio.h

    rd355df2 r976c170  
    11#define DEFAULT_BAUD_RATE 115200
    22
    3 #define HWREAD32(a)     *(volatile unsigned long *)(a)
    4 #define HWREAD16(a)     *(volatile unsigned short *)(a)
    5 #define HWREAD8(a)      *(volatile unsigned char *)(a)
     3#define HWREAD32(a) *(volatile unsigned long *)(a)
     4#define HWREAD16(a) *(volatile unsigned short *)(a)
     5#define HWREAD8(a)  *(volatile unsigned char *)(a)
    66
    7 #define HWWRITE32(a,b)  *(volatile unsigned long *)(a) = (b)
    8 #define HWWRITE16(a,b)  *(volatile unsigned short *)(a) = (b)
    9 #define HWWRITE8(a,b)   *(volatile unsigned char *)(a) = (b)
     7#define HWWRITE32(a,b)  *(volatile unsigned long *)(a) = (b)
     8#define HWWRITE16(a,b)  *(volatile unsigned short *)(a) = (b)
     9#define HWWRITE8(a,b)   *(volatile unsigned char *)(a) = (b)
    1010
    1111#define GPIO1_21    (1<<21)
  • ports/beagleboneblack/etherdev.c

    rd355df2 r976c170  
    88// Contributors: Luis Torrico, Cogent Computer Systems, Inc.
    99// Date:         05-26-2002
    10 // Modified:    06-26-2007
     10// Modified:    06-26-2007
    1111// Description:  This file contains the interface layer between Micro Monitor
    1212//               and the Ethernet driver for the LAN921x on the CSB733.
     
    3737/*
    3838 * enreset():
    39  *      Reset the PHY and MAC.
     39 *  Reset the PHY and MAC.
    4040 */
    4141void
    4242enreset(void)
    4343{
    44         smsc911x_reset();
     44    smsc911x_reset();
    4545}
    4646
     
    5858eninit(void)
    5959{
    60         return smsc911x_init();
     60    return smsc911x_init();
    6161
    6262}
     
    6565EtherdevStartup(int verbose)
    6666{
    67         /* Initialize local device error counts (if any) here. */
    68         /* OPT_ADD_CODE_HERE */
    69 
    70         /* Put ethernet controller in reset: */
    71         enreset();
    72 
    73         /* Initialize controller: */
    74         eninit();
    75 
    76         return(0);
     67    /* Initialize local device error counts (if any) here. */
     68    /* OPT_ADD_CODE_HERE */
     69
     70    /* Put ethernet controller in reset: */
     71    enreset();
     72
     73    /* Initialize controller: */
     74    eninit();
     75
     76    return(0);
    7777}
    7878
     
    8383disablePromiscuousReception(void)
    8484{
    85         smsc911x_disable_promiscuous_reception();
     85    smsc911x_disable_promiscuous_reception();
    8686}
    8787
     
    9292enablePromiscuousReception(void)
    9393{
    94         smsc911x_enable_promiscuous_reception();
     94    smsc911x_enable_promiscuous_reception();
    9595}
    9696
     
    101101disableBroadcastReception(void)
    102102{
    103         smsc911x_disable_broadcast_reception();
     103    smsc911x_disable_broadcast_reception();
    104104}
    105105
     
    110110enableBroadcastReception(void)
    111111{
    112         smsc911x_enable_broadcast_reception();
     112    smsc911x_enable_broadcast_reception();
    113113}
    114114
     
    116116disableMulticastReception(void)
    117117{
    118         smsc911x_disable_multicast_reception();
     118    smsc911x_disable_multicast_reception();
    119119}
    120120
     
    122122enableMulticastReception(void)
    123123{
    124         smsc911x_enable_multicast_reception();
    125 }
    126 
    127 
    128 /* 
     124    smsc911x_enable_multicast_reception();
     125}
     126
     127
     128/*
    129129 * enselftest():
    130  *      Run a self test of the ethernet device(s).  This can be stubbed
    131  *      with a return(1).
    132  *      Return 1 if success; else -1 if failure.
     130 *  Run a self test of the ethernet device(s).  This can be stubbed
     131 *  with a return(1).
     132 *  Return 1 if success; else -1 if failure.
    133133 */
    134134int
    135135enselftest(int verbose)
    136136{
    137         return(1);
     137    return(1);
    138138}
    139139
     
    145145ShowEtherdevStats(void)
    146146{
    147         /* OPT_ADD_CODE_HERE */
     147    /* OPT_ADD_CODE_HERE */
    148148}
    149149
     
    157157getXmitBuffer(void)
    158158{
    159         return((uchar *) tx_buf);
     159    return((uchar *) tx_buf);
    160160}
    161161
     
    167167sendBuffer(int length)
    168168{
    169         ulong temp32;
    170 
    171     if (length < 64)
     169    ulong temp32;
     170
     171    if(length < 64) {
    172172        length = 64;
    173 
    174         if (EtherVerbose &  SHOW_OUTGOING)
    175                 printPkt((struct ether_header *)tx_buf,length,ETHER_OUTGOING);
    176 
    177         // tell the cs8900a to send the tx buffer pointed to by tx_buf
    178         temp32 = smsc911x_tx((ulong)tx_buf, (ulong)length);
    179 
    180         EtherXFRAMECnt++;
    181         if (temp32) {
    182                 return -1;
    183         }
    184         else {
    185                 return 0;
    186         }
     173    }
     174
     175    if(EtherVerbose &  SHOW_OUTGOING) {
     176        printPkt((struct ether_header *)tx_buf,length,ETHER_OUTGOING);
     177    }
     178
     179    // tell the cs8900a to send the tx buffer pointed to by tx_buf
     180    temp32 = smsc911x_tx((ulong)tx_buf, (ulong)length);
     181
     182    EtherXFRAMECnt++;
     183    if(temp32) {
     184        return -1;
     185    } else {
     186        return 0;
     187    }
    187188}
    188189
     
    193194DisableEtherdev(void)
    194195{
    195         enreset();
     196    enreset();
    196197}
    197198
     
    204205extGetIpAdd(void)
    205206{
    206         return((char *)0);
     207    return((char *)0);
    207208}
    208209
     
    215216extGetEtherAdd(void)
    216217{
    217         return((char *)0);
     218    return((char *)0);
    218219}
    219220
     
    226227polletherdev(void)
    227228{
    228         ulong pktbuf[RBUFSIZE/4];
    229         int     pktlen, pktcnt = 0;
    230 
    231         pktlen = smsc911x_rx((uchar *)pktbuf);
    232 
    233         if(pktlen) {
    234                 pktcnt = 1;
    235                 EtherRFRAMECnt++;
    236                 processPACKET((struct ether_header *)pktbuf, pktlen);
    237         }
    238         return(pktcnt);
     229    ulong pktbuf[RBUFSIZE/4];
     230    int pktlen, pktcnt = 0;
     231
     232    pktlen = smsc911x_rx((uchar *)pktbuf);
     233
     234    if(pktlen) {
     235        pktcnt = 1;
     236        EtherRFRAMECnt++;
     237        processPACKET((struct ether_header *)pktbuf, pktlen);
     238    }
     239    return(pktcnt);
    239240}
    240241
  • ports/beagleboneblack/tfsdev.h

    rd355df2 r976c170  
    1111
    1212struct tfsdev tfsdevtbl[] = {
    13     {   "//FLASH/",
     13    {
     14        "//FLASH/",
    1415        TFSSTART,
    1516        TFSEND,
     
    1718        TFSSPARESIZE,
    1819        TFSSECTORCOUNT,
    19         TFS_DEVTYPE_FLASH, },
     20        TFS_DEVTYPE_FLASH,
     21    },
    2022
    2123#ifdef FLASHRAM_BASE
    22     {   "//RAM/",
     24    {
     25        "//RAM/",
    2326        FLASHRAM_BASE,
    2427        FLASHRAM_END-FLASHRAM_SECTORSIZE,
     
    2629        FLASHRAM_SECTORSIZE,
    2730        FLASHRAM_SECTORCOUNT-1,
    28         TFS_DEVTYPE_RAM | TFS_DEVINFO_AUTOINIT, },
     31        TFS_DEVTYPE_RAM | TFS_DEVINFO_AUTOINIT,
     32    },
    2933#endif
    3034    { 0, TFSEOT,0,0,0,0,0 }
  • ports/beagleboneblack/xcmdtbl.h

    rd355df2 r976c170  
    1010*/
    1111
    12 {"mmc",         mmc,            mmcHelp,        0},
     12{"mmc",     mmc,        mmcHelp,    0},
Note: See TracChangeset for help on using the changeset viewer.