Changeset 9704d86f in rtems for cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h

Timestamp:

Jun 26, 2018, 6:53:28 AM (3 years ago)

Author:

Sebastian Huber <sebastian.huber@…>

Branches:

5, master

Children:

98f051e

Parents:

0fd8287

git-author:

Sebastian Huber <sebastian.huber@…> (06/26/18 06:53:28)

git-committer:

Sebastian Huber <sebastian.huber@…> (06/29/18 08:04:32)

Message:

riscv: Enable interrupts during dispatch after ISR

The code sequence is derived from the ARM code
(see _ARMV4_Exception_interrupt).

Update #2751.
Update #3433.

File:

• cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h (modified) (1 diff)

cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h

@@ -39 +39 @@
 #if __riscv_xlen == 32
 
+#define RISCV_CONTEXT_ISR_DISPATCH_DISABLE 140
+
 #define CPU_INTERRUPT_FRAME_SIZE 144
 
 #elif __riscv_xlen == 64
+
+#define RISCV_CONTEXT_ISR_DISPATCH_DISABLE 280
 
 #define CPU_INTERRUPT_FRAME_SIZE 288