Ignore:
Timestamp:
Jun 26, 2018, 6:53:28 AM (3 years ago)
Author:
Sebastian Huber <sebastian.huber@…>
Branches:
5, master
Children:
98f051e
Parents:
0fd8287
git-author:
Sebastian Huber <sebastian.huber@…> (06/26/18 06:53:28)
git-committer:
Sebastian Huber <sebastian.huber@…> (06/29/18 08:04:32)
Message:

riscv: Enable interrupts during dispatch after ISR

The code sequence is derived from the ARM code
(see _ARMV4_Exception_interrupt).

Update #2751.
Update #3433.

File:
1 edited

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