Changeset 9704d86f in rtems


Ignore:
Timestamp:
Jun 26, 2018, 6:53:28 AM (10 months ago)
Author:
Sebastian Huber <sebastian.huber@…>
Branches:
master
Children:
98f051e
Parents:
0fd8287
git-author:
Sebastian Huber <sebastian.huber@…> (06/26/18 06:53:28)
git-committer:
Sebastian Huber <sebastian.huber@…> (06/29/18 08:04:32)
Message:

riscv: Enable interrupts during dispatch after ISR

The code sequence is derived from the ARM code
(see _ARMV4_Exception_interrupt).

Update #2751.
Update #3433.

Location:
cpukit/score/cpu/riscv
Files:
5 edited

Legend:

Unmodified
Added
Removed
  • cpukit/score/cpu/riscv/cpu.c

    r0fd8287 r9704d86f  
    11/*
    2  * RISC-V CPU Dependent Source
     2 * Copyright (c) 2018 embedded brains GmbH
    33 *
    44 * Copyright (c) 2015 University of York.
     
    3030 */
    3131
    32 #include <rtems/score/cpu.h>
     32#include <rtems/score/cpuimpl.h>
    3333#include <rtems/score/isr.h>
    3434#include <rtems/score/riscv-utility.h>
     35
     36#define RISCV_ASSERT_CONTEXT_OFFSET( field, off ) \
     37  RTEMS_STATIC_ASSERT( \
     38    offsetof( Context_Control, field) == RISCV_CONTEXT_ ## off, \
     39    riscv_context_offset_ ## field \
     40  )
     41
     42RISCV_ASSERT_CONTEXT_OFFSET( isr_dispatch_disable, ISR_DISPATCH_DISABLE );
    3543
    3644/* bsp_start_vector_table_begin is the start address of the vector table
  • cpukit/score/cpu/riscv/include/rtems/score/cpu.h

    r0fd8287 r9704d86f  
    44
    55/*
     6 * Copyright (c) 2018 embedded brains GmbH
    67 *
    78 * Copyright (c) 2015 University of York.
     
    7677  unsigned long mcause;
    7778  unsigned long mepc;
     79  uint32_t isr_dispatch_disable;
    7880#ifdef RTEMS_SMP
    7981  volatile bool is_executing;
  • cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h

    r0fd8287 r9704d86f  
    3939#if __riscv_xlen == 32
    4040
     41#define RISCV_CONTEXT_ISR_DISPATCH_DISABLE 140
     42
    4143#define CPU_INTERRUPT_FRAME_SIZE 144
    4244
    4345#elif __riscv_xlen == 64
     46
     47#define RISCV_CONTEXT_ISR_DISPATCH_DISABLE 280
    4448
    4549#define CPU_INTERRUPT_FRAME_SIZE 288
  • cpukit/score/cpu/riscv/riscv-context-switch.S

    r0fd8287 r9704d86f  
    11/*
    2  * riscv32 CPU Dependent Source
     2 * Copyright (c) 2018 embedded brains GmbH
    33 *
    44 * Copyright (c) 2015 University of York.
     
    3232
    3333#include <rtems/asm.h>
    34 #include <rtems/score/cpu.h>
    35 #include <rtems/score/riscv-utility.h>
     34#include <rtems/score/percpu.h>
    3635
    3736        .section        .text, "ax", @progbits
     
    4241PUBLIC(_CPU_Context_restore_fp)
    4342PUBLIC(_CPU_Context_save_fp)
    44 PUBLIC(restore)
    4543
    4644SYM(_CPU_Context_switch):
     45        GET_SELF_CPU_CONTROL    a2
     46        lw      a3, PER_CPU_ISR_DISPATCH_DISABLE(a2)
     47
    4748        /* Disable interrupts and store all registers */
    4849        csrr    t0, mstatus
    4950        SREG    t0, (32 * CPU_SIZEOF_POINTER)(a0)
    5051
    51         csrci   mstatus, MSTATUS_MIE
     52        csrci   mstatus, RISCV_MSTATUS_MIE
    5253
    5354        SREG    x1, (1 * CPU_SIZEOF_POINTER)(a0)
     
    8283        SREG    x31, (31 * CPU_SIZEOF_POINTER)(a0)
    8384
    84         SYM(restore):
     85        sw      a3, RISCV_CONTEXT_ISR_DISPATCH_DISABLE(a0)
     86
     87.Lrestore:
     88        lw      a3, RISCV_CONTEXT_ISR_DISPATCH_DISABLE(a1)
     89
     90        sw      a3, PER_CPU_ISR_DISPATCH_DISABLE(a2)
    8591
    8692        LREG    x1, (1 * CPU_SIZEOF_POINTER)(a1)
     
    124130        ret
    125131
    126         SYM(_CPU_Context_restore):
     132SYM(_CPU_Context_restore):
    127133        mv      a1, a0
    128         j       restore
     134        GET_SELF_CPU_CONTROL    a2
     135        j       .Lrestore
    129136
    130137        /* TODO no FP support for riscv32 yet */
  • cpukit/score/cpu/riscv/riscv-exception-handler.S

    r0fd8287 r9704d86f  
    88
    99/*
     10 * Copyright (c) 2018 embedded brains GmbH
     11
    1012 * Copyright (c) 2015 University of York.
    1113 * Hesham Almatary <hesham@alumni.york.ac.uk>
     
    3638#include "config.h"
    3739#endif
    38 
    39 #include <rtems/score/cpu.h>
    4040
    4141#include <rtems/asm.h>
     
    9696        andi    a0, a0, 0xf
    9797
    98         /* Increment nesting level */
    99         la      t0, ISR_NEST_LEVEL
    100 
    101         /* Disable multitasking */
    102         la      t1, THREAD_DISPATCH_DISABLE_LEVEL
    103 
    104         lw      t2, (t0)
    105         lw      t3, (t1)
    106         addi    t2, t2, 1
    107         addi    t3, t3, 1
    108         sw      t2, (t0)
    109         sw      t3, (t1)
     98        /* Get per-CPU control of current processor */
     99        GET_SELF_CPU_CONTROL    s0
     100
     101        /* Increment interrupt nest and thread dispatch disable level */
     102        lw      t0, PER_CPU_ISR_NEST_LEVEL(s0)
     103        lw      t1, PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL(s0)
     104        addi    t2, t0, 1
     105        addi    t1, t1, 1
     106        sw      t2, PER_CPU_ISR_NEST_LEVEL(s0)
     107        sw      t1, PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL(s0)
    110108
    111109        /* Save interrupted task stack pointer */
     
    133131        LREG    t5, (t5)
    134132
    135         /* Do not switch stacks if we are in a nested interrupt. At
    136                 * this point t2 should be holding ISR_NEST_LEVEL value.
    137                 */
    138         li      s0, 1
    139         bgtu    t2, s0, jump_to_c_handler
    140 
    141         /* Switch to RTEMS dedicated interrupt stack */
    142         la      sp, INTERRUPT_STACK_HIGH
    143         LREG    sp, (sp)
    144 
    145 jump_to_c_handler:
     133        /* Switch to interrupt stack if necessary */
     134        bnez    t0, .Linterrupt_stack_switch_done
     135        LREG    sp, PER_CPU_INTERRUPT_STACK_HIGH(s0)
     136.Linterrupt_stack_switch_done:
     137
    146138        jalr    t5
    147139
    148         /* Switch back to the interrupted task stack */
     140        /* Load some per-CPU variables */
     141        lw      t0, PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL(s0)
     142        lbu     t1, PER_CPU_DISPATCH_NEEDED(s0)
     143        lw      t2, PER_CPU_ISR_DISPATCH_DISABLE(s0)
     144        lw      t3, PER_CPU_ISR_NEST_LEVEL(s0)
     145
     146        /* Restore stack pointer */
    149147        mv      sp, s1
    150148
    151         /* Decrement nesting level */
    152         la      t0, ISR_NEST_LEVEL
    153 
    154         /* Enable multitasking */
    155         la      t1, THREAD_DISPATCH_DISABLE_LEVEL
    156 
    157         Lw      t2, (t0)
    158         lw      t3, (t1)
    159         addi    t2, t2, -1
     149        /* Decrement levels and determine thread dispatch state */
     150        xor     t1, t1, t0
     151        addi    t0, t0, -1
     152        or      t1, t1, t0
     153        or      t1, t1, t2
    160154        addi    t3, t3, -1
    161         sw      t2, (t0)
    162         sw      t3, (t1)
    163 
    164         /* Check if _ISR_Nest_level > 0 */
    165         bgtz    t2, exception_frame_restore
    166 
    167         /* Check if _Thread_Dispatch_disable_level > 0 */
    168         bgtz    t3, exception_frame_restore
    169 
    170         /* Check if dispatch needed */
    171         la      x31, DISPATCH_NEEDED
    172         lw      x31, (x31)
    173         beqz    x31, exception_frame_restore
    174 
    175         la      x31, _Thread_Dispatch
    176         jalr    x31
    177 
    178         SYM(exception_frame_restore):
     155
     156        /* Store thread dispatch disable and ISR nest levels */
     157        sw      t0, PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL(s0)
     158        sw      t3, PER_CPU_ISR_NEST_LEVEL(s0)
     159
     160        /*
     161         * Check thread dispatch necessary, ISR dispatch disable and thread
     162         * dispatch disable level.
     163         */
     164        bnez    t1, .Lthread_dispatch_done
     165
     166.Ldo_thread_dispatch:
     167
     168        /* Set ISR dispatch disable and thread dispatch disable level to one */
     169        li      t0, 1
     170        sw      t0, PER_CPU_ISR_DISPATCH_DISABLE(s0)
     171        sw      t0, PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL(s0)
     172
     173        /* Call _Thread_Do_dispatch(), this function will enable interrupts */
     174        mv      a0, s0
     175        li      a1, RISCV_MSTATUS_MIE
     176        call    _Thread_Do_dispatch
     177
     178        /* Disable interrupts */
     179        csrrc   zero, mstatus, RISCV_MSTATUS_MIE
     180
     181#ifdef RTEMS_SMP
     182        GET_SELF_CPU_CONTROL    s0
     183#endif
     184
     185        /* Check if we have to do the thread dispatch again */
     186        lbu     t0, PER_CPU_DISPATCH_NEEDED(s0)
     187        bnez    t0, .Ldo_thread_dispatch
     188
     189        /* We are done with thread dispatching */
     190        sw      zero, PER_CPU_ISR_DISPATCH_DISABLE(s0)
     191
     192.Lthread_dispatch_done:
     193
    179194        LREG    x1, (1 * CPU_SIZEOF_POINTER)(sp)
    180195        /* Skip sp/x2 */
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