Changeset 9647f7fe in rtems


Ignore:
Timestamp:
Feb 27, 2009, 11:26:44 AM (11 years ago)
Author:
Thomas Doerfler <Thomas.Doerfler@…>
Branches:
4.10, 4.11, master
Children:
949166d
Parents:
92cbf96
Message:
  • README: Added NCS.
  • Makefile.am, configure.ac, preinstall.am: Added BSP variants.
  • console/console-config.c, clock/clock-config.c, ssp/ssp.c: Fixed register settings. Cleanup.
  • include/bsp.h: Added network defines and functions.
  • include/lpc24xx.h: Added AHB and EMC defines. Fixed Ethernet status sizes.
  • include/system-clocks.h, misc/system-clocks.c: Added micro seconds delay function that uses Timer 1. Changed PLL setup.
  • network/network.c, startup/bspreset.c, startup/linkcmds.lpc2478, startup/linkcmds.lpc2478_ncs, startup/linkcmds.lpc2478_ncs_ram: New files.
  • startup/bspstart.c: Added EMC initialization. Changes for ROM boot.
Files:
23 edited

Legend:

Unmodified
Added
Removed
  • ChangeLog

    r92cbf96 r9647f7fe  
     12009-02-27      Sebastian Huber <sebastian.huber@embedded-brains.de>
     2
     3        * aclocal/bsp-alias.m4, aclocal/check-bsps.m4: Added defines for
     4        LPC2478 BSP variants.
     5
    162009-02-19      Joel Sherrill <joel.sherrill@oarcorp.com>
    27
  • aclocal/bsp-alias.m4

    r92cbf96 r9647f7fe  
    3939    rtl22xx_t)    $2=rtl22xx          ;; # rtl22xx bsp in thumb mode
    4040    lpc2478)      $2=lpc24xx          ;; # LPC2478 (QVGA Base Board from Embedded Artists)
     41    lpc2478_ncs)  $2=lpc24xx          ;; # LPC2478 (NCS)
     42    lpc2478_ncs_ram) $2=lpc24xx       ;; # LPC2478 (NCS, code and data in external RAM)
    4143    simcpu32)     $2=sim68000         ;; # BSVC CPU32 variant
    4244    simsh1)       $2=shsim            ;; # SH1 simulator in GDB
  • aclocal/check-bsps.m4

    r92cbf96 r9647f7fe  
    3636          erc32)             bsps="erc32 sis";;
    3737          rtl22xx)           bsps="rtl22xx rtl22xx_t";;
    38           lpc24xx)           bsps="lpc2478";;
     38          lpc24xx)           bsps="lpc2478 lpc2478_ncs lpc2478_ncs_ram";;
    3939          sim68000)          bsps="sim68000 simcpu32";;
    4040          shsim)             bsps="simsh1 simsh2 simsh4";;
  • c/src/lib/libbsp/arm/ChangeLog

    r92cbf96 r9647f7fe  
     12009-02-27      Sebastian Huber <sebastian.huber@embedded-brains.de>
     2
     3        * shared/startup/linkcmds.rom: New file
     4        * shared/include/start.h: Added declaration of start().
     5        * shared/start/start.S: Fixed vector table for ROM boot.
     6
    172008-09-23      Joel Sherrill <joel.sherrill@OARcorp.com>
    28
  • c/src/lib/libbsp/arm/lpc24xx/ChangeLog

    r92cbf96 r9647f7fe  
     12009-02-27      Sebastian Huber <sebastian.huber@embedded-brains.de>
     2
     3        * README: Added NCS.
     4        * Makefile.am, configure.ac, preinstall.am: Added BSP variants.
     5        * console/console-config.c, clock/clock-config.c, ssp/ssp.c: Fixed
     6        register settings.  Cleanup.
     7        * include/bsp.h: Added network defines and functions.
     8        * include/lpc24xx.h: Added AHB and EMC defines.  Fixed Ethernet status
     9        sizes.
     10        * include/system-clocks.h, misc/system-clocks.c: Added micro seconds
     11        delay function that uses Timer 1.  Changed PLL setup.
     12        * network/network.c, startup/bspreset.c, startup/linkcmds.lpc2478,
     13        startup/linkcmds.lpc2478_ncs, startup/linkcmds.lpc2478_ncs_ram: New
     14        files.
     15        * startup/bspstart.c: Added EMC initialization.  Changes for ROM boot.
     16
    1172009-02-17      Ralf Corsépius <ralf.corsepius@rtems.org>
    218
  • c/src/lib/libbsp/arm/lpc24xx/Makefile.am

    r92cbf96 r9647f7fe  
    2222include_HEADERS = include/bsp.h
    2323
    24 nodist_include_HEADERS = include/bspopts.h
     24nodist_include_HEADERS = ../../shared/include/coverhd.h \
     25        include/bspopts.h
    2526
    2627nodist_include_bsp_HEADERS = ../../shared/include/bootcard.h
    27 nodist_include_HEADERS += ../../shared/include/coverhd.h
    2828
    2929include_bsp_HEADERS =
    3030include_bsp_HEADERS += ../../shared/include/utility.h
    3131include_bsp_HEADERS += ../../shared/include/irq-generic.h
     32include_bsp_HEADERS += ../../shared/include/irq-info.h
    3233include_bsp_HEADERS += ../../shared/tod.h
    3334include_bsp_HEADERS += ../shared/include/linker-symbols.h
     
    3940include_bsp_HEADERS += include/ssp.h
    4041include_bsp_HEADERS += include/dma.h
     42
    4143include_HEADERS += ../../shared/include/tm27.h
    4244
     
    5254
    5355dist_project_lib_DATA += ../shared/startup/linkcmds.base \
    54         startup/linkcmds
     56        ../shared/startup/linkcmds.rom \
     57        startup/linkcmds.lpc2478 \
     58        startup/linkcmds.lpc2478_ncs \
     59        startup/linkcmds.lpc2478_ncs_ram
    5560
    5661###############################################################################
     
    6570libbsp_a_SOURCES += ../../shared/bootcard.c \
    6671        ../../shared/bspclean.c \
    67         ../../shared/bspreset.c \
    6872        ../../shared/bspgetworkarea.c \
    6973        ../../shared/bsplibc.c \
     
    7680
    7781# Startup
    78 libbsp_a_SOURCES += startup/bspstart.c
     82libbsp_a_SOURCES += startup/bspstart.c \
     83        startup/bspreset.c
    7984
    8085# IRQ
    8186libbsp_a_SOURCES += ../../shared/src/irq-generic.c \
    8287        ../../shared/src/irq-legacy.c \
     88        ../../shared/src/irq-info.c \
     89        ../../shared/src/irq-shell.c \
    8390        ../shared/irq/irq_asm.S \
    8491        irq/irq.c
     
    106113
    107114###############################################################################
     115#                  Network                                                    #
     116###############################################################################
     117
     118if HAS_NETWORKING
     119
     120noinst_PROGRAMS = network.rel
     121
     122network_rel_SOURCES = network/network.c
     123network_rel_CPPFLAGS = $(AM_CPPFLAGS) -D__INSIDE_RTEMS_BSD_TCPIP_STACK__ -D__BSD_VISIBLE
     124network_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
     125
     126libbsp_a_LIBADD = network.rel
     127
     128endif
     129
     130###############################################################################
    108131#                  Special Rules                                              #
    109132###############################################################################
  • c/src/lib/libbsp/arm/lpc24xx/README

    r92cbf96 r9647f7fe  
    88
    99Drivers:
     10
    1011        o Console
    1112        o Clock
    1213        o RTC
    1314        o SSP (SPI mode): This driver is in active development.  Use with care.
     15        o Network
     16
     17Howto setup QVGA Base Board?
     18
     19        o Unpack board.
     20        o Connect board via USB to your PC.
     21        o Verify that demo application runs.
     22        o Disconnect board.
     23        o Change jumpers to enable ISP.
     24        o Connect board.
     25        o Load U-Boot image 'u-boot_v1.1.6_lpc2468oem_v1_8_16bit.hex'
     26        (available from the EA support page) into the flash (flash tool
     27        FlashMagic is availabe from NXP).
     28        o Change jumbers back to disable ISP.
     29        o Use a terminal program to change the U-Boot settings via the console.
     30        o U-Boot settings:
     31                set ethaddr '00:1a:f1:X:X:X'
     32                set serverip 'X.X.X.X'
     33                set ipaddr 'X.X.X.X'
     34                set rtems 'tftp a1000000 lpc2478.img;bootm'
     35                set bootcmd 'echo Booting RTEMS ...;run rtems'
     36                saveenv
     37
     38Application Board: NCS (Nurse Control Station)
     39
     40        Board:      NextGenNCS
     41        Processor:  NXP LPC2478
     42        SDRAM:      8MByte, 16 bit wide
     43        Ext. Flash: 1MByte, 16 bit wide
     44        Console:    UART, 115200 Baud
     45        Network:    100Base-T
  • c/src/lib/libbsp/arm/lpc24xx/clock/clock-config.c

    r92cbf96 r9647f7fe  
    5858  /* Set timer pclk to cclk */
    5959  rtems_interrupt_disable( level);
    60   SET_PCLKSEL0_PCLK_TIMER0( PCLKSEL0, 1);
     60  PCONP = SET_FLAGS( PCONP, 0x02);
     61  PCLKSEL0 = SET_FLAGS( PCLKSEL0, 0x04);
    6162  rtems_interrupt_enable( level);
    6263
     
    107108static uint32_t lpc24xx_clock_nanoseconds_since_last_tick( void)
    108109{
    109   uint64_t clock = lpc24xx_cclk();
     110  uint64_t clock = LPC24XX_CCLK;
    110111  uint32_t clicks = T0TC;
    111112  uint64_t ns = ((uint64_t) clicks * 1000000000) / clock;
  • c/src/lib/libbsp/arm/lpc24xx/configure.ac

    r92cbf96 r9647f7fe  
    2424AM_CONDITIONAL(HAS_NETWORKING,test "$HAS_NETWORKING" = "yes")
    2525
    26 RTEMS_BSPOPTS_SET([LPC24XX_OSCILLATOR_MAIN],[lpc2478],
    27 [12000000U])
    28 RTEMS_BSPOPTS_HELP([LPC24XX_OSCILLATOR_MAIN],
    29 [Main oscillator frequency in Hz])
     26RTEMS_BSPOPTS_SET([LPC24XX_OSCILLATOR_MAIN],[*],[12000000U])
     27RTEMS_BSPOPTS_HELP([LPC24XX_OSCILLATOR_MAIN],[Main oscillator frequency in Hz])
    3028
    31 RTEMS_BSPOPTS_SET([LPC24XX_OSCILLATOR_RTC],[lpc2478],
    32 [32768])
    33 RTEMS_BSPOPTS_HELP([LPC24XX_OSCILLATOR_RTC],
    34 [RTC oscillator frequency in Hz])
     29RTEMS_BSPOPTS_SET([LPC24XX_OSCILLATOR_RTC],[*],[32768])
     30RTEMS_BSPOPTS_HELP([LPC24XX_OSCILLATOR_RTC],[RTC oscillator frequency in Hz])
     31
     32RTEMS_BSPOPTS_SET([LPC24XX_CCLK],[*],[72000000])
     33RTEMS_BSPOPTS_HELP([LPC24XX_CCLK],[CPU clock in Hz])
     34
     35RTEMS_BSPOPTS_SET([LPC24XX_UART_BAUD],[*],[115200])
     36RTEMS_BSPOPTS_HELP([LPC24XX_UART_BAUD],[Baud for UARTs])
     37
     38RTEMS_BSPOPTS_SET([LPC24XX_HAS_UBOOT],[lpc2478],[1])
     39RTEMS_BSPOPTS_SET([LPC24XX_HAS_UBOOT],[lpc2478_ncs_ram],[1])
     40RTEMS_BSPOPTS_HELP([LPC24XX_HAS_UBOOT],[Enable U-Boot startup])
     41
     42RTEMS_BSPOPTS_SET([LPC24XX_ETHERNET_RMII],[lpc2478_ncs],[1])
     43RTEMS_BSPOPTS_SET([LPC24XX_ETHERNET_RMII],[lpc2478_ncs_ram],[1])
     44RTEMS_BSPOPTS_HELP([LPC24XX_ETHERNET_RMII],[Enable RMII for Ethernet])
     45
     46RTEMS_BSPOPTS_SET([LPC24XX_EMC_MICRON],[lpc2478_ncs],[1])
     47RTEMS_BSPOPTS_HELP([LPC24XX_EMC_MICRON],[Enable RMII for Ethernet])
    3548
    3649BSP_BOOTCARD_OPTIONS
  • c/src/lib/libbsp/arm/lpc24xx/console/console-config.c

    r92cbf96 r9647f7fe  
    2222#include <libchip/ns16550.h>
    2323
     24#include <bsp.h>
    2425#include <bsp/lpc24xx.h>
    2526#include <bsp/irq.h>
     
    5657    .ulMargin = 16,
    5758    .ulHysteresis = 8,
    58     .pDeviceParams = (void *) 38400,
     59    .pDeviceParams = (void *) LPC24XX_UART_BAUD,
    5960    .ulCtrlPort1 = UART0_BASE_ADDR,
    6061    .ulCtrlPort2 = 0,
     
    6465    .getData = NULL,
    6566    .setData = NULL,
    66     .ulClock = 57600000,
     67    .ulClock = LPC24XX_CCLK,
    6768    .ulIntVector = LPC24XX_IRQ_UART_0
    6869  }
  • c/src/lib/libbsp/arm/lpc24xx/include/bsp.h

    r92cbf96 r9647f7fe  
    3636#ifndef ASM
    3737
     38/* Network driver configuration */
     39
     40struct rtems_bsdnet_ifconfig;
     41
     42int lpc24xx_eth_attach_detach(
     43  struct rtems_bsdnet_ifconfig *config,
     44  int attaching
     45);
     46
     47#define RTEMS_BSP_NETWORK_DRIVER_ATTACH lpc24xx_eth_attach_detach
     48
     49#define RTEMS_BSP_NETWORK_DRIVER_NAME "eth0"
     50
    3851#endif /* ASM */
    3952
  • c/src/lib/libbsp/arm/lpc24xx/include/lpc24xx.h

    r92cbf96 r9647f7fe  
    18551855  uint32_t status;
    18561856  uint32_t hash_crc;
    1857 } lpc24xx_eth_transfer_status;
     1857} lpc24xx_eth_receive_info;
    18581858
    18591859#define ETH_TRANSFER_DESCRIPTOR_SIZE 8
    18601860
    1861 #define ETH_TRANSFER_STATUS_SIZE 8
    1862 
    1863 #define ETH_TRANSFER_CTRL_SIZE \
    1864   (ETH_TRANSFER_DESCRIPTOR_SIZE + ETH_TRANSFER_STATUS_SIZE)
     1861#define ETH_RECEIVE_INFO_SIZE 8
     1862
     1863#define ETH_TRANSMIT_STATUS_SIZE 4
    18651864
    18661865/* ETH_RX_CTRL */
     
    20242023#define ETH_CMD_FULL_DUPLEX 0x00000400U
    20252024
     2025/* AHBCFG */
     2026
     2027#define AHBCFG_SCHEDULER_UNIFORM 0x00000001U
     2028
     2029#define AHBCFG_BREAK_BURST_MASK 0x00000006U
     2030
     2031#define GET_AHBCFG_BREAK_BURST( reg) \
     2032  GET_FIELD( reg, AHBCFG_BREAK_BURST_MASK, 1)
     2033
     2034#define SET_AHBCFG_BREAK_BURST( reg, val) \
     2035  SET_FIELD( reg, val, AHBCFG_BREAK_BURST_MASK, 1)
     2036
     2037#define AHBCFG_QUANTUM_BUS_CYCLE 0x00000008U
     2038
     2039#define AHBCFG_QUANTUM_SIZE_MASK 0x000000f0U
     2040
     2041#define GET_AHBCFG_QUANTUM_SIZE( reg) \
     2042  GET_FIELD( reg, AHBCFG_QUANTUM_SIZE_MASK, 4)
     2043
     2044#define SET_AHBCFG_QUANTUM_SIZE( reg, val) \
     2045  SET_FIELD( reg, val, AHBCFG_QUANTUM_SIZE_MASK, 4)
     2046
     2047#define AHBCFG_DEFAULT_MASTER_MASK 0x00000700U
     2048
     2049#define GET_AHBCFG_DEFAULT_MASTER( reg) \
     2050  GET_FIELD( reg, AHBCFG_DEFAULT_MASTER_MASK, 8)
     2051
     2052#define SET_AHBCFG_DEFAULT_MASTER( reg, val) \
     2053  SET_FIELD( reg, val, AHBCFG_DEFAULT_MASTER_MASK, 8)
     2054
     2055#define AHBCFG_EP1_MASK 0x00007000U
     2056
     2057#define GET_AHBCFG_EP1( reg) \
     2058  GET_FIELD( reg, AHBCFG_EP1_MASK, 12)
     2059
     2060#define SET_AHBCFG_EP1( reg, val) \
     2061  SET_FIELD( reg, val, AHBCFG_EP1_MASK, 12)
     2062
     2063#define AHBCFG_EP2_MASK 0x00070000U
     2064
     2065#define GET_AHBCFG_EP2( reg) \
     2066  GET_FIELD( reg, AHBCFG_EP2_MASK, 16)
     2067
     2068#define SET_AHBCFG_EP2( reg, val) \
     2069  SET_FIELD( reg, val, AHBCFG_EP2_MASK, 16)
     2070
     2071#define AHBCFG_EP3_MASK 0x00700000U
     2072
     2073#define GET_AHBCFG_EP3( reg) \
     2074  GET_FIELD( reg, AHBCFG_EP3_MASK, 20)
     2075
     2076#define SET_AHBCFG_EP3( reg, val) \
     2077  SET_FIELD( reg, val, AHBCFG_EP3_MASK, 20)
     2078
     2079#define AHBCFG_EP4_MASK 0x07000000U
     2080
     2081#define GET_AHBCFG_EP4( reg) \
     2082  GET_FIELD( reg, AHBCFG_EP4_MASK, 24)
     2083
     2084#define SET_AHBCFG_EP4( reg, val) \
     2085  SET_FIELD( reg, val, AHBCFG_EP4_MASK, 24)
     2086
     2087#define AHBCFG_EP5_MASK 0x70000000U
     2088
     2089#define GET_AHBCFG_EP5( reg) \
     2090  GET_FIELD( reg, AHBCFG_EP5_MASK, 28)
     2091
     2092#define SET_AHBCFG_EP5( reg, val) \
     2093  SET_FIELD( reg, val, AHBCFG_EP5_MASK, 28)
     2094
     2095/* EMC */
     2096
     2097#define EMC_DYN_CTRL_CE 0x00000001U
     2098
     2099#define EMC_DYN_CTRL_CS 0x00000002U
     2100
     2101#define EMC_DYN_CTRL_CMD_NORMAL 0x00000000U
     2102
     2103#define EMC_DYN_CTRL_CMD_MODE 0x00000080U
     2104
     2105#define EMC_DYN_CTRL_CMD_PALL 0x00000100U
     2106
     2107#define EMC_DYN_CTRL_CMD_NOP 0x00000180U
     2108
    20262109#endif /* LIBBSP_ARM_LPC24XX_LPC24XX_H */
  • c/src/lib/libbsp/arm/lpc24xx/include/system-clocks.h

    r92cbf96 r9647f7fe  
    2626#endif /* __cplusplus */
    2727
     28void lpc24xx_micro_seconds_delay( unsigned us);
     29
    2830unsigned lpc24xx_cclk( void);
    2931
  • c/src/lib/libbsp/arm/lpc24xx/misc/system-clocks.c

    r92cbf96 r9647f7fe  
    2929#define LPC24XX_OSCILLATOR_INTERNAL 4000000U
    3030
    31 #if !defined(LPC24XX_OSCILLATOR_MAIN)
    32 #error unknown main oscillator frequency
     31#ifndef LPC24XX_OSCILLATOR_MAIN
     32  #error "unknown main oscillator frequency"
    3333#endif
    3434
    35 #if !defined(LPC24XX_OSCILLATOR_RTC)
    36 #error unknown rtc oscillator frequency
     35#ifndef LPC24XX_OSCILLATOR_RTC
     36  #error "unknown RTC oscillator frequency"
    3737#endif
    3838
    3939/**
     40 * @brief Delay for @a us micro seconds.
     41 *
     42 * @note Uses Timer 1.
     43 */
     44void lpc24xx_micro_seconds_delay( unsigned us)
     45{
     46  /* Stop and reset timer */
     47  T1TCR = 0x02;
     48
     49  /* Set prescaler to zero */
     50  T1PR = 0x00;
     51 
     52  /* Set match value */
     53  T1MR0 = (uint32_t) ((uint64_t) 4000000 * (uint64_t) us / (uint64_t) lpc24xx_cclk()) + 1;
     54
     55  /* Reset all interrupt flags */
     56  T1IR = 0xff;
     57
     58  /* Stop timer on match */
     59  T1MCR = 0x04;
     60
     61  /* Start timer */
     62  T1TCR = 0x01;
     63 
     64  /* Wait until delay time has elapsed */
     65  while ((T1TCR & 0x01) != 0) {
     66    /* Wait */
     67  }
     68}
     69
     70/**
    4071 * @brief Returns the CPU clock frequency in [Hz].
     72 *
     73 * Return zero in case of an unexpected PLL input frequency.
    4174 */
    4275unsigned lpc24xx_cclk( void)
     
    5992      break;
    6093    default:
    61       while (1) {
    62         /* Spin forever */
    63       }
    6494      return 0;
    6595  }
     
    117147
    118148  /* Set CPU clock divider to a reasonable save value */
    119   CCLKCFG = SET_CCLKCFG_CCLKSEL( 0, 1);
     149  CCLKCFG = 0;
    120150
    121151  /* Disable PLL if necessary */
  • c/src/lib/libbsp/arm/lpc24xx/preinstall.am

    r92cbf96 r9647f7fe  
    4242PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp.h
    4343
     44$(PROJECT_INCLUDE)/coverhd.h: ../../shared/include/coverhd.h $(PROJECT_INCLUDE)/$(dirstamp)
     45        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/coverhd.h
     46PREINSTALL_FILES += $(PROJECT_INCLUDE)/coverhd.h
     47
    4448$(PROJECT_INCLUDE)/bspopts.h: include/bspopts.h $(PROJECT_INCLUDE)/$(dirstamp)
    4549        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bspopts.h
     
    5054PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/bootcard.h
    5155
    52 $(PROJECT_INCLUDE)/coverhd.h: ../../shared/include/coverhd.h $(PROJECT_INCLUDE)/$(dirstamp)
    53         $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/coverhd.h
    54 PREINSTALL_FILES += $(PROJECT_INCLUDE)/coverhd.h
    55 
    5656$(PROJECT_INCLUDE)/bsp/utility.h: ../../shared/include/utility.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
    5757        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/utility.h
     
    6161        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq-generic.h
    6262PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq-generic.h
     63
     64$(PROJECT_INCLUDE)/bsp/irq-info.h: ../../shared/include/irq-info.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
     65        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq-info.h
     66PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq-info.h
    6367
    6468$(PROJECT_INCLUDE)/bsp/tod.h: ../../shared/tod.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
     
    110114PREINSTALL_FILES += $(PROJECT_LIB)/linkcmds.base
    111115
    112 $(PROJECT_LIB)/linkcmds: startup/linkcmds $(PROJECT_LIB)/$(dirstamp)
    113         $(INSTALL_DATA) $< $(PROJECT_LIB)/linkcmds
    114 PREINSTALL_FILES += $(PROJECT_LIB)/linkcmds
     116$(PROJECT_LIB)/linkcmds.rom: ../shared/startup/linkcmds.rom $(PROJECT_LIB)/$(dirstamp)
     117        $(INSTALL_DATA) $< $(PROJECT_LIB)/linkcmds.rom
     118PREINSTALL_FILES += $(PROJECT_LIB)/linkcmds.rom
    115119
     120$(PROJECT_LIB)/linkcmds.lpc2478: startup/linkcmds.lpc2478 $(PROJECT_LIB)/$(dirstamp)
     121        $(INSTALL_DATA) $< $(PROJECT_LIB)/linkcmds.lpc2478
     122PREINSTALL_FILES += $(PROJECT_LIB)/linkcmds.lpc2478
     123
     124$(PROJECT_LIB)/linkcmds.lpc2478_ncs: startup/linkcmds.lpc2478_ncs $(PROJECT_LIB)/$(dirstamp)
     125        $(INSTALL_DATA) $< $(PROJECT_LIB)/linkcmds.lpc2478_ncs
     126PREINSTALL_FILES += $(PROJECT_LIB)/linkcmds.lpc2478_ncs
     127
     128$(PROJECT_LIB)/linkcmds.lpc2478_ncs_ram: startup/linkcmds.lpc2478_ncs_ram $(PROJECT_LIB)/$(dirstamp)
     129        $(INSTALL_DATA) $< $(PROJECT_LIB)/linkcmds.lpc2478_ncs_ram
     130PREINSTALL_FILES += $(PROJECT_LIB)/linkcmds.lpc2478_ncs_ram
     131
  • c/src/lib/libbsp/arm/lpc24xx/ssp/ssp.c

    r92cbf96 r9647f7fe  
    218218    case SSP0_BASE_ADDR:
    219219      rtems_interrupt_disable( level);
    220       SET_PCLKSEL1_PCLK_SSP0( PCLKSEL1, 1);
     220      PCLKSEL1 = SET_PCLKSEL1_PCLK_SSP0( PCLKSEL1, 1);
    221221      rtems_interrupt_enable( level);
    222222
     
    225225    case SSP1_BASE_ADDR:
    226226      rtems_interrupt_disable( level);
    227       SET_PCLKSEL0_PCLK_SSP1( PCLKSEL0, 1);
     227      PCLKSEL0 = SET_PCLKSEL0_PCLK_SSP1( PCLKSEL0, 1);
    228228      rtems_interrupt_enable( level);
    229229
     
    403403
    404404  /* Disable DMA on SSP */
    405   regs->dmacr = SSP_DMACR_RXDMAE | SSP_DMACR_TXDMAE;
     405  regs->dmacr = 0;
    406406
    407407  if (in == NULL) {
  • c/src/lib/libbsp/arm/lpc24xx/startup/bspstart.c

    r92cbf96 r9647f7fe  
    3030#include <bsp/system-clocks.h>
    3131
    32 void bsp_start_hook_0( void)
    33 {
    34   /* Re-map interrupt vectors to internal RAM */
    35   SET_MEMMAP_MAP( MEMMAP, 2);
    36 }
    37 
    38 void bsp_start_hook_1( void)
    39 {
    40   unsigned zero = 0;
     32static void lpc24xx_fatal_error( void)
     33{
     34  while (true) {
     35    /* Spin forever */
     36  }
     37}
     38
     39static void lpc24xx_ram_test_32( void)
     40{
     41  volatile unsigned *out = (volatile unsigned *) bsp_ram_ext_start;
     42
     43  while (out < (volatile unsigned *) bsp_ram_ext_end) {
     44    *out = (unsigned) out;
     45    ++out;
     46  }
     47
     48  out = (volatile unsigned *) bsp_ram_ext_start;
     49  while (out < (volatile unsigned *) bsp_ram_ext_end) {
     50    if (*out != (unsigned) out) {
     51      lpc24xx_fatal_error();
     52    }
     53    ++out;
     54  }
     55}
     56
     57/**
     58 * @brief EMC initialization.
     59 *
     60 * Dynamic Memory 0: Micron M T48LC 4M16 A2 P 75 IT
     61 */
     62static void lpc24xx_init_emc( void)
     63{
     64  #ifdef LPC24XX_EMC_MICRON
     65    int i = 0;
     66    uint32_t mode = 0;
     67
     68    /* Enable power */
     69    PCONP = SET_FLAGS( PCONP, 0x0800);
     70
     71    /* Set PIN selects */
     72    PINSEL5 = SET_FLAGS( PINSEL5, 0x05050555);
     73    PINSEL6 = SET_FLAGS( PINSEL6, 0x55555555);
     74    PINSEL8 = SET_FLAGS( PINSEL8, 0x55555555);
     75    PINSEL9 = SET_FLAGS( PINSEL9, 0x50555555);
     76
     77    /* Enable module, normal memory map and normal power mode */
     78    EMC_CTRL = 1;
     79
     80    /* Use little-endian mode and 1:1 clock ratio */
     81    EMC_CONFIG = 0;
     82
     83    /* Global dynamic settings */
     84
     85    /* FIXME */
     86    EMC_DYN_APR = 2;
     87
     88    /* Data-in to active command period tWR + tRP */
     89    EMC_DYN_DAL = 4;
     90
     91    /* Load mode register to active or refresh command period 2 tCK */
     92    EMC_DYN_MRD = 1;
     93
     94    /* Active to precharge command period 44 ns */
     95    EMC_DYN_RAS = 3;
     96
     97    /* Active to active command period 66 ns */
     98    EMC_DYN_RC = 4;
     99
     100    /* Use command delayed strategy */
     101    EMC_DYN_RD_CFG = 1;
     102
     103    /* Auto refresh period 66 ns */
     104    EMC_DYN_RFC = 4;
     105
     106    /* Precharge command period 20 ns */
     107    EMC_DYN_RP = 1;
     108
     109    /* Active bank a to active bank b command period 15 ns */
     110    EMC_DYN_RRD = 1;
     111
     112    /* FIXME */
     113    EMC_DYN_SREX = 5;
     114
     115    /* Write recovery time 15 ns */
     116    EMC_DYN_WR = 1;
     117
     118    /* Exit self refresh to active command period 75 ns */
     119    EMC_DYN_XSR = 5;
     120
     121    /* Dynamic Memory 0 settings */
     122
     123    /*
     124     * Use SDRAM, 0 0 001 01 address mapping, disabled buffer, unprotected writes
     125     */
     126    EMC_DYN_CFG0 = 0x0280;
     127
     128    /* CAS and RAS latency */
     129    EMC_DYN_RASCAS0 = 0x0202;
     130
     131    /* Wait 50 micro seconds */
     132    lpc24xx_micro_seconds_delay( 50);
     133
     134    /* Send command: NOP */
     135    EMC_DYN_CTRL = EMC_DYN_CTRL_CE | EMC_DYN_CTRL_CS | EMC_DYN_CTRL_CMD_NOP;
     136
     137    /* Wait 50 micro seconds */
     138    lpc24xx_micro_seconds_delay( 50);
     139
     140    /* Send command: PRECHARGE ALL */
     141    EMC_DYN_CTRL = EMC_DYN_CTRL_CE | EMC_DYN_CTRL_CS | EMC_DYN_CTRL_CMD_PALL;
     142
     143    /* Shortest possible refresh period */
     144    EMC_DYN_RFSH = 0x01;
     145
     146    /* Wait at least 128 ABH clock cycles */
     147    for (i = 0; i < 128; ++i) {
     148      asm volatile (" nop");
     149    }
     150
     151    /* Wait 1 micro second */
     152    lpc24xx_micro_seconds_delay( 1);
     153
     154    /* Set refresh period */
     155    EMC_DYN_RFSH = 0x46;
     156
     157    /* Send command: MODE */
     158    EMC_DYN_CTRL = EMC_DYN_CTRL_CE | EMC_DYN_CTRL_CS | EMC_DYN_CTRL_CMD_MODE;
     159
     160    /* Set mode registerin SDRAM */
     161    mode = *((volatile uint32_t *) (0xa0000000 | (0x23 << (1 + 2 + 8))));
     162
     163    /* Send command: NORMAL */
     164    EMC_DYN_CTRL = 0;
     165
     166    /* Enable buffer */
     167    EMC_DYN_CFG0 |= 0x00080000;
     168
     169    /* Static Memory 0 settings */
     170    EMC_STA_WAITWEN0 = 0x02;
     171    EMC_STA_WAITOEN0 = 0x02;
     172    EMC_STA_WAITRD0 = 0x1f;
     173    EMC_STA_WAITPAGE0 = 0x1f;
     174    EMC_STA_WAITWR0 = 0x1f;
     175    EMC_STA_WAITTURN0 = 0x0f;
     176    EMC_STA_CFG0 = 0x81;
     177
     178    /* Static Memory 1 settings */
     179    EMC_STA_WAITWEN1 = 0x02;
     180    EMC_STA_WAITOEN1 = 0x02;
     181    EMC_STA_WAITRD1 = 0x08;
     182    EMC_STA_WAITPAGE1 = 0x1f;
     183    EMC_STA_WAITWR1 = 0x08;
     184    EMC_STA_WAITTURN1 = 0x0f;
     185    EMC_STA_CFG1 = 0x80;
     186
     187    /* RAM test */
     188    lpc24xx_ram_test_32();
     189  #endif /* LPC24XX_EMC_MICRON */
     190}
     191
     192static void lpc24xx_init_pll( void)
     193{
     194  #ifndef LPC24XX_HAS_UBOOT
     195    /* Enable main oscillator */
     196    SCS = SET_FLAGS( SCS, 0x20);
     197    while (IS_FLAG_CLEARED( SCS, 0x40)) {
     198      /* Wait */
     199    }
     200
     201    /* Set PLL */
     202    lpc24xx_set_pll( 1, 0, 11, 3);
     203  #endif /* LPC24XX_HAS_UBOOT */
     204}
     205
     206void /* __attribute__ ((section (".entry"))) */ bsp_start_hook_0( void)
     207{
     208  /* Initialize PLL */
     209  lpc24xx_init_pll();
     210
     211  #ifndef LPC24XX_HAS_UBOOT
     212    /* Set pin functions  */
     213    PINSEL0 = 0;
     214    PINSEL1 = 0;
     215    PINSEL2 = 0;
     216    PINSEL3 = 0;
     217    PINSEL4 = 0;
     218    PINSEL5 = 0;
     219    PINSEL6 = 0;
     220    PINSEL7 = 0;
     221    PINSEL8 = 0;
     222    PINSEL9 = 0;
     223    PINSEL10 = 0;
     224
     225    /* Set periperal clocks */
     226    PCLKSEL0 = 0;
     227    PCLKSEL1 = 0;
     228
     229    /* Disable power for all modules */
     230    PCONP = 0;
     231
     232    /* Set memory accelerator module (MAM) */
     233    MAMCR = 0;
     234    MAMTIM = 4;
     235
     236    /* Set general purpose IO */
     237    IODIR0 = 0;
     238    IODIR1 = 0;
     239    IOSET0 = 0xffffffff;
     240    IOSET1 = 0xffffffff;
     241
     242    /* Set fast IO */
     243    FIO0DIR = 0;
     244    FIO1DIR = 0;
     245    FIO2DIR = 0;
     246    FIO3DIR = 0;
     247    FIO4DIR = 0;
     248    FIO0SET = 0xffffffff;
     249    FIO1SET = 0xffffffff;
     250    FIO2SET = 0xffffffff;
     251    FIO3SET = 0xffffffff;
     252    FIO4SET = 0xffffffff;
     253
     254    /* Initialize UART 0 */
     255    PCONP = SET_FLAGS( PCONP, 0x08);
     256    PCLKSEL0 = SET_FLAGS( PCLKSEL0, 0x40);
     257    PINSEL0 = SET_FLAGS( PINSEL0, 0x50);
     258    U0LCR = 0;
     259    U0IER = 0;
     260    U0LCR = 0x80;
     261    U0DLL = lpc24xx_cclk() / 16 / LPC24XX_UART_BAUD;
     262    U0DLM = 0;
     263    U0LCR = 0x03;
     264    U0FCR = 0x07;
     265
     266    /* Initialize Timer 1 */
     267    PCONP = SET_FLAGS( PCONP, 0x04);
     268    PCLKSEL0 = SET_FLAGS( PCLKSEL0, 0x10);
     269  #endif /* LPC24XX_HAS_UBOOT */
     270}
     271
     272static void lpc24xx_copy_data( void)
     273{
     274  #ifndef LPC24XX_HAS_UBOOT
     275    unsigned *in = bsp_section_text_end;
     276    unsigned *out = bsp_section_data_start;
     277
     278    /* Copy data */
     279    while (out < bsp_section_data_end) {
     280      *out = *in;
     281      ++out;
     282      ++in;
     283    }
     284  #endif /* LPC24XX_HAS_UBOOT */
     285}
     286
     287static void lpc24xx_clear_bss( void)
     288{
    41289  unsigned *out = bsp_section_bss_start;
    42290
    43291  /* Clear BSS */
    44292  while (out < bsp_section_bss_end) {
    45     *out = zero;
     293    *out = 0;
    46294    ++out;
    47295  }
    48296}
    49297
     298void /* __attribute__ ((section (".entry"))) */ bsp_start_hook_1( void)
     299{
     300  /* Re-map interrupt vectors to internal RAM */
     301  MEMMAP = SET_MEMMAP_MAP( MEMMAP, 2);
     302
     303  /* Initialize External Memory Controller (EMC) */
     304  lpc24xx_init_emc();
     305
     306  /* Copy data */
     307  lpc24xx_copy_data();
     308
     309  /* Clear BSS */
     310  lpc24xx_clear_bss();
     311}
     312
    50313void bsp_start( void)
    51314{
    52   printk( "CPU Clock: %u\n", lpc24xx_cclk());
     315  printk( "CPU clock (CCLK): %u\n", lpc24xx_cclk());
    53316
    54317  /* Exceptions */
     
    58321  if (bsp_interrupt_initialize() != RTEMS_SUCCESSFUL) {
    59322    /* FIXME */
    60     printk( "Cannot intitialize interrupt support\n");
    61     while (1) {
    62       /* Spin forever */
    63     }
     323    printk( "cannot intitialize interrupt support\n");
     324    lpc24xx_fatal_error();
    64325  }
    65326
  • c/src/lib/libbsp/arm/shared/include/start.h

    r92cbf96 r9647f7fe  
    2121
    2222#ifndef ASM
     23
     24  /**
     25   * @brief System start entry.
     26   */
     27  void start( void);
    2328
    2429  /**
  • c/src/lib/libbsp/arm/shared/start/start.S

    r92cbf96 r9647f7fe  
    2828
    2929.globl start
    30 
    31 .globl Reset_Handler
    32 .globl Undefined_Handler
    3330.globl SWI_Handler
    34 .globl Prefetch_Handler
    35 .globl Abort_Handler
    36 .globl IRQ_Handler
    37 .globl FIQ_Handler
    3831
    3932/* Program Status Register definitions */
     
    5043.equ PSR_T,          0x20
    5144
     45.section ".entry"
     46
     47/*
     48 * This is the exception vector table and the pointers to the default
     49 * exceptions handlers.
     50 */
     51
     52vector_block:
     53
     54        ldr     pc, handler_addr_reset
     55        ldr     pc, handler_addr_undef
     56        ldr     pc, handler_addr_swi
     57        ldr     pc, handler_addr_prefetch
     58        ldr     pc, handler_addr_abort
     59
     60        /* Program signature checked by boot loader */
     61        .word   0xb8a06f58
     62
     63        ldr     pc, handler_addr_irq
     64        ldr     pc, handler_addr_fiq
     65
     66handler_addr_reset:
     67
     68        .word   start
     69
     70handler_addr_undef:
     71
     72        .word   twiddle
     73
     74handler_addr_swi:
     75
     76        .word   twiddle
     77
     78handler_addr_prefetch:
     79
     80        .word   twiddle
     81
     82handler_addr_abort:
     83
     84        .word   twiddle
     85
     86handler_addr_reserved:
     87
     88        .word   twiddle
     89
     90handler_addr_irq:
     91
     92        .word   twiddle
     93
     94handler_addr_fiq:
     95
     96        .word   twiddle
     97
    5298/* Start entry */
    5399
    54 .section ".entry"
    55100start:
    56101
     
    113158         */
    114159
    115         mov     r0, #0
     160        ldr     r0, =bsp_section_vector_start
    116161        adr     r1, vector_block
    117162        ldmia   r1!, {r2-r9}
     
    132177        /* Spin forever */
    133178
     179SWI_Handler:
     180
    134181twiddle:
    135182
    136183        b       twiddle
    137 
    138 /*
    139  * This is the exception vector table and the pointers to the default
    140  * exceptions handlers.
    141  */
    142 
    143 vector_block:
    144 
    145         ldr     pc, Reset_Handler
    146         ldr     pc, Undefined_Handler
    147         ldr     pc, SWI_Handler
    148         ldr     pc, Prefetch_Handler
    149         ldr     pc, Abort_Handler
    150         nop
    151         ldr     pc, IRQ_Handler
    152         ldr     pc, FIQ_Handler
    153 
    154 Reset_Handler:
    155 
    156         b       bsp_reset
    157 
    158 Undefined_Handler:
    159 
    160         b       Undefined_Handler
    161 
    162 SWI_Handler:
    163 
    164         b       SWI_Handler
    165 
    166 Prefetch_Handler:
    167 
    168         b       Prefetch_Handler
    169 
    170 Abort_Handler:
    171 
    172         b       Abort_Handler
    173 
    174         nop
    175 
    176 IRQ_Handler:
    177 
    178         b       IRQ_Handler
    179 
    180 FIQ_Handler:
    181 
    182         b       FIQ_Handler
  • c/src/lib/libbsp/shared/ChangeLog

    r92cbf96 r9647f7fe  
     12009-02-27      Sebastian Huber <sebastian.huber@embedded-brains.de>
     2
     3        * include/utility.h: Added define.
     4        * include/irq-generic.h: Added missing prototypes.
     5
    162009-02-11      Joel Sherrill <joel.sherrill@oarcorp.com>
    27
  • c/src/lib/libbsp/shared/include/irq-generic.h

    r92cbf96 r9647f7fe  
    147147void bsp_interrupt_handler_default( rtems_vector_number vector);
    148148
    149 rtems_status_code bsp_interrupt_initialize();
     149rtems_status_code bsp_interrupt_initialize( void);
    150150
    151151/**
     
    164164 * @return On success RTEMS_SUCCESSFUL shall be returned.
    165165 */
    166 rtems_status_code bsp_interrupt_facility_initialize();
     166rtems_status_code bsp_interrupt_facility_initialize( void);
    167167
    168168/**
  • c/src/lib/libbsp/shared/include/utility.h

    r92cbf96 r9647f7fe  
    4242  (((val) & (flags)) == (flags))
    4343
     44#define IS_ANY_FLAG_SET( val, flags) \
     45  (((val) & (flags)) != 0)
     46
    4447#define ARE_FLAGS_CLEARED( val, flags) \
    4548  (((val) & (flags)) == 0)
  • make/custom/lpc2478.cfg

    r92cbf96 r9647f7fe  
    55#
    66
    7 include $(RTEMS_ROOT)/make/custom/default.cfg
     7LPC24XX_LINKCMDS = linkcmds.lpc2478
    88
    9 RTEMS_CPU = arm
    10 RTEMS_BSP_FAMILY = lpc24xx
     9include $(RTEMS_ROOT)/make/custom/lpc24xx.cfg
    1110
    12 CPU_CFLAGS = -mcpu=arm7tdmi -mstructure-size-boundary=8 -mapcs-frame
    13 
    14 CFLAGS_OPTIMIZE_V = -Os -g
    15 
    16 define bsp-post-link
    17         $(OBJCOPY) -O binary '$@' '$(basename $@).bin'
    18         gzip -f -9 '$(basename $@).bin'
    19         # mkimage -A arm -O rtems -T kernel -C gzip \
    20         #     -a a0000000 -e a0000000 -name '$(notdir $@)' \
    21         #     -d '$(basename $@).bin.gz' '$(basename $@).img'
    22         $(default-bsp-post-link)
    23 endef
     11# define bsp-post-link
     12#       $(OBJCOPY) -O binary '$@' '$(basename $@).bin'
     13#       gzip -f -9 '$(basename $@).bin'
     14#       mkimage -A arm -O rtems -T kernel -C gzip -a a0000000 -e a0000040 -name '$(notdir $@)' -d '$(basename $@).bin.gz' '$(basename $@).img'
     15#       $(default-bsp-post-link)
     16# endef
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