Changeset 957c075 in rtems


Ignore:
Timestamp:
Nov 19, 2014, 10:51:33 AM (5 years ago)
Author:
Sebastian Huber <sebastian.huber@…>
Branches:
4.11, master
Children:
a9d6c20
Parents:
6b4a22e3
git-author:
Sebastian Huber <sebastian.huber@…> (11/19/14 10:51:33)
git-committer:
Sebastian Huber <sebastian.huber@…> (11/20/14 09:30:26)
Message:

bsps/arm: L2C 310 rename BSP_ARM_L2CC_BASE

Rename BSP_ARM_L2CC_BASE to BSP_ARM_L2C_310_BASE.

Location:
c/src/lib/libbsp/arm
Files:
3 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/arm/altera-cyclone-v/include/bsp.h

    r6b4a22e3 r957c075  
    4040#define BSP_ARM_GIC_DIST_BASE ( BSP_ARM_A9MPCORE_SCU_BASE + 0x00001000 )
    4141
    42 #define BSP_ARM_L2CC_BASE 0xFFFEF000U
     42#define BSP_ARM_L2C_310_BASE 0xFFFEF000U
    4343
    4444/* Forward declaration */
  • c/src/lib/libbsp/arm/shared/arm-l2c-310/cache_.h

    r6b4a22e3 r957c075  
    483483{
    484484  volatile L2CC                  *l2cc          =
    485     (volatile L2CC *) BSP_ARM_L2CC_BASE;
     485    (volatile L2CC *) BSP_ARM_L2C_310_BASE;
    486486  const cache_l2c_310_rtl_release RTL_RELEASE   =
    487487    l2cc->cache_id & CACHE_L2C_310_L2CC_ID_RTL_MASK;
     
    519519{
    520520  volatile L2CC                  *l2cc          =
    521     (volatile L2CC *) BSP_ARM_L2CC_BASE;
     521    (volatile L2CC *) BSP_ARM_L2C_310_BASE;
    522522  const cache_l2c_310_rtl_release RTL_RELEASE   =
    523523    l2cc->cache_id & CACHE_L2C_310_L2CC_ID_RTL_MASK;
     
    555555{
    556556  volatile L2CC                  *l2cc          =
    557     (volatile L2CC *) BSP_ARM_L2CC_BASE;
     557    (volatile L2CC *) BSP_ARM_L2C_310_BASE;
    558558  const cache_l2c_310_rtl_release RTL_RELEASE   =
    559559    l2cc->cache_id & CACHE_L2C_310_L2CC_ID_RTL_MASK;
     
    591591{
    592592  volatile L2CC                  *l2cc          =
    593     (volatile L2CC *) BSP_ARM_L2CC_BASE;
     593    (volatile L2CC *) BSP_ARM_L2C_310_BASE;
    594594  const cache_l2c_310_rtl_release RTL_RELEASE   =
    595595    l2cc->cache_id & CACHE_L2C_310_L2CC_ID_RTL_MASK;
     
    627627{
    628628  volatile L2CC                  *l2cc          =
    629     (volatile L2CC *) BSP_ARM_L2CC_BASE;
     629    (volatile L2CC *) BSP_ARM_L2C_310_BASE;
    630630  const cache_l2c_310_rtl_release RTL_RELEASE   =
    631631    l2cc->cache_id & CACHE_L2C_310_L2CC_ID_RTL_MASK;
     
    663663{
    664664  volatile L2CC                  *l2cc          =
    665     (volatile L2CC *) BSP_ARM_L2CC_BASE;
     665    (volatile L2CC *) BSP_ARM_L2C_310_BASE;
    666666  const cache_l2c_310_rtl_release RTL_RELEASE   =
    667667    l2cc->cache_id & CACHE_L2C_310_L2CC_ID_RTL_MASK;
     
    699699{
    700700  volatile L2CC                  *l2cc          =
    701     (volatile L2CC *) BSP_ARM_L2CC_BASE;
     701    (volatile L2CC *) BSP_ARM_L2C_310_BASE;
    702702  const cache_l2c_310_rtl_release RTL_RELEASE   =
    703703    l2cc->cache_id & CACHE_L2C_310_L2CC_ID_RTL_MASK;
     
    735735{
    736736  volatile L2CC                  *l2cc          =
    737     (volatile L2CC *) BSP_ARM_L2CC_BASE;
     737    (volatile L2CC *) BSP_ARM_L2C_310_BASE;
    738738  const cache_l2c_310_rtl_release RTL_RELEASE   =
    739739    l2cc->cache_id & CACHE_L2C_310_L2CC_ID_RTL_MASK;
     
    771771{
    772772  volatile L2CC                  *l2cc          =
    773     (volatile L2CC *) BSP_ARM_L2CC_BASE;
     773    (volatile L2CC *) BSP_ARM_L2C_310_BASE;
    774774  const cache_l2c_310_rtl_release RTL_RELEASE   =
    775775    l2cc->cache_id & CACHE_L2C_310_L2CC_ID_RTL_MASK;
     
    805805{
    806806  volatile L2CC                  *l2cc          =
    807     (volatile L2CC *) BSP_ARM_L2CC_BASE;
     807    (volatile L2CC *) BSP_ARM_L2C_310_BASE;
    808808  const cache_l2c_310_rtl_release RTL_RELEASE   =
    809809    l2cc->cache_id & CACHE_L2C_310_L2CC_ID_RTL_MASK;
     
    841841{
    842842  volatile L2CC                  *l2cc          =
    843     (volatile L2CC *) BSP_ARM_L2CC_BASE;
     843    (volatile L2CC *) BSP_ARM_L2C_310_BASE;
    844844  const cache_l2c_310_rtl_release RTL_RELEASE   =
    845845    l2cc->cache_id & CACHE_L2C_310_L2CC_ID_RTL_MASK;
     
    878878{
    879879  volatile L2CC                  *l2cc          =
    880     (volatile L2CC *) BSP_ARM_L2CC_BASE;
     880    (volatile L2CC *) BSP_ARM_L2C_310_BASE;
    881881  const cache_l2c_310_rtl_release RTL_RELEASE   =
    882882    l2cc->cache_id & CACHE_L2C_310_L2CC_ID_RTL_MASK;
     
    943943  if( l2c_310_cache_errata_is_applicable_729815() )
    944944  {
    945     volatile L2CC *l2cc = (volatile L2CC *) BSP_ARM_L2CC_BASE;
     945    volatile L2CC *l2cc = (volatile L2CC *) BSP_ARM_L2C_310_BASE;
    946946
    947947    assert( 0 == ( l2cc->aux_ctrl & CACHE_L2C_310_L2CC_AUX_HPSODRE_MASK ) );
     
    979979  if( l2c_310_cache_errata_is_applicable_765569() )
    980980  {
    981     volatile L2CC *l2cc = (volatile L2CC *) BSP_ARM_L2CC_BASE;
     981    volatile L2CC *l2cc = (volatile L2CC *) BSP_ARM_L2C_310_BASE;
    982982
    983983    assert( !( ( l2cc->aux_ctrl & CACHE_L2C_310_L2CC_AUX_IPFE_MASK
     
    10071007cache_l2c_310_sync( void )
    10081008{
    1009   volatile L2CC *l2cc = (volatile L2CC *) BSP_ARM_L2CC_BASE;
     1009  volatile L2CC *l2cc = (volatile L2CC *) BSP_ARM_L2C_310_BASE;
    10101010
    10111011  if( l2c_310_cache_errata_is_applicable_753970() ) {
     
    10221022)
    10231023{
    1024   volatile L2CC *l2cc = (volatile L2CC *) BSP_ARM_L2CC_BASE;
     1024  volatile L2CC *l2cc = (volatile L2CC *) BSP_ARM_L2C_310_BASE;
    10251025
    10261026  if( is_errata_588369applicable ) {
     
    10741074cache_l2c_310_flush_entire( void )
    10751075{
    1076   volatile L2CC               *l2cc = (volatile L2CC *) BSP_ARM_L2CC_BASE;
     1076  volatile L2CC               *l2cc = (volatile L2CC *) BSP_ARM_L2C_310_BASE;
    10771077  rtems_interrupt_lock_context lock_context;
    10781078
     
    10981098cache_l2c_310_invalidate_1_line( const void *d_addr )
    10991099{
    1100   volatile L2CC *l2cc = (volatile L2CC *) BSP_ARM_L2CC_BASE;
     1100  volatile L2CC *l2cc = (volatile L2CC *) BSP_ARM_L2C_310_BASE;
    11011101
    11021102
     
    11081108cache_l2c_310_invalidate_range( uint32_t adx, const uint32_t ADDR_LAST )
    11091109{
    1110   volatile L2CC               *l2cc = (volatile L2CC *) BSP_ARM_L2CC_BASE;
     1110  volatile L2CC               *l2cc = (volatile L2CC *) BSP_ARM_L2C_310_BASE;
    11111111  rtems_interrupt_lock_context lock_context;
    11121112
     
    11251125cache_l2c_310_invalidate_entire( void )
    11261126{
    1127   volatile L2CC *l2cc = (volatile L2CC *) BSP_ARM_L2CC_BASE;
     1127  volatile L2CC *l2cc = (volatile L2CC *) BSP_ARM_L2C_310_BASE;
    11281128
    11291129  /* Invalidate the caches */
     
    11431143cache_l2c_310_clean_and_invalidate_entire( void )
    11441144{
    1145   volatile L2CC               *l2cc = (volatile L2CC *) BSP_ARM_L2CC_BASE;
     1145  volatile L2CC               *l2cc = (volatile L2CC *) BSP_ARM_L2C_310_BASE;
    11461146  rtems_interrupt_lock_context lock_context;
    11471147
     
    11821182{
    11831183  size_t         size       = 0;
    1184   volatile L2CC *l2cc       = (volatile L2CC *) BSP_ARM_L2CC_BASE;
     1184  volatile L2CC *l2cc       = (volatile L2CC *) BSP_ARM_L2C_310_BASE;
    11851185  uint32_t       cache_type = l2cc->cache_type;
    11861186  uint32_t       way_size;
     
    12201220static void cache_l2c_310_unlock( void )
    12211221{
    1222   volatile L2CC *l2cc = (volatile L2CC *) BSP_ARM_L2CC_BASE;
     1222  volatile L2CC *l2cc = (volatile L2CC *) BSP_ARM_L2C_310_BASE;
    12231223
    12241224
     
    12441244cache_l2c_310_enable( void )
    12451245{
    1246   volatile L2CC *l2cc = (volatile L2CC *) BSP_ARM_L2CC_BASE;
     1246  volatile L2CC *l2cc = (volatile L2CC *) BSP_ARM_L2C_310_BASE;
    12471247 
    12481248  /* Only enable if L2CC is currently disabled */
     
    12531253
    12541254    /* Do we actually have an L2C-310 cache controller?
    1255     * Has BSP_ARM_L2CC_BASE been configured correctly? */
     1255    * Has BSP_ARM_L2C_310_BASE been configured correctly? */
    12561256    switch ( cache_id ) {
    12571257      case CACHE_L2C_310_L2CC_ID_PART_L310:
     
    13361336cache_l2c_310_disable( void )
    13371337{
    1338   volatile L2CC               *l2cc = (volatile L2CC *) BSP_ARM_L2CC_BASE;
     1338  volatile L2CC               *l2cc = (volatile L2CC *) BSP_ARM_L2C_310_BASE;
    13391339  rtems_interrupt_lock_context lock_context;
    13401340
  • c/src/lib/libbsp/arm/xilinx-zynq/include/bsp.h

    r6b4a22e3 r957c075  
    5656#define BSP_ARM_GIC_DIST_BASE 0xf8f01000
    5757
    58 #define BSP_ARM_L2CC_BASE 0xF8F02000U
     58#define BSP_ARM_L2C_310_BASE 0xF8F02000U
    5959
    6060/**
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