Changeset 957c075 in rtems
- Timestamp:
- 11/19/14 10:51:33 (9 years ago)
- Branches:
- 4.11, 5, master
- Children:
- a9d6c20
- Parents:
- 6b4a22e3
- git-author:
- Sebastian Huber <sebastian.huber@…> (11/19/14 10:51:33)
- git-committer:
- Sebastian Huber <sebastian.huber@…> (11/20/14 09:30:26)
- Location:
- c/src/lib/libbsp/arm
- Files:
-
- 3 edited
Legend:
- Unmodified
- Added
- Removed
-
c/src/lib/libbsp/arm/altera-cyclone-v/include/bsp.h
r6b4a22e3 r957c075 40 40 #define BSP_ARM_GIC_DIST_BASE ( BSP_ARM_A9MPCORE_SCU_BASE + 0x00001000 ) 41 41 42 #define BSP_ARM_L2C C_BASE 0xFFFEF000U42 #define BSP_ARM_L2C_310_BASE 0xFFFEF000U 43 43 44 44 /* Forward declaration */ -
c/src/lib/libbsp/arm/shared/arm-l2c-310/cache_.h
r6b4a22e3 r957c075 483 483 { 484 484 volatile L2CC *l2cc = 485 (volatile L2CC *) BSP_ARM_L2C C_BASE;485 (volatile L2CC *) BSP_ARM_L2C_310_BASE; 486 486 const cache_l2c_310_rtl_release RTL_RELEASE = 487 487 l2cc->cache_id & CACHE_L2C_310_L2CC_ID_RTL_MASK; … … 519 519 { 520 520 volatile L2CC *l2cc = 521 (volatile L2CC *) BSP_ARM_L2C C_BASE;521 (volatile L2CC *) BSP_ARM_L2C_310_BASE; 522 522 const cache_l2c_310_rtl_release RTL_RELEASE = 523 523 l2cc->cache_id & CACHE_L2C_310_L2CC_ID_RTL_MASK; … … 555 555 { 556 556 volatile L2CC *l2cc = 557 (volatile L2CC *) BSP_ARM_L2C C_BASE;557 (volatile L2CC *) BSP_ARM_L2C_310_BASE; 558 558 const cache_l2c_310_rtl_release RTL_RELEASE = 559 559 l2cc->cache_id & CACHE_L2C_310_L2CC_ID_RTL_MASK; … … 591 591 { 592 592 volatile L2CC *l2cc = 593 (volatile L2CC *) BSP_ARM_L2C C_BASE;593 (volatile L2CC *) BSP_ARM_L2C_310_BASE; 594 594 const cache_l2c_310_rtl_release RTL_RELEASE = 595 595 l2cc->cache_id & CACHE_L2C_310_L2CC_ID_RTL_MASK; … … 627 627 { 628 628 volatile L2CC *l2cc = 629 (volatile L2CC *) BSP_ARM_L2C C_BASE;629 (volatile L2CC *) BSP_ARM_L2C_310_BASE; 630 630 const cache_l2c_310_rtl_release RTL_RELEASE = 631 631 l2cc->cache_id & CACHE_L2C_310_L2CC_ID_RTL_MASK; … … 663 663 { 664 664 volatile L2CC *l2cc = 665 (volatile L2CC *) BSP_ARM_L2C C_BASE;665 (volatile L2CC *) BSP_ARM_L2C_310_BASE; 666 666 const cache_l2c_310_rtl_release RTL_RELEASE = 667 667 l2cc->cache_id & CACHE_L2C_310_L2CC_ID_RTL_MASK; … … 699 699 { 700 700 volatile L2CC *l2cc = 701 (volatile L2CC *) BSP_ARM_L2C C_BASE;701 (volatile L2CC *) BSP_ARM_L2C_310_BASE; 702 702 const cache_l2c_310_rtl_release RTL_RELEASE = 703 703 l2cc->cache_id & CACHE_L2C_310_L2CC_ID_RTL_MASK; … … 735 735 { 736 736 volatile L2CC *l2cc = 737 (volatile L2CC *) BSP_ARM_L2C C_BASE;737 (volatile L2CC *) BSP_ARM_L2C_310_BASE; 738 738 const cache_l2c_310_rtl_release RTL_RELEASE = 739 739 l2cc->cache_id & CACHE_L2C_310_L2CC_ID_RTL_MASK; … … 771 771 { 772 772 volatile L2CC *l2cc = 773 (volatile L2CC *) BSP_ARM_L2C C_BASE;773 (volatile L2CC *) BSP_ARM_L2C_310_BASE; 774 774 const cache_l2c_310_rtl_release RTL_RELEASE = 775 775 l2cc->cache_id & CACHE_L2C_310_L2CC_ID_RTL_MASK; … … 805 805 { 806 806 volatile L2CC *l2cc = 807 (volatile L2CC *) BSP_ARM_L2C C_BASE;807 (volatile L2CC *) BSP_ARM_L2C_310_BASE; 808 808 const cache_l2c_310_rtl_release RTL_RELEASE = 809 809 l2cc->cache_id & CACHE_L2C_310_L2CC_ID_RTL_MASK; … … 841 841 { 842 842 volatile L2CC *l2cc = 843 (volatile L2CC *) BSP_ARM_L2C C_BASE;843 (volatile L2CC *) BSP_ARM_L2C_310_BASE; 844 844 const cache_l2c_310_rtl_release RTL_RELEASE = 845 845 l2cc->cache_id & CACHE_L2C_310_L2CC_ID_RTL_MASK; … … 878 878 { 879 879 volatile L2CC *l2cc = 880 (volatile L2CC *) BSP_ARM_L2C C_BASE;880 (volatile L2CC *) BSP_ARM_L2C_310_BASE; 881 881 const cache_l2c_310_rtl_release RTL_RELEASE = 882 882 l2cc->cache_id & CACHE_L2C_310_L2CC_ID_RTL_MASK; … … 943 943 if( l2c_310_cache_errata_is_applicable_729815() ) 944 944 { 945 volatile L2CC *l2cc = (volatile L2CC *) BSP_ARM_L2C C_BASE;945 volatile L2CC *l2cc = (volatile L2CC *) BSP_ARM_L2C_310_BASE; 946 946 947 947 assert( 0 == ( l2cc->aux_ctrl & CACHE_L2C_310_L2CC_AUX_HPSODRE_MASK ) ); … … 979 979 if( l2c_310_cache_errata_is_applicable_765569() ) 980 980 { 981 volatile L2CC *l2cc = (volatile L2CC *) BSP_ARM_L2C C_BASE;981 volatile L2CC *l2cc = (volatile L2CC *) BSP_ARM_L2C_310_BASE; 982 982 983 983 assert( !( ( l2cc->aux_ctrl & CACHE_L2C_310_L2CC_AUX_IPFE_MASK … … 1007 1007 cache_l2c_310_sync( void ) 1008 1008 { 1009 volatile L2CC *l2cc = (volatile L2CC *) BSP_ARM_L2C C_BASE;1009 volatile L2CC *l2cc = (volatile L2CC *) BSP_ARM_L2C_310_BASE; 1010 1010 1011 1011 if( l2c_310_cache_errata_is_applicable_753970() ) { … … 1022 1022 ) 1023 1023 { 1024 volatile L2CC *l2cc = (volatile L2CC *) BSP_ARM_L2C C_BASE;1024 volatile L2CC *l2cc = (volatile L2CC *) BSP_ARM_L2C_310_BASE; 1025 1025 1026 1026 if( is_errata_588369applicable ) { … … 1074 1074 cache_l2c_310_flush_entire( void ) 1075 1075 { 1076 volatile L2CC *l2cc = (volatile L2CC *) BSP_ARM_L2C C_BASE;1076 volatile L2CC *l2cc = (volatile L2CC *) BSP_ARM_L2C_310_BASE; 1077 1077 rtems_interrupt_lock_context lock_context; 1078 1078 … … 1098 1098 cache_l2c_310_invalidate_1_line( const void *d_addr ) 1099 1099 { 1100 volatile L2CC *l2cc = (volatile L2CC *) BSP_ARM_L2C C_BASE;1100 volatile L2CC *l2cc = (volatile L2CC *) BSP_ARM_L2C_310_BASE; 1101 1101 1102 1102 … … 1108 1108 cache_l2c_310_invalidate_range( uint32_t adx, const uint32_t ADDR_LAST ) 1109 1109 { 1110 volatile L2CC *l2cc = (volatile L2CC *) BSP_ARM_L2C C_BASE;1110 volatile L2CC *l2cc = (volatile L2CC *) BSP_ARM_L2C_310_BASE; 1111 1111 rtems_interrupt_lock_context lock_context; 1112 1112 … … 1125 1125 cache_l2c_310_invalidate_entire( void ) 1126 1126 { 1127 volatile L2CC *l2cc = (volatile L2CC *) BSP_ARM_L2C C_BASE;1127 volatile L2CC *l2cc = (volatile L2CC *) BSP_ARM_L2C_310_BASE; 1128 1128 1129 1129 /* Invalidate the caches */ … … 1143 1143 cache_l2c_310_clean_and_invalidate_entire( void ) 1144 1144 { 1145 volatile L2CC *l2cc = (volatile L2CC *) BSP_ARM_L2C C_BASE;1145 volatile L2CC *l2cc = (volatile L2CC *) BSP_ARM_L2C_310_BASE; 1146 1146 rtems_interrupt_lock_context lock_context; 1147 1147 … … 1182 1182 { 1183 1183 size_t size = 0; 1184 volatile L2CC *l2cc = (volatile L2CC *) BSP_ARM_L2C C_BASE;1184 volatile L2CC *l2cc = (volatile L2CC *) BSP_ARM_L2C_310_BASE; 1185 1185 uint32_t cache_type = l2cc->cache_type; 1186 1186 uint32_t way_size; … … 1220 1220 static void cache_l2c_310_unlock( void ) 1221 1221 { 1222 volatile L2CC *l2cc = (volatile L2CC *) BSP_ARM_L2C C_BASE;1222 volatile L2CC *l2cc = (volatile L2CC *) BSP_ARM_L2C_310_BASE; 1223 1223 1224 1224 … … 1244 1244 cache_l2c_310_enable( void ) 1245 1245 { 1246 volatile L2CC *l2cc = (volatile L2CC *) BSP_ARM_L2C C_BASE;1246 volatile L2CC *l2cc = (volatile L2CC *) BSP_ARM_L2C_310_BASE; 1247 1247 1248 1248 /* Only enable if L2CC is currently disabled */ … … 1253 1253 1254 1254 /* Do we actually have an L2C-310 cache controller? 1255 * Has BSP_ARM_L2C C_BASE been configured correctly? */1255 * Has BSP_ARM_L2C_310_BASE been configured correctly? */ 1256 1256 switch ( cache_id ) { 1257 1257 case CACHE_L2C_310_L2CC_ID_PART_L310: … … 1336 1336 cache_l2c_310_disable( void ) 1337 1337 { 1338 volatile L2CC *l2cc = (volatile L2CC *) BSP_ARM_L2C C_BASE;1338 volatile L2CC *l2cc = (volatile L2CC *) BSP_ARM_L2C_310_BASE; 1339 1339 rtems_interrupt_lock_context lock_context; 1340 1340 -
c/src/lib/libbsp/arm/xilinx-zynq/include/bsp.h
r6b4a22e3 r957c075 56 56 #define BSP_ARM_GIC_DIST_BASE 0xf8f01000 57 57 58 #define BSP_ARM_L2C C_BASE 0xF8F02000U58 #define BSP_ARM_L2C_310_BASE 0xF8F02000U 59 59 60 60 /**
Note: See TracChangeset
for help on using the changeset viewer.