Changeset 95273a6 in rtems


Ignore:
Timestamp:
Jan 3, 2000, 2:06:42 PM (20 years ago)
Author:
Joel Sherrill <joel.sherrill@…>
Branches:
4.10, 4.11, 4.8, 4.9, master
Children:
db94167
Parents:
d5c4681e
Message:

Combination of coverhd.h cleanup and MVME23xx/MCP750 patch from Eric Valette
<valette@…> and Jay Kulpinski <jskulpin@…>.

Location:
c/src/lib
Files:
9 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/powerpc/shared/include/bsp.h

    rd5c4681e r95273a6  
    3333 * Total memory using RESIDUAL DATA
    3434 */
    35 unsigned int BSP_mem_size;
     35extern unsigned int BSP_mem_size;
    3636/*
    3737 * PCI Bus Frequency
    3838 */
    39 unsigned int BSP_bus_frequency;
     39extern unsigned int BSP_bus_frequency;
    4040/*
    4141 * processor clock frequency
    4242 */
    43 unsigned int BSP_processor_frequency;
     43extern unsigned int BSP_processor_frequency;
    4444/*
    4545 * Time base divisior (how many tick for 1 second).
    4646 */
    47 unsigned int BSP_time_base_divisor;
     47extern unsigned int BSP_time_base_divisor;
     48
     49#define BSP_Convert_decrementer( _value ) \
     50  ((unsigned long long) ((((unsigned long long)BSP_time_base_divisor) * 1000000ULL) /((unsigned long long) BSP_bus_frequency)) * ((unsigned long long) (_value)))
    4851
    4952extern rtems_configuration_table  BSP_Configuration;
  • c/src/lib/libbsp/powerpc/shared/irq/irq_init.c

    rd5c4681e r95273a6  
    55 *
    66 *  CopyRight (C) 1999 valette@crf.canon.fr
     7 *
     8 * Enhanced by Jay Kulpinski <jskulpin@eng01.gdds.com>
     9 * to make it valid for MVME2300 Motorola boards.
    710 *
    811 *  The license and distribution terms for this file may be
     
    250253  printk("Going to initialize the PCI/ISA bridge IRQ related setting (VIA 82C586)\n");
    251254#endif
    252   if ( (currentBoard == MESQUITE) ) {
     255  if ( currentBoard == MESQUITE ) {
    253256    VIA_isa_bridge_interrupts_setup();
     257    known_cpi_isa_bridge = 1;
     258  }
     259  if ( currentBoard == MVME_2300 ) {
     260    /* nothing to do for W83C553 bridge */
    254261    known_cpi_isa_bridge = 1;
    255262  }
  • c/src/lib/libbsp/powerpc/shared/start/start.S

    rd5c4681e r95273a6  
    5050 *   r7: End of command line string
    5151 *
     52 *   The Prep boot loader insure that the MMU is currently off...
     53 *
    5254 */
    5355       
     
    5759        mr      r28,r6
    5860        mr      r27,r7
     61        /*
     62         * Make sure we have nothing in BATS and TLB
     63         */
     64        bl      clear_bats
     65        bl      flush_tlbs
    5966/*
    6067 * Use the first pair of BAT registers to map the 1st 64MB
     
    6471        ori     r11,r11,0x7fe           /* set up BAT registers for 604 */
    6572        li      r8,2                    /* R/W access */
     73        isync
    6674        mtspr   DBAT0L,r8               /* N.B. 6xx (not 601) have valid */
    6775        mtspr   DBAT0U,r11              /* bit in upper BAT register */
     
    130138        mtctr   r30
    131139        bctr   
     140
     141/*
     142 * An undocumented "feature" of 604e requires that the v bit
     143 * be cleared before changing BAT values.
     144 *
     145 * Also, newer IBM firmware does not clear bat3 and 4 so
     146 * this makes sure it's done.
     147 *  -- Cort
     148 */
     149clear_bats:
     150        li      r20,0
     151        mfspr   r9,PVR
     152        rlwinm  r9,r9,16,16,31          /* r9 = 1 for 601, 4 for 604 */
     153        cmpwi   r9, 1
     154        SYNC
     155        beq     1f
     156        mtspr   DBAT0U,r20
     157        mtspr   DBAT0L,r20     
     158        mtspr   DBAT1U,r20
     159        mtspr   DBAT1L,r20
     160        mtspr   DBAT2U,r20
     161        mtspr   DBAT2L,r20     
     162        mtspr   DBAT3U,r20
     163        mtspr   DBAT3L,r20
     1641:     
     165        mtspr   IBAT0U,r20
     166        mtspr   IBAT0L,r20
     167        mtspr   IBAT1U,r20
     168        mtspr   IBAT1L,r20
     169        mtspr   IBAT2U,r20
     170        mtspr   IBAT2L,r20
     171        mtspr   IBAT3U,r20
     172        mtspr   IBAT3L,r20
     173        SYNC   
     174        blr
     175
     176flush_tlbs:
     177        lis     r20, 0x1000
     1781:      addic.  r20, r20, -0x1000
     179        tlbie   r20
     180        blt     1b
     181        sync
     182        blr
     183       
  • c/src/lib/libbsp/powerpc/shared/startup/bspstart.c

    rd5c4681e r95273a6  
    234234   * provided by the RAVEN
    235235   */
    236   setdbat(3, 0xfeff0000, 0xfeff0000, 0x10000, IO_PAGE);
    237 
     236  setdbat(3, 0xf0000000, 0xf0000000, 0x10000000, IO_PAGE);
    238237  select_console(CONSOLE_LOG);
    239238
  • c/src/lib/libcpu/powerpc/mpc6xx/clock/c_clock.c

    rd5c4681e r95273a6  
    144144)
    145145{
    146   Clock_Decrementer_value = (BSP_bus_frequency/4000)*
     146  Clock_Decrementer_value = (BSP_bus_frequency/BSP_time_base_divisor)*
    147147                            (BSP_Configuration.microseconds_per_tick/1000);
    148148
     
    186186        goto done;
    187187 
    188     Clock_Decrementer_value = (BSP_bus_frequency/4000)*
     188    Clock_Decrementer_value = (BSP_bus_frequency/BSP_time_base_divisor)*
    189189      (BSP_Configuration.microseconds_per_tick/1000);
    190190
  • c/src/lib/libcpu/powerpc/mpc6xx/exceptions/raw_exception.c

    rd5c4681e r95273a6  
    1111 * Copyright (C) 1999  Eric Valette (valette@crf.canon.fr)
    1212 *                     Canon Centre Recherche France.
     13 *
     14 * Enhanced by Jay Kulpinski <jskulpin@eng01.gdds.com>
     15 * to support 603, 603e, 604, 604e exceptions
    1316 *
    1417 *  The license and distribution terms for this file may be
     
    5154}
    5255
     56int mpc603_vector_is_valid(rtems_vector vector)
     57{
     58  switch(vector) {
     59  case ASM_RESET_VECTOR: /* fall through */
     60  case ASM_MACH_VECTOR:
     61  case ASM_PROT_VECTOR:
     62  case ASM_ISI_VECTOR:
     63  case ASM_EXT_VECTOR:
     64  case ASM_ALIGN_VECTOR:
     65  case ASM_PROG_VECTOR:
     66  case ASM_FLOAT_VECTOR:
     67  case ASM_DEC_VECTOR:
     68  case ASM_SYS_VECTOR:
     69  case ASM_TRACE_VECTOR:
     70    return 1;
     71  case ASM_PERFMON_VECTOR:
     72    return 0;
     73  case ASM_IMISS_VECTOR: /* fall through */
     74  case ASM_DLMISS_VECTOR:
     75  case ASM_DSMISS_VECTOR:
     76  case ASM_ADDR_VECTOR:
     77  case ASM_SYSMGMT_VECTOR:
     78    return 1;
     79  case ASM_ITM_VECTOR:
     80    return 0;
     81  }
     82  return 0;
     83}
     84
    5385int mpc604_vector_is_valid(rtems_vector vector)
    5486{
    55   /*
    56    * Please fill this for MVME2307
    57    */
    58   printk("Please complete libcpu/powerpc/XXX/raw_exception.c\n");
     87  switch(vector) {
     88  case ASM_RESET_VECTOR: /* fall through */
     89  case ASM_MACH_VECTOR:
     90  case ASM_PROT_VECTOR:
     91  case ASM_ISI_VECTOR:
     92  case ASM_EXT_VECTOR:
     93  case ASM_ALIGN_VECTOR:
     94  case ASM_PROG_VECTOR:
     95  case ASM_FLOAT_VECTOR:
     96  case ASM_DEC_VECTOR:
     97  case ASM_SYS_VECTOR:
     98  case ASM_TRACE_VECTOR:
     99  case ASM_PERFMON_VECTOR:
     100    return 1;
     101  case ASM_IMISS_VECTOR: /* fall through */
     102  case ASM_DLMISS_VECTOR:
     103  case ASM_DSMISS_VECTOR:
     104    return 0;
     105  case ASM_ADDR_VECTOR: /* fall through */
     106  case ASM_SYSMGMT_VECTOR:
     107    return 1;
     108  case ASM_ITM_VECTOR:
     109    return 0;
     110  }
    59111  return 0;
    60112}
     
    64116    unsigned int level;
    65117
    66     if (current_ppc_cpu == PPC_750) {
    67       if (!mpc750_vector_is_valid(except->exceptIndex)){
    68         return 0;
    69       }
    70       goto exception_ok;
     118    switch (current_ppc_cpu) {
     119        case PPC_750:
     120            if (!mpc750_vector_is_valid(except->exceptIndex)) {
     121                return 0;
     122            }
     123            break;
     124        case PPC_604:
     125        case PPC_604e:
     126        case PPC_604r:
     127            if (!mpc604_vector_is_valid(except->exceptIndex)) {
     128                return 0;
     129            }
     130            break;
     131        case PPC_603:
     132        case PPC_603e:
     133            if (!mpc603_vector_is_valid(except->exceptIndex)) {
     134                return 0;
     135            }
     136            break;
     137        default:
     138            printk("Please complete libcpu/powerpc/mpc6xx/raw_exception.c\n");
     139            printk("current_ppc_cpu = %x\n", current_ppc_cpu);
     140            return 0;
    71141    }
    72     if (current_ppc_cpu == PPC_604) {
    73       if (!mpc604_vector_is_valid(except->exceptIndex)){
    74         return 0;
    75       }
    76       goto exception_ok;
    77     }
    78     printk("Please complete libcpu/powerpc/XXX/raw_exception.c\n");
    79     return 0;
    80    
    81 exception_ok:
     142
    82143    /*
    83144     * Check if default handler is actually connected. If not issue an error.
  • c/src/lib/libcpu/powerpc/mpc6xx/exceptions/raw_exception.h

    rd5c4681e r95273a6  
    1313 * Copyright (C) 1999  Eric Valette (valette@crf.canon.fr)
    1414 *                     Canon Centre Recherche France.
     15 *
     16 * Enhanced by Jay Kulpinski <jskulpin@eng01.gdds.com>
     17 * to support 603, 603e, 604, 604e exceptions
    1518 *
    1619 *  The license and distribution terms for this file may be
     
    3942#define ASM_SYS_VECTOR          0x0C
    4043#define ASM_TRACE_VECTOR        0x0D
     44#define ASM_PERFMON_VECTOR      0x0F
     45#define ASM_IMISS_VECTOR        0x10
     46#define ASM_DLMISS_VECTOR       0x11
     47#define ASM_DSMISS_VECTOR       0x12
    4148#define ASM_ADDR_VECTOR         0x13
    4249#define ASM_SYSMGMT_VECTOR      0x14
  • c/src/lib/libcpu/powerpc/mpc6xx/mmu/mmuAsm.S

    rd5c4681e r95273a6  
    2020#include "asm.h"
    2121
     22/*
     23 * Each setdbat routine start by invalidating the DBAT as some
     24 * proc (604e) request the valid bit set to 0 before accepting
     25 * to write in BAT
     26 */
     27
    2228        .globl  asm_setdbat1
    2329        .type   asm_setdbat1,@function
    24 asm_setdbat1:   
     30asm_setdbat1:
     31        li      r20,0
     32        SYNC
     33        mtspr   DBAT1U,r20
     34        mtspr   DBAT1L,r20
     35        SYNC
     36        mtspr DBAT1L, r4
    2537        mtspr DBAT1U, r3
    26         mtspr DBAT1L, r4
    2738        SYNC
    2839        blr
     
    3142        .type   asm_setdbat2,@function
    3243asm_setdbat2:   
     44        li      r20,0
     45        SYNC
     46        mtspr   DBAT2U,r20
     47        mtspr   DBAT2L,r20
     48        SYNC
     49        mtspr DBAT2L, r4
    3350        mtspr DBAT2U, r3
    34         mtspr DBAT2L, r4
    3551        SYNC
    3652        blr
     
    3955        .type   asm_setdbat3,@function
    4056asm_setdbat3:   
     57        li      r20,0
     58        SYNC
     59        mtspr   DBAT3U,r20
     60        mtspr   DBAT3L,r20
     61        SYNC
     62        mtspr DBAT3L, r4
    4163        mtspr DBAT3U, r3
    42         mtspr DBAT3L, r4
    4364        SYNC
    4465        blr
  • c/src/lib/libcpu/powerpc/shared/cpu.h

    rd5c4681e r95273a6  
    192192extern ppc_cpu_revision_t get_ppc_cpu_revision();
    193193extern ppc_cpu_revision_t current_ppc_revision;
     194/*
     195 *  Routines to access the time base register
     196 */
     197
     198static inline unsigned long long PPC_Get_timebase_register( void )
     199{
     200  unsigned long tbr_low;
     201  unsigned long tbr_high;
     202  unsigned long tbr_high_old;
     203  unsigned long long tbr;
     204
     205  do {
     206    asm volatile( "mftbu %0" : "=r" (tbr_high_old));
     207    asm volatile( "mftb  %0" : "=r" (tbr_low));
     208    asm volatile( "mftbu %0" : "=r" (tbr_high));
     209  } while ( tbr_high_old != tbr_high );
     210
     211  tbr = tbr_high;
     212  tbr <<= 32;
     213  tbr |= tbr_low;
     214  return tbr;
     215}
     216
     217static inline  void PPC_Set_timebase_register (unsigned long long tbr)
     218{
     219  unsigned long tbr_low;
     220  unsigned long tbr_high;
     221
     222  tbr_low = (tbr & 0xffffffff) ;
     223  tbr_high = (tbr >> 32) & 0xffffffff;
     224  asm volatile( "mtspr 284, %0" : : "r" (tbr_low));
     225  asm volatile( "mtspr 285, %0" : : "r" (tbr_high));
     226 
     227}
    194228#endif
    195229
Note: See TracChangeset for help on using the changeset viewer.