Changeset 94fb377b in rtems


Ignore:
Timestamp:
Jan 22, 2017, 2:58:18 PM (3 years ago)
Author:
Daniel Hellstrom <daniel@…>
Branches:
5, master
Children:
1b559e3
Parents:
8acfa94
git-author:
Daniel Hellstrom <daniel@…> (01/22/17 14:58:18)
git-committer:
Daniel Hellstrom <daniel@…> (03/06/17 06:54:55)
Message:

leon, grspw_pkt: ISR RX/TX DMA interrupt source disable configurable

This patch introduces some new options to let the user control when

the ISR shall disable DMA RX/TX interrupt. The ISR can be set in three
modes when a RX/TX DMA interrupt is asserted:

1) ISR will always clear both RX/TX DMA interrupt enable. (DEFAULT).
2) ISR will never never RX or TX DMA interrupt enable, ISR will

leave RX/TX DMA interrupt enable untouched.

3) ISR will clear the interrupt enable(s) causing the interrupt,

this allows separate RX and TX IRQ handling.

This patch is backwards compatible since default mode 1) is activated
when the grspw_dma_config.flags DMAFLAGS2_IRQD field is 0.

Location:
c/src/lib/libbsp/sparc/shared
Files:
2 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/sparc/shared/include/grspw_pkt.h

    r8acfa94 r94fb377b  
    271271                                         * when rx_irq_en_cnt=0.
    272272                                         */
    273 #define DMAFLAG2_MASK   (DMAFLAG2_TXIE | DMAFLAG2_RXIE)
     273/* Defines how the ISR will disable RX/TX DMA interrupt source when a DMA RX/TX
     274 * interrupt has happended. DMA Error Interrupt always disables both RX/TX DMA
     275 * interrupt. By default both RX/TX IRQs are disabled when either a RX, TX or
     276 * both RX/TX DMA interrupt has been requested. The work-task, custom
     277 * application handler or custom ISR handler is responsible to re-enable
     278 * DMA interrupts.
     279 */
     280#define DMAFLAG2_IRQD_SRC  0x01000000   /* Disable triggering RX/TX source */
     281#define DMAFLAG2_IRQD_NONE 0x00c00000   /* Never disable RX/TX IRQ in ISR */
     282#define DMAFLAG2_IRQD_BOTH 0x00000000   /* Always disable both RX/TX sources */
     283#define DMAFLAG2_IRQD_MASK 0x01c00000   /* Mask of options */
     284#define DMAFLAG2_IRQD_BIT  22
     285
     286#define DMAFLAG2_MASK   (DMAFLAG2_TXIE | DMAFLAG2_RXIE | DMAFLAG2_IRQD_MASK)
    274287
    275288struct grspw_dma_config {
  • c/src/lib/libbsp/sparc/shared/spw/grspw_pkt.c

    r8acfa94 r94fb377b  
    26262626                break;
    26272627        }
     2628        if (msg == 0)
     2629                return;
    26282630
    26292631        rx_cond_true = 0;
    26302632        tx_cond_true = 0;
     2633
     2634        if ((dma->cfg.flags & DMAFLAG2_IRQD_MASK) == DMAFLAG2_IRQD_BOTH) {
     2635                /* In case both interrupt sources are disabled simultaneously
     2636                 * by the ISR the re-enabling of the interrupt source must also
     2637                 * do so to avoid missing interrupts. Both RX and TX process
     2638                 * will be forced.
     2639                 */
     2640                msg |= WORK_DMA_RX_MASK | WORK_DMA_TX_MASK;
     2641        }
    26312642
    26322643        if (msg & WORK_DMA_RX_MASK) {
     
    27272738        unsigned int rxirq, rxack, intto;
    27282739        int i, handled = 0, call_user_int_isr;
    2729         unsigned int message = WORK_NONE;
     2740        unsigned int message = WORK_NONE, dma_en;
    27302741#ifdef RTEMS_HAS_SMP
    27312742        IRQFLAGS_TYPE irqflags;
     
    28402851                        continue;
    28412852
    2842                 /* Disable Further IRQs (until enabled again)
     2853                handled = 1;
     2854
     2855                /* DMA error has priority, if error happens it is assumed that
     2856                 * the common work-queue stops the DMA operation for that
     2857                 * channel and makes the DMA tasks exit from their waiting
     2858                 * functions (both RX and TX tasks).
     2859                 *
     2860                 * Disable Further IRQs (until enabled again)
    28432861                 * from this DMA channel. Let the status
    28442862                 * bit remain so that they can be handled by
    28452863                 * work function.
    28462864                 */
    2847                 REG_WRITE(&priv->regs->dma[i].ctrl, dma_stat &
    2848                         ~(GRSPW_DMACTRL_RI|GRSPW_DMACTRL_TI|
    2849                         GRSPW_DMACTRL_PR|GRSPW_DMACTRL_PS|
    2850                         GRSPW_DMACTRL_RA|GRSPW_DMACTRL_TA|
    2851                         GRSPW_DMACTRL_AT));
    2852                 handled = 1;
    2853 
    2854                 /* DMA error has priority, if error happens it is assumed that
    2855                  * the common work-queue stops the DMA operation for that
    2856                  * channel and makes the DMA tasks exit from their waiting
    2857                  * functions (both RX and TX tasks).
    2858                  */
    28592865                if (irqs & GRSPW_DMA_STATUS_ERROR) {
     2866                        REG_WRITE(&priv->regs->dma[i].ctrl, dma_stat &
     2867                                ~(GRSPW_DMACTRL_RI | GRSPW_DMACTRL_TI |
     2868                                  GRSPW_DMACTRL_PR | GRSPW_DMACTRL_PS |
     2869                                  GRSPW_DMACTRL_RA | GRSPW_DMACTRL_TA |
     2870                                  GRSPW_DMACTRL_AT));
    28602871                        message |= WORK_DMA_ER(i);
    28612872                } else {
     2873                        /* determine if RX/TX interrupt source(s) shall remain
     2874                         * enabled.
     2875                         */
     2876                        if (priv->dma[i].cfg.flags & DMAFLAG2_IRQD_SRC) {
     2877                                dma_en = ~irqs >> 3;
     2878                        } else {
     2879                                dma_en = priv->dma[i].cfg.flags >>
     2880                                 (DMAFLAG2_IRQD_BIT - GRSPW_DMACTRL_TI_BIT);
     2881                        }
     2882                        dma_en &= (GRSPW_DMACTRL_RI | GRSPW_DMACTRL_TI);
     2883                        REG_WRITE(&priv->regs->dma[i].ctrl, dma_stat &
     2884                                (~(GRSPW_DMACTRL_RI | GRSPW_DMACTRL_TI |
     2885                                   GRSPW_DMACTRL_PR | GRSPW_DMACTRL_PS |
     2886                                   GRSPW_DMACTRL_RA | GRSPW_DMACTRL_TA |
     2887                                   GRSPW_DMACTRL_AT) | dma_en));
    28622888                        message |= WORK_DMA(i, irqs >> GRSPW_DMACTRL_PS_BIT);
    28632889                }
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