Changeset 94e2b11 in rtems


Ignore:
Timestamp:
Feb 13, 2005, 7:42:56 AM (16 years ago)
Author:
Ralf Corsepius <ralf.corsepius@…>
Branches:
4.10, 4.11, 4.8, 4.9, 5, master
Children:
5022a49
Parents:
5c4f1f1
Message:

2005-02-13 Ralf Corsepius <ralf.corsepius@…>

  • rtems/score/powerpc.h: Remove PPC_MSR_* defines.
Location:
cpukit/score/cpu/powerpc
Files:
2 edited

Legend:

Unmodified
Added
Removed
  • cpukit/score/cpu/powerpc/ChangeLog

    r5c4f1f1 r94e2b11  
     12005-02-13      Ralf Corsepius <ralf.corsepius@rtems.org>
     2
     3        * rtems/score/powerpc.h: Remove PPC_MSR_* defines.
     4
    152005-02-13      Ralf Corsepius <ralf.corsepius@rtems.org>
    26
  • cpukit/score/cpu/powerpc/rtems/score/powerpc.h

    r5c4f1f1 r94e2b11  
    224224#define PPC_USE_MULTIPLE        1
    225225
    226 #define PPC_MSR_0               0x00009000
    227 #define PPC_MSR_1               0x00001000
    228 #define PPC_MSR_2               0x00001000
    229 #define PPC_MSR_3               0x00000000
    230 
    231226#elif defined(mpc821)
    232227/*
     
    240235#define PPC_CACHE_ALIGNMENT     16
    241236#define PPC_INTERRUPT_MAX       71
    242 
    243 #define PPC_MSR_0               0x00009000
    244 #define PPC_MSR_1               0x00001000
    245 #define PPC_MSR_2               0x00001000
    246 #define PPC_MSR_3               0x00000000
    247237
    248238#elif defined(mpc750)
     
    678668
    679669/*
    680  *  Machine Status Register (MSR) Constants Used by RTEMS
    681  */
    682 
    683 /*
    684  *  Some PPC model manuals refer to the Exception Prefix (EP) bit as
    685  *  IP for no apparent reason.
    686  */
    687 
    688 #define PPC_MSR_RI       0x000000002 /* bit 30 - recoverable exception */
    689 #define PPC_MSR_DR       0x000000010 /* bit 27 - data address translation */
    690 #define PPC_MSR_IR       0x000000020 /* bit 26 - instruction addr translation*/
    691 
    692 #if (PPC_HAS_EXCEPTION_PREFIX)
    693 #define PPC_MSR_EP       0x000000040 /* bit 25 - exception prefix */
    694 #else
    695 #define PPC_MSR_EP       0x000000000 /* bit 25 - exception prefix */
    696 #endif
    697 
    698 #if (PPC_HAS_FPU)
    699 #define PPC_MSR_FP       0x000002000 /* bit 18 - floating point enable */
    700 #else
    701 #define PPC_MSR_FP       0x000000000 /* bit 18 - floating point enable */
    702 #endif
    703 
    704 #if (PPC_LOW_POWER_MODE == PPC_LOW_POWER_MODE_NONE)
    705 #define PPC_MSR_POW      0x000000000 /* bit 13 - power management enable */
    706 #else
    707 #define PPC_MSR_POW      0x000040000 /* bit 13 - power management enable */
    708 #endif
    709 
    710 #define PPC_MSR_ME       0x000001000 /* bit 19 - machine check enable */
    711 #define PPC_MSR_EE       0x000008000 /* bit 16 - external interrupt enable */
    712 
    713 #if (PPC_HAS_RFCI)
    714 #define PPC_MSR_CE       0x000020000 /* bit 14 - critical interrupt enable */
    715 #else
    716 #define PPC_MSR_CE       0x000000000 /* bit 14 - critical interrupt enable */
    717 #endif
    718 
    719 #define PPC_MSR_DISABLE_MASK (PPC_MSR_ME|PPC_MSR_EE|PPC_MSR_CE)
    720 
    721 /*
    722670 *  Initial value for the FPSCR register
    723671 */
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