Changeset 937a6f3c in rtems


Ignore:
Timestamp:
Jun 3, 1998, 7:00:17 PM (22 years ago)
Author:
Joel Sherrill <joel.sherrill@…>
Branches:
4.10, 4.11, 4.8, 4.9, master
Children:
3c7916f
Parents:
75d0b0b
Message:

Added CPU_ISR_PASSES_FRAME_POINTER so some ports could pass just the
vector number to user ISR's and other ports could pass both the vector
number and a pointer to the ISF.

Files:
14 edited

Legend:

Unmodified
Added
Removed
  • c/src/exec/score/cpu/a29k/cpu.h

    r75d0b0b r937a6f3c  
    159159
    160160#define CPU_ALLOCATE_INTERRUPT_STACK FALSE
     161
     162/*
     163 *  Does the RTEMS invoke the user's ISR with the vector number and
     164 *  a pointer to the saved interrupt frame (1) or just the vector
     165 *  number (0)?
     166 */
     167
     168#define CPU_ISR_PASSES_FRAME_POINTER 0
    161169
    162170/*
  • c/src/exec/score/cpu/hppa1.1/cpu.h

    r75d0b0b r937a6f3c  
    4040#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE
    4141#define CPU_ALLOCATE_INTERRUPT_STACK     TRUE
     42
     43/*
     44 *  Does the RTEMS invoke the user's ISR with the vector number and
     45 *  a pointer to the saved interrupt frame (1) or just the vector
     46 *  number (0)?
     47 */
     48
     49#define CPU_ISR_PASSES_FRAME_POINTER 0
    4250
    4351/*
  • c/src/exec/score/cpu/i386/cpu.h

    r75d0b0b r937a6f3c  
    3939#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE
    4040#define CPU_ALLOCATE_INTERRUPT_STACK     TRUE
     41
     42/*
     43 *  Does the RTEMS invoke the user's ISR with the vector number and
     44 *  a pointer to the saved interrupt frame (1) or just the vector
     45 *  number (0)?
     46 */
     47
     48#define CPU_ISR_PASSES_FRAME_POINTER 0
    4149
    4250/*
  • c/src/exec/score/cpu/i960/cpu.h

    r75d0b0b r937a6f3c  
    4040#define CPU_HAS_HARDWARE_INTERRUPT_STACK TRUE
    4141#define CPU_ALLOCATE_INTERRUPT_STACK     TRUE
     42
     43/*
     44 *  Does the RTEMS invoke the user's ISR with the vector number and
     45 *  a pointer to the saved interrupt frame (1) or just the vector
     46 *  number (0)?
     47 */
     48
     49#define CPU_ISR_PASSES_FRAME_POINTER 0
    4250
    4351/*
  • c/src/exec/score/cpu/m68k/cpu.h

    r75d0b0b r937a6f3c  
    4646#define CPU_ALLOCATE_INTERRUPT_STACK     1
    4747#endif
     48
     49/*
     50 *  Does the RTEMS invoke the user's ISR with the vector number and
     51 *  a pointer to the saved interrupt frame (1) or just the vector
     52 *  number (0)?
     53 */
     54
     55#define CPU_ISR_PASSES_FRAME_POINTER 0
    4856
    4957/*
  • c/src/exec/score/cpu/mips64orion/cpu.h

    r75d0b0b r937a6f3c  
    146146
    147147#define CPU_ALLOCATE_INTERRUPT_STACK FALSE
     148
     149/*
     150 *  Does the RTEMS invoke the user's ISR with the vector number and
     151 *  a pointer to the saved interrupt frame (1) or just the vector
     152 *  number (0)?
     153 */
     154
     155#define CPU_ISR_PASSES_FRAME_POINTER 0
    148156
    149157/*
  • c/src/exec/score/cpu/no_cpu/cpu.h

    r75d0b0b r937a6f3c  
    122122
    123123#define CPU_ALLOCATE_INTERRUPT_STACK TRUE
     124
     125/*
     126 *  Does the RTEMS invoke the user's ISR with the vector number and
     127 *  a pointer to the saved interrupt frame (1) or just the vector
     128 *  number (0)?
     129 */
     130
     131#define CPU_ISR_PASSES_FRAME_POINTER 0
    124132
    125133/*
  • c/src/exec/score/cpu/powerpc/cpu.h

    r75d0b0b r937a6f3c  
    146146
    147147#define CPU_ALLOCATE_INTERRUPT_STACK TRUE
     148
     149/*
     150 *  Does the RTEMS invoke the user's ISR with the vector number and
     151 *  a pointer to the saved interrupt frame (1) or just the vector
     152 *  number (0)?
     153 */
     154
     155#define CPU_ISR_PASSES_FRAME_POINTER 1
    148156
    149157/*
     
    10951103  (((value&0xff) << 8) | ((value >> 8)&0xff))
    10961104
     1105/*
     1106 *  Routines to access the decrementer register
     1107 */
     1108
     1109#define PPC_Set_decrementer( _clicks ) \
     1110  do { \
     1111    asm volatile( "mtdec %0" : "=r" ((_clicks)) : "r" ((_clicks)) ); \
     1112  } while (0)
     1113
     1114/*
     1115 *  Routines to access the time base register
     1116 */
     1117
     1118static inline unsigned64 PPC_Get_timebase_register( void )
     1119{
     1120  unsigned32 tbr_low;
     1121  unsigned32 tbr_high;
     1122  unsigned32 tbr_high_old;
     1123  unsigned64 tbr;
     1124
     1125  do {
     1126    asm volatile( "mftbu %0" : "=r" (tbr_high_old));
     1127    asm volatile( "mftb  %0" : "=r" (tbr_low));
     1128    asm volatile( "mftbu %0" : "=r" (tbr_high));
     1129  } while ( tbr_high_old != tbr_high );
     1130
     1131  tbr = tbr_high;
     1132  tbr <<= 32;
     1133  tbr |= tbr_low;
     1134  return tbr;
     1135}
     1136
    10971137#ifdef __cplusplus
    10981138}
  • c/src/exec/score/cpu/sh/cpu.h

    r75d0b0b r937a6f3c  
    109109#define CPU_ALLOCATE_INTERRUPT_STACK FALSE
    110110
     111/*
     112 *  Does the RTEMS invoke the user's ISR with the vector number and
     113 *  a pointer to the saved interrupt frame (1) or just the vector
     114 *  number (0)?
     115 */
     116
     117#define CPU_ISR_PASSES_FRAME_POINTER 0
    111118
    112119/*
  • c/src/exec/score/cpu/sparc/cpu.h

    r75d0b0b r937a6f3c  
    9393
    9494#define CPU_ALLOCATE_INTERRUPT_STACK      TRUE
     95
     96/*
     97 *  Does the RTEMS invoke the user's ISR with the vector number and
     98 *  a pointer to the saved interrupt frame (1) or just the vector
     99 *  number (0)?
     100 */
     101
     102#define CPU_ISR_PASSES_FRAME_POINTER 0
    95103
    96104/*
  • c/src/exec/score/cpu/unix/cpu.h

    r75d0b0b r937a6f3c  
    133133
    134134#define CPU_ALLOCATE_INTERRUPT_STACK FALSE
     135
     136/*
     137 *  Does the RTEMS invoke the user's ISR with the vector number and
     138 *  a pointer to the saved interrupt frame (1) or just the vector
     139 *  number (0)?
     140 */
     141
     142#define CPU_ISR_PASSES_FRAME_POINTER 0
    135143
    136144/*
  • c/src/exec/score/headers/isr.h

    r75d0b0b r937a6f3c  
    4747 */
    4848
     49#if (CPU_ISR_PASSES_FRAME_POINTER == 1)
     50typedef ISR_Handler ( *ISR_Handler_entry )(
     51                 ISR_Vector_number,
     52                 CPU_Interrupt_frame *
     53             );
     54#else
    4955typedef ISR_Handler ( *ISR_Handler_entry )(
    5056                 ISR_Vector_number
    5157             );
     58#endif
    5259/*
    5360 *  This constant promotes out the number of vectors truly supported by
  • c/src/exec/score/include/rtems/score/isr.h

    r75d0b0b r937a6f3c  
    4747 */
    4848
     49#if (CPU_ISR_PASSES_FRAME_POINTER == 1)
     50typedef ISR_Handler ( *ISR_Handler_entry )(
     51                 ISR_Vector_number,
     52                 CPU_Interrupt_frame *
     53             );
     54#else
    4955typedef ISR_Handler ( *ISR_Handler_entry )(
    5056                 ISR_Vector_number
    5157             );
     58#endif
    5259/*
    5360 *  This constant promotes out the number of vectors truly supported by
  • cpukit/score/include/rtems/score/isr.h

    r75d0b0b r937a6f3c  
    4747 */
    4848
     49#if (CPU_ISR_PASSES_FRAME_POINTER == 1)
     50typedef ISR_Handler ( *ISR_Handler_entry )(
     51                 ISR_Vector_number,
     52                 CPU_Interrupt_frame *
     53             );
     54#else
    4955typedef ISR_Handler ( *ISR_Handler_entry )(
    5056                 ISR_Vector_number
    5157             );
     58#endif
    5259/*
    5360 *  This constant promotes out the number of vectors truly supported by
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