Changeset 9374e9b0 in rtems for c/src/lib/libbsp/m68k/mcf52235/clock/clock.c
- Timestamp:
- 06/19/08 05:46:19 (16 years ago)
- Branches:
- 4.10, 4.11, 4.9, 5, master
- Children:
- eaaade2
- Parents:
- 8f25cec
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
c/src/lib/libbsp/m68k/mcf52235/clock/clock.c
r8f25cec r9374e9b0 18 18 /* 19 19 * Provide nanosecond extension 20 * Interrupts are disabled when this is called 20 21 */ 21 22 static uint32_t bsp_clock_nanoseconds_since_last_tick(void) 22 23 { 23 uint32_t i = MCF_PIT1_PCNTR; 24 if(MCF_PIT1_PCSR & MCF_PIT_PCSR_PIF) 25 { 26 i = MCF_PIT1_PCNTR + MCF_PIT1_PMR; 27 } 28 return (i - s_pcntrAtTick) * s_nanoScale; 24 uint32_t i; 25 26 if (MCF_PIT1_PCSR & MCF_PIT_PCSR_PIF) { 27 i = s_pcntrAtTick + (MCF_PIT1_PMR - MCF_PIT1_PCNTR); 28 } 29 else { 30 i = s_pcntrAtTick - MCF_PIT1_PCNTR; 31 } 32 return i * s_nanoScale; 29 33 } 30 34 … … 51 55 * Turn off the clock 52 56 */ 53 static void Clock_driver_support_shutdown_hardware() 57 static void Clock_driver_support_shutdown_hardware() 54 58 { 55 59 MCF_PIT1_PCSR &= ~MCF_PIT_PCSR_EN; 56 60 } 57 61 … … 63 67 static void Clock_driver_support_initialize_hardware() 64 68 { 65 int level; 66 uint32_t pmr; 67 uint32_t preScaleCode = 0; 68 uint32_t clk = bsp_get_CPU_clock_speed() >> 1; 69 uint32_t tps = 1000000 / Configuration.microseconds_per_tick; 70 while (preScaleCode < 15) { 71 pmr = (clk >> preScaleCode) / tps; 72 if(pmr < (1 << 15)) break; 73 preScaleCode++; 74 } 75 s_nanoScale = 1000000000 / (clk >> preScaleCode); 69 int level; 70 uint32_t pmr; 71 uint32_t preScaleCode = 0; 72 uint32_t clk = bsp_get_CPU_clock_speed() >> 1; 73 uint32_t tps = 1000000 / Configuration.microseconds_per_tick; 76 74 77 MCF_INTC0_ICR56 = MCF_INTC_ICR_IL(PIT3_IRQ_LEVEL) | 78 MCF_INTC_ICR_IP(PIT3_IRQ_PRIORITY); 79 rtems_interrupt_disable( level ); 80 MCF_INTC0_IMRH &= ~MCF_INTC_IMRH_MASK56; 81 MCF_PIT1_PCSR &= ~MCF_PIT_PCSR_EN; 82 rtems_interrupt_enable( level ); 75 while (preScaleCode < 15) { 76 pmr = (clk >> preScaleCode) / tps; 77 if (pmr < (1 << 15)) 78 break; 79 preScaleCode++; 80 } 81 s_nanoScale = 1000000000 / (clk >> preScaleCode); 83 82 84 MCF_PIT1_PCSR = MCF_PIT_PCSR_PRE(preScaleCode) | 85 MCF_PIT_PCSR_OVW | 86 MCF_PIT_PCSR_PIE | 87 MCF_PIT_PCSR_RLD; 88 MCF_PIT1_PMR = pmr; 89 MCF_PIT1_PCSR = MCF_PIT_PCSR_PRE(preScaleCode) | 90 MCF_PIT_PCSR_PIE | 91 MCF_PIT_PCSR_RLD | 92 MCF_PIT_PCSR_EN; 93 s_pcntrAtTick = MCF_PIT1_PCNTR; 83 MCF_INTC0_ICR56 = MCF_INTC_ICR_IL(PIT3_IRQ_LEVEL) | 84 MCF_INTC_ICR_IP(PIT3_IRQ_PRIORITY); 85 rtems_interrupt_disable(level); 86 MCF_INTC0_IMRH &= ~MCF_INTC_IMRH_MASK56; 87 MCF_PIT1_PCSR &= ~MCF_PIT_PCSR_EN; 88 rtems_interrupt_enable(level); 89 90 MCF_PIT1_PCSR = MCF_PIT_PCSR_PRE(preScaleCode) | 91 MCF_PIT_PCSR_OVW | MCF_PIT_PCSR_PIE | MCF_PIT_PCSR_RLD; 92 MCF_PIT1_PMR = pmr; 93 MCF_PIT1_PCSR = MCF_PIT_PCSR_PRE(preScaleCode) | 94 MCF_PIT_PCSR_PIE | MCF_PIT_PCSR_RLD | MCF_PIT_PCSR_EN; 95 s_pcntrAtTick = MCF_PIT1_PCNTR; 94 96 } 95 97
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