Changeset 92e2757 in rtems


Ignore:
Timestamp:
Apr 17, 2014, 8:37:10 AM (5 years ago)
Author:
Ralf Kirchner <ralf.kirchner@…>
Branches:
4.11, master
Children:
db5a84d
Parents:
cbd9e63
git-author:
Ralf Kirchner <ralf.kirchner@…> (04/17/14 08:37:10)
git-committer:
Sebastian Huber <sebastian.huber@…> (04/17/14 11:25:11)
Message:

bsp/arm: Correct L2 cache flushing

Correct misalignment handling and prepare for locking.

File:
1 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/arm/shared/arm-l2c-310/cache_.h

    rcbd9e63 r92e2757  
    8181#define CACHE_l2C_310_WAY_MASK ( ( 1 << CACHE_l2C_310_NUM_WAYS ) - 1 )
    8282
     83#define CACHE_MIN( a, b ) \
     84  ((a < b) ? (a) : (b))
     85
    8386
    8487/* RTL release number as can be read from cache_id register */
     
    10331036
    10341037static inline void
    1035 cache_l2c_310_flush_1_line( const void *d_addr )
     1038cache_l2c_310_flush_1_line(
     1039  const void *d_addr,
     1040  const bool  is_errata_588369applicable
     1041)
    10361042{
    10371043  volatile L2CC *l2cc = (volatile L2CC *) BSP_ARM_L2CC_BASE;
    10381044
    1039 
    1040   if( l2c_310_cache_errata_is_applicable_588369() ) {
     1045  if( is_errata_588369applicable ) {
    10411046    /*
    10421047    * Errata 588369 says that clean + inv may keep the
    1043     * cache line if it was clean, the recommanded
     1048    * cache line if it was clean, the recommended
    10441049    * workaround is to clean then invalidate the cache
    10451050    * line, with write-back and cache linefill disabled.
     
    10511056    l2cc->clean_inv_pa = (uint32_t) d_addr;
    10521057  }
    1053 
     1058}
     1059
     1060static inline void
     1061cache_l2c_310_flush_range( const void* d_addr, const size_t n_bytes )
     1062{
     1063  /* Back starting address up to start of a line and invalidate until ADDR_LAST */
     1064  uint32_t       adx               = (uint32_t)d_addr
     1065    & ~CACHE_L2C_310_DATA_LINE_MASK;
     1066  const uint32_t ADDR_LAST         =
     1067    (uint32_t)( (size_t)d_addr + n_bytes - 1 );
     1068  uint32_t       block_end         =
     1069    CACHE_MIN( ADDR_LAST, adx + CACHE_MAX_LOCKING_BYTES );
     1070  bool is_errata_588369_applicable =
     1071    l2c_310_cache_errata_is_applicable_588369();
     1072
     1073  for (;
     1074       adx      <= ADDR_LAST;
     1075       adx       = block_end + 1,
     1076       block_end = CACHE_MIN( ADDR_LAST, adx + CACHE_MAX_LOCKING_BYTES )) {
     1077    for (; adx <= block_end; adx += CPU_DATA_CACHE_ALIGNMENT ) {
     1078      cache_l2c_310_flush_1_line( (void*)adx, is_errata_588369_applicable );
     1079    }
     1080    if( block_end < ADDR_LAST ) {
     1081      rtems_interrupt_lock_release( &l2c_310_cache_lock, &lock_context );
     1082      rtems_interrupt_lock_acquire( &l2c_310_cache_lock, &lock_context );
     1083    }
     1084  }
    10541085  cache_l2c_310_sync();
    1055 }
    1056 
    1057 static inline void
    1058 cache_l2c_310_flush_range( const void *addr, size_t n_bytes )
    1059 {
    1060   if ( n_bytes != 0 ) {
    1061     uint32_t       adx       = (uint32_t) addr
    1062                                & ~CACHE_L2C_310_DATA_LINE_MASK;
    1063     const uint32_t ADDR_LAST =
    1064       ( (uint32_t) addr + n_bytes - 1 ) & ~CACHE_L2C_310_DATA_LINE_MASK;
    1065     volatile L2CC *l2cc      = (volatile L2CC *) BSP_ARM_L2CC_BASE;
    1066 
    1067     for (; adx <= ADDR_LAST; adx += CPU_DATA_CACHE_ALIGNMENT ) {
    1068       l2cc->clean_pa = adx;
    1069     }
    1070     cache_l2c_310_sync();
    1071   }
    10721086}
    10731087
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