Changeset 92d8038 in rtems


Ignore:
Timestamp:
Apr 19, 2013, 9:53:07 AM (6 years ago)
Author:
Sebastian Huber <sebastian.huber@…>
Branches:
4.11, master
Children:
10e348ab
Parents:
7a44d06
git-author:
Sebastian Huber <sebastian.huber@…> (04/19/13 09:53:07)
git-committer:
Sebastian Huber <sebastian.huber@…> (04/23/13 07:59:57)
Message:

bsp/mpc5200: New BSP variant BRS6L

Location:
c/src/lib/libbsp/powerpc/gen5200
Files:
2 added
5 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/powerpc/gen5200/Makefile.am

    r7a44d06 r92d8038  
    3434project_lib_DATA += startup/linkcmds
    3535EXTRA_DIST = startup/linkcmds.brs5l
     36EXTRA_DIST += startup/linkcmds.brs6l
    3637EXTRA_DIST += startup/linkcmds.icecube
    3738EXTRA_DIST += startup/linkcmds.pm520_cr825
  • c/src/lib/libbsp/powerpc/gen5200/configure.ac

    r7a44d06 r92d8038  
    3737RTEMS_BSPOPTS_SET([BSP_RESET_BOARD_AT_EXIT],[icecube],[1])
    3838RTEMS_BSPOPTS_SET([BSP_RESET_BOARD_AT_EXIT],[pm520_*],[1])
    39 RTEMS_BSPOPTS_SET([BSP_RESET_BOARD_AT_EXIT],[brs5l],[1])
     39RTEMS_BSPOPTS_SET([BSP_RESET_BOARD_AT_EXIT],[brs*l],[1])
    4040RTEMS_BSPOPTS_SET([BSP_RESET_BOARD_AT_EXIT],[*],[0])
    4141RTEMS_BSPOPTS_HELP([BSP_RESET_BOARD_AT_EXIT],
     
    4545RTEMS_BSPOPTS_SET([BSP_GPIOPCR_INITVAL],[pm520_ze30],[0x01552104])
    4646
    47 RTEMS_BSPOPTS_SET([BSP_GPIOPCR_INITMASK],[brs5l],[0xb30F0F77])
    48 RTEMS_BSPOPTS_SET([BSP_GPIOPCR_INITVAL],[brs5l],[0x91050444])
     47RTEMS_BSPOPTS_SET([BSP_GPIOPCR_INITMASK],[brs*l],[0xb30F0F77])
     48RTEMS_BSPOPTS_SET([BSP_GPIOPCR_INITVAL],[brs*l],[0x91050444])
    4949
    5050RTEMS_BSPOPTS_SET([BSP_GPIOPCR_INITMASK],[dp2],[0x337F3F77])
     
    6969## on cr825, we have PSC1/2/3
    7070RTEMS_BSPOPTS_SET([BSP_UART_AVAIL_MASK],[pm520_cr825],[0x07])
    71 ## on brs5l, we have PSC1/2/3
    72 RTEMS_BSPOPTS_SET([BSP_UART_AVAIL_MASK],[brs5l],[0x07])
     71## on brs5l and brs6l, we have PSC1/2/3
     72RTEMS_BSPOPTS_SET([BSP_UART_AVAIL_MASK],[brs*l],[0x07])
    7373## on icecube, we only have PSC1
    7474RTEMS_BSPOPTS_SET([BSP_UART_AVAIL_MASK],[icecube],[0x01])
     
    110110[enable settings for BRS5L])
    111111
     112RTEMS_BSPOPTS_SET([MPC5200_BOARD_BRS6L],[brs6l],[1])
     113RTEMS_BSPOPTS_HELP([MPC5200_BOARD_BRS6L],
     114[enable settings for BRS6L])
     115
    112116RTEMS_BSPOPTS_SET([MPC5200_BOARD_DP2],[dp2],[1])
    113117RTEMS_BSPOPTS_HELP([MPC5200_BOARD_DP2],
  • c/src/lib/libbsp/powerpc/gen5200/include/bsp.h

    r7a44d06 r92d8038  
    110110#define HAS_NVRAM_93CXX
    111111
     112#elif defined(MPC5200_BOARD_BRS6L)
     113  #define MPC5200_BRS6L_FPGA_BEGIN 0x800000
     114  #define MPC5200_BRS6L_FPGA_SIZE (64 * 1024)
     115  #define MPC5200_BRS6L_FPGA_END \
     116    (MPC5200_BRS6L_FPGA_BEGIN + MPC5200_BRS6L_FPGA_SIZE)
     117
     118  #define MPC5200_BRS6L_MRAM_BEGIN 0xff000000
     119  #define MPC5200_BRS6L_MRAM_SIZE (4 * 1024 * 1024)
     120  #define MPC5200_BRS6L_MRAM_END \
     121    (MPC5200_BRS6L_MRAM_BEGIN + MPC5200_BRS6L_MRAM_SIZE)
    112122#elif defined (PM520)
    113123
     
    194204#define XLB_CLOCK (bsp_uboot_board_info.bi_busfreq)
    195205#define G2_CLOCK  (bsp_uboot_board_info.bi_intfreq)
    196 #elif defined(MPC5200_BOARD_BRS5L)
     206#elif defined(MPC5200_BOARD_BRS5L) || defined(MPC5200_BOARD_BRS6L)
    197207#define IPB_CLOCK 66000000   /* 66 MHz */
    198208#define XLB_CLOCK 132000000  /* 132 MHz */
  • c/src/lib/libbsp/powerpc/gen5200/start/start.S

    r7a44d06 r92d8038  
    301301#if defined(MPC5200_BOARD_BRS5L)
    302302        #define CSBOOTROM_VAL 0x0101D910
     303#elif defined(MPC5200_BOARD_BRS6L)
     304        #define CSBOOTROM_VAL 0x0202D910
    303305#endif
    304306
     
    529531        #define SDELAY_VAL 0x00000004
    530532
     533#if defined(MPC5200_BOARD_BRS6L)
     534        #define CFG1_VAL 0x73722930
     535#else
    531536        /*
    532537         * Single Read2Read/Write delay=0xC, Single Write2Read/Prec. delay=0x4
     
    534539         */
    535540        #define CFG1_VAL 0xC4222600
    536 
     541#endif
     542
     543#if defined(MPC5200_BOARD_BRS6L)
     544        #define CFG2_VAL 0x47770000
     545#else
    537546        /* Refr.2No-Read delay=0x06, Write latency=0x0 */
    538547        /* Burst2Read Prec.delay=0x8, Burst Write delay=0x8 */
    539548        /* Burst Read2Write delay=0xB, Burst length=0x7, Read Tap=0x4 */
    540549        #define CFG2_VAL 0xCCC70004
     550#endif
    541551
    542552#if defined(MPC5200_BOARD_BRS5L)
     
    544554        /* Refresh counter=0xFFFF */
    545555        #define CTRL_VAL 0xD1470000
     556#elif defined(MPC5200_BOARD_BRS6L)
     557        #define CTRL_VAL 0xF15F0F00
    546558#else
    547559        /* Mode Set enabled, Clock enabled, Auto refresh enabled, Mem. data drv */
     
    550562#endif
    551563
     564#if defined(MPC5200_BOARD_BRS6L)
     565        /* Enable DLL, normal drive strength */
     566        #define EMODE_VAL 0x40010000
     567#endif
     568
     569#if defined(MPC5200_BOARD_BRS6L)
     570        /* Burst length = 8, burst type sequential, CAS latency 2.5, normal operation/reset DLL */
     571        #define MODE_VAL 0x058D0000
     572#else
    552573        /* Op.Mode=0x0, Read CAS latency=0x2, Burst length=0x3, Write strobe puls */
    553574        #define MODE_VAL 0x008D0000
     575#endif
     576
     577#if defined(MPC5200_BOARD_BRS6L)
     578        /* Burst length = 8, burst type sequential, CAS latency 2.5, normal operation */
     579        #define SECOND_MODE_VAL (MODE_VAL & ~0x04000000)
     580#endif
    554581
    555582        /* SDRAM initialization according to application note AN3221 */
  • c/src/lib/libbsp/powerpc/gen5200/startup/cpuinit.c

    r7a44d06 r92d8038  
    122122  BAT dbat;
    123123
    124 #if defined(MPC5200_BOARD_BRS5L)
     124#if defined(MPC5200_BOARD_BRS5L) || defined(MPC5200_BOARD_BRS6L)
    125125  calc_dbat_regvals(
    126126    &dbat,
     
    158158  );
    159159  SET_DBAT(2,dbat.batu,dbat.batl);
    160 
    161   calc_dbat_regvals(
    162     &dbat,
    163     (uint32_t) bsp_dpram_start,
    164     128 * 1024,
    165     false,
    166     true,
    167     false,
    168     true,
    169     BPP_RW
    170   );
    171   SET_DBAT(3,dbat.batu,dbat.batl);
    172160#elif defined (HAS_UBOOT)
    173161  uint32_t start = 0;
     
    286274  );
    287275  SET_DBAT(4, dbat.batu, dbat.batl);
     276#elif defined(MPC5200_BOARD_BRS5L)
     277  calc_dbat_regvals(
     278    &dbat,
     279    (uint32_t) bsp_dpram_start,
     280    128 * 1024,
     281    false,
     282    true,
     283    false,
     284    true,
     285    BPP_RW
     286  );
     287  SET_DBAT(3,dbat.batu,dbat.batl);
     288#elif defined(MPC5200_BOARD_BRS6L)
     289  enable_bat_4_to_7();
     290
     291  /* FPGA */
     292  calc_dbat_regvals(
     293    &dbat,
     294    MPC5200_BRS6L_FPGA_BEGIN,
     295    MPC5200_BRS6L_FPGA_SIZE,
     296    false,
     297    true,
     298    false,
     299    true,
     300    BPP_RW
     301  );
     302  SET_DBAT(3,dbat.batu,dbat.batl);
     303
     304  /* MRAM */
     305  calc_dbat_regvals(
     306    &dbat,
     307    MPC5200_BRS6L_MRAM_BEGIN,
     308    MPC5200_BRS6L_MRAM_SIZE,
     309    true,
     310    false,
     311    false,
     312    false,
     313    BPP_RW
     314  );
     315  SET_DBAT(4,dbat.batu,dbat.batl);
    288316#endif
    289317}
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