Ignore:
Timestamp:
Jan 12, 2021, 6:13:08 AM (4 months ago)
Author:
Sebastian Huber <sebastian.huber@…>
Branches:
master
Children:
19acb3b
Parents:
c968b27
git-author:
Sebastian Huber <sebastian.huber@…> (01/12/21 06:13:08)
git-committer:
Sebastian Huber <sebastian.huber@…> (02/01/21 05:26:18)
Message:

nios2: Use Per_CPU_Control::isr_dispatch_disable

File:
1 edited

Legend:

Unmodified
Added
Removed
  • cpukit/score/cpu/nios2/nios2-eic-il-low-level.S

    rc968b27 r9165349d  
    4242
    4343        .extern _Per_CPU_Information
    44         .extern _Nios2_Thread_dispatch_disabled
    4544        .extern _Nios2_ISR_Status_interrupts_disabled
    4645
     
    6665        ldb     r12, %gprel(_Per_CPU_Information + PER_CPU_DISPATCH_NEEDED)(gp)
    6766
    68         /* Load Nios II specific thread dispatch disabled */
    69         ldw     r13, %gprel(_Nios2_Thread_dispatch_disabled)(gp)
     67        /* Load thread dispatch after ISR disable indicator */
     68        ldw     r13, %gprel(_Per_CPU_Information + PER_CPU_ISR_DISPATCH_DISABLE)(gp)
    7069
    7170        /* Read status */
     
    9392        bne     r14, zero, no_thread_dispatch
    9493
    95         /* Is Nios II specific thread dispatch allowed? */
     94        /* Is thread dispatch after ISR allowed? */
    9695        bne     r13, zero, no_thread_dispatch
    9796
     
    9998        rdprs   r15, sp, -FRAME_SIZE
    10099
    101         /* Disable Nios II specific thread dispatch */
    102         stw     r12, %gprel(_Nios2_Thread_dispatch_disabled)(gp)
     100        /* Disable thread dispatch after ISR */
     101        stw     r12, %gprel(_Per_CPU_Information + PER_CPU_ISR_DISPATCH_DISABLE)(gp)
    103102
    104103        /* Save context */
     
    185184        bne     r13, zero, enable_interrupts_before_thread_dispatch
    186185
    187         /* Enable Nios II specific thread dispatch */
    188         stw     zero, %gprel(_Nios2_Thread_dispatch_disabled)(gp)
     186        /* Enable thread dispatch after ISR */
     187        stw     zero, %gprel(_Per_CPU_Information + PER_CPU_ISR_DISPATCH_DISABLE)(gp)
    189188
    190189        /* Restore remaining volatile register */
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