Index: ports/beagleboneblack/am335x.h
===================================================================
--- ports/beagleboneblack/am335x.h	(revision 82f69414387102e992dd63a8df9e5472996d3c0e)
+++ ports/beagleboneblack/am335x.h	(revision 90c27015b9177cc66f85282c55887e50ed2d6262)
@@ -50,5 +50,5 @@
 /*===========================================================================*/
 #define EMIF0_BASE			0x4C000000
-#define EMIFO_REG(_x_)			*(vulong *)(EMIFO_BASE + _x_)
+#define EMIF0_REG(_x_)			*(vulong *)(EMIF0_BASE + _x_)
 /*---------------------------------------------------------------------------*/
 /* EMIFO Register offsets */
@@ -58,5 +58,5 @@
 #define SDRAM_CONFIG_2			0x000C
 #define SDRAM_REF_CTRL			0x0010
-#define SDRAM_REF_CTRL_SHOW		0x0014
+#define SDRAM_REF_CTRL_SHDW		0x0014
 #define SDRAM_TIM_1			0x0018
 #define SDRAM_TIM_1_SHDW		0x001C
@@ -91,4 +91,78 @@
 #define CONN_ID_TO_CLASS_SRVC_2_MAP	0x0108
 #define RW_EXEC_THRESHOLD		0x0120
+/* Register fields and values */
+#define SDRAM_CONFIG_REG_SDRAM_TYPE		0xE0000000
+#define SDRAM_CONFIG_REG_SDRAM_TYPE_DDR1	0x00000000
+#define SDRAM_CONFIG_REG_SDRAM_TYPE_LPDDR1	0x20000000
+#define SDRAM_CONFIG_REG_SDRAM_TYPE_DDR2	0x40000000
+#define SDRAM_CONFIG_REG_SDRAM_TYPE_DDR3	0x60000000
+#define SDRAM_CONFIG_REG_IBANK_POS		0x18000000
+#define SDRAM_CONFIG_REG_IBANK_POS_0		0x00000000
+#define SDRAM_CONFIG_REG_IBANK_POS_1		0x08000000
+#define SDRAM_CONFIG_REG_IBANK_POS_2		0x10000000
+#define SDRAM_CONFIG_REG_IBANK_POS_3		0x18000000
+#define SDRAM_CONFIG_REG_DDR_TERM		0x07000000
+#define SDRAM_CONFIG_REG_DDR_TERM_DISABLE	0x00000000
+#define SDRAM_CONFIG_REG_DDR_TERM_DDR2_75OHM	0x01000000
+#define SDRAM_CONFIG_REG_DDR_TERM_DDR2_150OHM	0x02000000
+#define SDRAM_CONFIG_REG_DDR_TERM_DDR2_50OHM	0x03000000
+#define SDRAM_CONFIG_REG_DDR_TERM_DDR3_RZQ_4	0x01000000
+#define SDRAM_CONFIG_REG_DDR_TERM_DDR3_RZQ_2	0x02000000
+#define SDRAM_CONFIG_REG_DDR_TERM_DDR3_RZQ_6	0x03000000
+#define SDRAM_CONFIG_REG_DDR_TERM_DDR3_RZQ_12	0x04000000
+#define SDRAM_CONFIG_REG_DDR_TERM_DDR3_RZQ_8	0x05000000
+#define SDRAM_CONFIG_REG_DDR2_DDQS		0x00800000
+#define SDRAM_CONFIG_REG_DDR2_DDQS_SINGLE_DQS	0x00000000
+#define SDRAM_CONFIG_REG_DDR2_DDQS_DIFF_DQS	0x00800000
+#define SDRAM_CONFIG_REG_DYN_ODT		0x00600000
+#define SDRAM_CONFIG_REG_DYN_ODT_DISABLE	0x00000000
+#define SDRAM_CONFIG_REG_DYN_ODT_RZQ_4		0x00200000
+#define SDRAM_CONFIG_REG_DYN_ODT_RZQ_2		0x00400000
+#define SDRAM_CONFIG_REG_DDR_DISABLE_DLL	0x00100000
+#define SDRAM_CONFIG_REG_DDR_DISABLE_DLL_ENABLE		0x00000000
+#define SDRAM_CONFIG_REG_DDR_DISABLE_DLL_DISABLE	0x00100000
+#define SDRAM_CONFIG_REG_SDRAM_DRIVE		0x000C0000
+#define SDRAM_CONFIG_REG_SDRAM_DRIVE_RZQ_6	0x00000000
+#define SDRAM_CONFIG_REG_SDRAM_DRIVE_RZQ_7	0x00040000
+#define SDRAM_CONFIG_REG_CAS_WR_LATENCY		0x00030000
+#define SDRAM_CONFIG_REG_CAS_WR_LATENCY_5	0x00000000
+#define SDRAM_CONFIG_REG_CAS_WR_LATENCY_6	0x00010000
+#define SDRAM_CONFIG_REG_CAS_WR_LATENCY_7	0x00020000
+#define SDRAM_CONFIG_REG_CAS_WR_LATENCY_8	0x00030000
+#define SDRAM_CONFIG_REG_NARROW_MODE		0x0000C000
+#define SDRAM_CONFIG_REG_NARROW_MODE_32BIT	0x00000000
+#define SDRAM_CONFIG_REG_NARROW_MODE_16BIT	0x00004000
+#define SDRAM_CONFIG_REG_CAS_LATENCY		0x00003C00
+#define SDRAM_CONFIG_REG_CAS_LATENCY_5		0x00000800
+#define SDRAM_CONFIG_REG_CAS_LATENCY_6		0x00001000
+#define SDRAM_CONFIG_REG_CAS_LATENCY_7		0x00001800
+#define SDRAM_CONFIG_REG_CAS_LATENCY_8		0x00002000
+#define SDRAM_CONFIG_REG_CAS_LATENCY_9		0x00002800
+#define SDRAM_CONFIG_REG_CAS_LATENCY_10		0x00003000
+#define SDRAM_CONFIG_REG_CAS_LATENCY_11		0x00003800
+#define SDRAM_CONFIG_REG_ROWSIZE		0x00000380
+#define SDRAM_CONFIG_REG_ROWSIZE_9BIT		0x00000000
+#define SDRAM_CONFIG_REG_ROWSIZE_10BIT		0x00000080
+#define SDRAM_CONFIG_REG_ROWSIZE_11BIT		0x00000100
+#define SDRAM_CONFIG_REG_ROWSIZE_12BIT		0x00000180
+#define SDRAM_CONFIG_REG_ROWSIZE_13BIT		0x00000200
+#define SDRAM_CONFIG_REG_ROWSIZE_14BIT		0x00000280
+#define SDRAM_CONFIG_REG_ROWSIZE_15BIT		0x00000300
+#define SDRAM_CONFIG_REG_ROWSIZE_16BIT		0x00000380
+#define SDRAM_CONFIG_REG_IBANK			0x00000070
+#define SDRAM_CONFIG_REG_IBANK_1		0x00000000
+#define SDRAM_CONFIG_REG_IBANK_2		0x00000010
+#define SDRAM_CONFIG_REG_IBANK_4		0x00000020
+#define SDRAM_CONFIG_REG_IBANK_8		0x00000030
+#define SDRAM_CONFIG_REG_EBANK			0x00000008
+#define SDRAM_CONFIG_REG_EBANK_1		0x00000000
+#define SDRAM_CONFIG_REG_PAGESIZE		0x00000007
+#define SDRAM_CONFIG_REG_PAGESIZE_256_WORD	0x00000000
+#define SDRAM_CONFIG_REG_PAGESIZE_512_WORD	0x00000001
+#define SDRAM_CONFIG_REG_PAGESIZE_1024_WORD	0x00000002
+#define SDRAM_CONFIG_REG_PAGESIZE_2048_WORD	0x00000003
+#define SDRAM_CONFIG_2_REG_EBANK_POS		0x08000000
+#define SDRAM_CONFIG_2_REG_EBANK_POS_0		0x00000000
+#define SDRAM_CONFIG_2_REG_EBANK_POS_1		0x08000000
 /*===========================================================================*/
 
@@ -189,4 +263,12 @@
 
 /*===========================================================================*/
+/* CM_PER Registers */
+/*===========================================================================*/
+#define CM_PER_L3_CLKSTCTRL		0x0C
+#define CM_PER_EMIF_CLKCTRL		0x28
+/*===========================================================================*/
+
+
+/*===========================================================================*/
 /* CM_WKUP Registers */
 /*===========================================================================*/
@@ -230,9 +312,9 @@
 #define CM_CLKMODE_DPLL_DDR             0x94
 #define CM_CLKMODE_DPLL_DISP            0x98
-#define CM_CLKSEL_DPLL_PERIPH           0x9C
+#define CM_CLKSEL_DPLL_PER           	0x9C
 #define CM_DIV_M2_DPLL_DDR              0xA0
-#define CM_DIV_M3_DPLL_DISP             0xA4
-#define CM_DIV_M3_DPLL_MPU              0xA8
-#define CM_DIV_M3_DPLL_PER              0xAC
+#define CM_DIV_M2_DPLL_DISP             0xA4
+#define CM_DIV_M2_DPLL_MPU              0xA8
+#define CM_DIV_M2_DPLL_PER              0xAC
 #define CM_WKUP_WKUP_M3_CLKCTRL         0xB0
 #define CM_WKUP_UART0_CLKCTRL           0xB4
@@ -248,7 +330,14 @@
 
 
+#define CM_CLKSEL_DPLL_PER_DPLL_MULT	(960 << 8)
+#define CM_CLKSEL_DPLL_PER_DPLL_DIV	(23)
+#define CM_CLKSEL_DPLL_PER_DPLL_SD_DIV	(4 << 24)
+
+
 /*===========================================================================*/
 /* Control Module Registers */
 /*===========================================================================*/
+#define CONTROL_STATUS			0x0040
+#define CONTROL_EMIF_SDRAM_CONFIG	0x0110
 #define CONF_GPMC_A5                    0x0854
 #define CONF_GPMC_A6                    0x0858
@@ -257,4 +346,50 @@
 #define CONF_UART0_RXD                  0x0970
 #define CONF_UART0_TXD                  0x0974
+#define DDR_IO_CTRL			0x0E04
+#define VTP_CTRL			0x0E0C
+#define VREF_CTRL			0x0E14
+#define DDR_CKE_CTRL			0x131C
+#define DDR_CMD0_IOCTRL			0x1404
+#define DDR_CMD1_IOCTRL			0x1408
+#define DDR_CMD2_IOCTRL			0x140C
+#define DDR_DATA0_IOCTRL		0x1440
+#define DDR_DATA1_IOCTRL		0x1444
+/*===========================================================================*/
+
+
+/*===========================================================================*/
+/* DDR2/3/mDDR PHY Registers */
+/*===========================================================================*/
+#define CMD0_REG_PHY_CTRL_SLAVE_RATIO_0		0x001C
+#define CMD0_REG_PHY_DLL_LOCK_DIFF_0		0x0028
+#define CMD0_REG_PHY_INVERT_CLKOUT_0		0x002C
+#define CMD1_REG_PHY_CTRL_SLAVE_RATIO_0		0x0050
+#define CMD1_REG_PHY_DLL_LOCK_DIFF_0		0x005C
+#define CMD1_REG_PHY_INVERT_CLKOUT_0		0x0060
+#define CMD2_REG_PHY_CTRL_SLAVE_RATIO_0		0x0084
+#define CMD2_REG_PHY_DLL_LOCK_DIFF_0		0x0090
+#define CMD2_REG_PHY_INVERT_CLKOUT_0		0x0094
+#define DATA0_REG_PHY_RD_DQS_SLAVE_RATIO_0	0x00C8
+#define DATA0_REG_PHY_WR_DQS_SLAVE_RATIO_0	0x00DC
+#define DATA0_REG_PHY_WRLVL_INIT_RATIO_0	0x00F0
+#define DATA0_REG_PHY_WRLVL_INIT_MODE_0		0x00F8
+#define DATA0_REG_PHY_GATELVL_INIT_RATIO_0	0x00FC
+#define DATA0_REG_PHY_GATELVL_INIT_MODE_0	0x0104
+#define DATA0_REG_PHY_FIFO_WE_SLAVE_RATIO_0	0x0108
+#define DATA0_REG_PHY_DQ_OFFSET_0		0x011C
+#define DATA0_REG_PHY_WR_DATA_SLAVE_RATIO_0	0x0120
+#define DATA0_REG_PHY_USE_RANK0_DELAYS		0x0134
+#define DATA0_REG_PHY_LOCK_DIFF_0		0x0138
+#define DATA1_REG_PHY_RD_DQS_SLAVE_RATIO_0	0x016C
+#define DATA1_REG_PHY_WR_DQS_SLAVE_RATIO_0	0x0180
+#define DATA1_REG_PHY_WRLVL_INIT_RATIO_0	0x0194
+#define DATA1_REG_PHY_WRLVL_INIT_MODE_0		0x019C
+#define DATA1_REG_PHY_GATELVL_INIT_RATIO_0	0x01A0
+#define DATA1_REG_PHY_GATELVL_INIT_MODE_0	0x01A8
+#define DATA1_REG_PHY_FIFO_WE_SLAVE_RATIO_0	0x01AC
+#define DATA1_REG_PHY_DQ_OFFSET_0		0x01C0
+#define DATA1_REG_PHY_WR_DATA_SLAVE_RATIO_0	0x01C4
+#define DATA1_REG_PHY_USE_RANK0_DELAYS		0x01D8
+#define DATA1_REG_PHY_LOCK_DIFF_0		0x01DC
 /*===========================================================================*/
 
