Changeset 90c2701 in umon
- Timestamp:
- 07/16/15 11:26:40 (9 years ago)
- Branches:
- master
- Children:
- 9f5d36e
- Parents:
- 82f6941
- git-author:
- Jarielle Catbagan <jcatbagan93@…> (07/16/15 11:26:40)
- git-committer:
- Ed Sutter <edsutterjr@…> (07/18/15 13:13:23)
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
ports/beagleboneblack/am335x.h
r82f6941 r90c2701 50 50 /*===========================================================================*/ 51 51 #define EMIF0_BASE 0x4C000000 52 #define EMIF O_REG(_x_) *(vulong *)(EMIFO_BASE + _x_)52 #define EMIF0_REG(_x_) *(vulong *)(EMIF0_BASE + _x_) 53 53 /*---------------------------------------------------------------------------*/ 54 54 /* EMIFO Register offsets */ … … 58 58 #define SDRAM_CONFIG_2 0x000C 59 59 #define SDRAM_REF_CTRL 0x0010 60 #define SDRAM_REF_CTRL_SH OW 0x001460 #define SDRAM_REF_CTRL_SHDW 0x0014 61 61 #define SDRAM_TIM_1 0x0018 62 62 #define SDRAM_TIM_1_SHDW 0x001C … … 91 91 #define CONN_ID_TO_CLASS_SRVC_2_MAP 0x0108 92 92 #define RW_EXEC_THRESHOLD 0x0120 93 /* Register fields and values */ 94 #define SDRAM_CONFIG_REG_SDRAM_TYPE 0xE0000000 95 #define SDRAM_CONFIG_REG_SDRAM_TYPE_DDR1 0x00000000 96 #define SDRAM_CONFIG_REG_SDRAM_TYPE_LPDDR1 0x20000000 97 #define SDRAM_CONFIG_REG_SDRAM_TYPE_DDR2 0x40000000 98 #define SDRAM_CONFIG_REG_SDRAM_TYPE_DDR3 0x60000000 99 #define SDRAM_CONFIG_REG_IBANK_POS 0x18000000 100 #define SDRAM_CONFIG_REG_IBANK_POS_0 0x00000000 101 #define SDRAM_CONFIG_REG_IBANK_POS_1 0x08000000 102 #define SDRAM_CONFIG_REG_IBANK_POS_2 0x10000000 103 #define SDRAM_CONFIG_REG_IBANK_POS_3 0x18000000 104 #define SDRAM_CONFIG_REG_DDR_TERM 0x07000000 105 #define SDRAM_CONFIG_REG_DDR_TERM_DISABLE 0x00000000 106 #define SDRAM_CONFIG_REG_DDR_TERM_DDR2_75OHM 0x01000000 107 #define SDRAM_CONFIG_REG_DDR_TERM_DDR2_150OHM 0x02000000 108 #define SDRAM_CONFIG_REG_DDR_TERM_DDR2_50OHM 0x03000000 109 #define SDRAM_CONFIG_REG_DDR_TERM_DDR3_RZQ_4 0x01000000 110 #define SDRAM_CONFIG_REG_DDR_TERM_DDR3_RZQ_2 0x02000000 111 #define SDRAM_CONFIG_REG_DDR_TERM_DDR3_RZQ_6 0x03000000 112 #define SDRAM_CONFIG_REG_DDR_TERM_DDR3_RZQ_12 0x04000000 113 #define SDRAM_CONFIG_REG_DDR_TERM_DDR3_RZQ_8 0x05000000 114 #define SDRAM_CONFIG_REG_DDR2_DDQS 0x00800000 115 #define SDRAM_CONFIG_REG_DDR2_DDQS_SINGLE_DQS 0x00000000 116 #define SDRAM_CONFIG_REG_DDR2_DDQS_DIFF_DQS 0x00800000 117 #define SDRAM_CONFIG_REG_DYN_ODT 0x00600000 118 #define SDRAM_CONFIG_REG_DYN_ODT_DISABLE 0x00000000 119 #define SDRAM_CONFIG_REG_DYN_ODT_RZQ_4 0x00200000 120 #define SDRAM_CONFIG_REG_DYN_ODT_RZQ_2 0x00400000 121 #define SDRAM_CONFIG_REG_DDR_DISABLE_DLL 0x00100000 122 #define SDRAM_CONFIG_REG_DDR_DISABLE_DLL_ENABLE 0x00000000 123 #define SDRAM_CONFIG_REG_DDR_DISABLE_DLL_DISABLE 0x00100000 124 #define SDRAM_CONFIG_REG_SDRAM_DRIVE 0x000C0000 125 #define SDRAM_CONFIG_REG_SDRAM_DRIVE_RZQ_6 0x00000000 126 #define SDRAM_CONFIG_REG_SDRAM_DRIVE_RZQ_7 0x00040000 127 #define SDRAM_CONFIG_REG_CAS_WR_LATENCY 0x00030000 128 #define SDRAM_CONFIG_REG_CAS_WR_LATENCY_5 0x00000000 129 #define SDRAM_CONFIG_REG_CAS_WR_LATENCY_6 0x00010000 130 #define SDRAM_CONFIG_REG_CAS_WR_LATENCY_7 0x00020000 131 #define SDRAM_CONFIG_REG_CAS_WR_LATENCY_8 0x00030000 132 #define SDRAM_CONFIG_REG_NARROW_MODE 0x0000C000 133 #define SDRAM_CONFIG_REG_NARROW_MODE_32BIT 0x00000000 134 #define SDRAM_CONFIG_REG_NARROW_MODE_16BIT 0x00004000 135 #define SDRAM_CONFIG_REG_CAS_LATENCY 0x00003C00 136 #define SDRAM_CONFIG_REG_CAS_LATENCY_5 0x00000800 137 #define SDRAM_CONFIG_REG_CAS_LATENCY_6 0x00001000 138 #define SDRAM_CONFIG_REG_CAS_LATENCY_7 0x00001800 139 #define SDRAM_CONFIG_REG_CAS_LATENCY_8 0x00002000 140 #define SDRAM_CONFIG_REG_CAS_LATENCY_9 0x00002800 141 #define SDRAM_CONFIG_REG_CAS_LATENCY_10 0x00003000 142 #define SDRAM_CONFIG_REG_CAS_LATENCY_11 0x00003800 143 #define SDRAM_CONFIG_REG_ROWSIZE 0x00000380 144 #define SDRAM_CONFIG_REG_ROWSIZE_9BIT 0x00000000 145 #define SDRAM_CONFIG_REG_ROWSIZE_10BIT 0x00000080 146 #define SDRAM_CONFIG_REG_ROWSIZE_11BIT 0x00000100 147 #define SDRAM_CONFIG_REG_ROWSIZE_12BIT 0x00000180 148 #define SDRAM_CONFIG_REG_ROWSIZE_13BIT 0x00000200 149 #define SDRAM_CONFIG_REG_ROWSIZE_14BIT 0x00000280 150 #define SDRAM_CONFIG_REG_ROWSIZE_15BIT 0x00000300 151 #define SDRAM_CONFIG_REG_ROWSIZE_16BIT 0x00000380 152 #define SDRAM_CONFIG_REG_IBANK 0x00000070 153 #define SDRAM_CONFIG_REG_IBANK_1 0x00000000 154 #define SDRAM_CONFIG_REG_IBANK_2 0x00000010 155 #define SDRAM_CONFIG_REG_IBANK_4 0x00000020 156 #define SDRAM_CONFIG_REG_IBANK_8 0x00000030 157 #define SDRAM_CONFIG_REG_EBANK 0x00000008 158 #define SDRAM_CONFIG_REG_EBANK_1 0x00000000 159 #define SDRAM_CONFIG_REG_PAGESIZE 0x00000007 160 #define SDRAM_CONFIG_REG_PAGESIZE_256_WORD 0x00000000 161 #define SDRAM_CONFIG_REG_PAGESIZE_512_WORD 0x00000001 162 #define SDRAM_CONFIG_REG_PAGESIZE_1024_WORD 0x00000002 163 #define SDRAM_CONFIG_REG_PAGESIZE_2048_WORD 0x00000003 164 #define SDRAM_CONFIG_2_REG_EBANK_POS 0x08000000 165 #define SDRAM_CONFIG_2_REG_EBANK_POS_0 0x00000000 166 #define SDRAM_CONFIG_2_REG_EBANK_POS_1 0x08000000 93 167 /*===========================================================================*/ 94 168 … … 189 263 190 264 /*===========================================================================*/ 265 /* CM_PER Registers */ 266 /*===========================================================================*/ 267 #define CM_PER_L3_CLKSTCTRL 0x0C 268 #define CM_PER_EMIF_CLKCTRL 0x28 269 /*===========================================================================*/ 270 271 272 /*===========================================================================*/ 191 273 /* CM_WKUP Registers */ 192 274 /*===========================================================================*/ … … 230 312 #define CM_CLKMODE_DPLL_DDR 0x94 231 313 #define CM_CLKMODE_DPLL_DISP 0x98 232 #define CM_CLKSEL_DPLL_PER IPH0x9C314 #define CM_CLKSEL_DPLL_PER 0x9C 233 315 #define CM_DIV_M2_DPLL_DDR 0xA0 234 #define CM_DIV_M 3_DPLL_DISP 0xA4235 #define CM_DIV_M 3_DPLL_MPU 0xA8236 #define CM_DIV_M 3_DPLL_PER 0xAC316 #define CM_DIV_M2_DPLL_DISP 0xA4 317 #define CM_DIV_M2_DPLL_MPU 0xA8 318 #define CM_DIV_M2_DPLL_PER 0xAC 237 319 #define CM_WKUP_WKUP_M3_CLKCTRL 0xB0 238 320 #define CM_WKUP_UART0_CLKCTRL 0xB4 … … 248 330 249 331 332 #define CM_CLKSEL_DPLL_PER_DPLL_MULT (960 << 8) 333 #define CM_CLKSEL_DPLL_PER_DPLL_DIV (23) 334 #define CM_CLKSEL_DPLL_PER_DPLL_SD_DIV (4 << 24) 335 336 250 337 /*===========================================================================*/ 251 338 /* Control Module Registers */ 252 339 /*===========================================================================*/ 340 #define CONTROL_STATUS 0x0040 341 #define CONTROL_EMIF_SDRAM_CONFIG 0x0110 253 342 #define CONF_GPMC_A5 0x0854 254 343 #define CONF_GPMC_A6 0x0858 … … 257 346 #define CONF_UART0_RXD 0x0970 258 347 #define CONF_UART0_TXD 0x0974 348 #define DDR_IO_CTRL 0x0E04 349 #define VTP_CTRL 0x0E0C 350 #define VREF_CTRL 0x0E14 351 #define DDR_CKE_CTRL 0x131C 352 #define DDR_CMD0_IOCTRL 0x1404 353 #define DDR_CMD1_IOCTRL 0x1408 354 #define DDR_CMD2_IOCTRL 0x140C 355 #define DDR_DATA0_IOCTRL 0x1440 356 #define DDR_DATA1_IOCTRL 0x1444 357 /*===========================================================================*/ 358 359 360 /*===========================================================================*/ 361 /* DDR2/3/mDDR PHY Registers */ 362 /*===========================================================================*/ 363 #define CMD0_REG_PHY_CTRL_SLAVE_RATIO_0 0x001C 364 #define CMD0_REG_PHY_DLL_LOCK_DIFF_0 0x0028 365 #define CMD0_REG_PHY_INVERT_CLKOUT_0 0x002C 366 #define CMD1_REG_PHY_CTRL_SLAVE_RATIO_0 0x0050 367 #define CMD1_REG_PHY_DLL_LOCK_DIFF_0 0x005C 368 #define CMD1_REG_PHY_INVERT_CLKOUT_0 0x0060 369 #define CMD2_REG_PHY_CTRL_SLAVE_RATIO_0 0x0084 370 #define CMD2_REG_PHY_DLL_LOCK_DIFF_0 0x0090 371 #define CMD2_REG_PHY_INVERT_CLKOUT_0 0x0094 372 #define DATA0_REG_PHY_RD_DQS_SLAVE_RATIO_0 0x00C8 373 #define DATA0_REG_PHY_WR_DQS_SLAVE_RATIO_0 0x00DC 374 #define DATA0_REG_PHY_WRLVL_INIT_RATIO_0 0x00F0 375 #define DATA0_REG_PHY_WRLVL_INIT_MODE_0 0x00F8 376 #define DATA0_REG_PHY_GATELVL_INIT_RATIO_0 0x00FC 377 #define DATA0_REG_PHY_GATELVL_INIT_MODE_0 0x0104 378 #define DATA0_REG_PHY_FIFO_WE_SLAVE_RATIO_0 0x0108 379 #define DATA0_REG_PHY_DQ_OFFSET_0 0x011C 380 #define DATA0_REG_PHY_WR_DATA_SLAVE_RATIO_0 0x0120 381 #define DATA0_REG_PHY_USE_RANK0_DELAYS 0x0134 382 #define DATA0_REG_PHY_LOCK_DIFF_0 0x0138 383 #define DATA1_REG_PHY_RD_DQS_SLAVE_RATIO_0 0x016C 384 #define DATA1_REG_PHY_WR_DQS_SLAVE_RATIO_0 0x0180 385 #define DATA1_REG_PHY_WRLVL_INIT_RATIO_0 0x0194 386 #define DATA1_REG_PHY_WRLVL_INIT_MODE_0 0x019C 387 #define DATA1_REG_PHY_GATELVL_INIT_RATIO_0 0x01A0 388 #define DATA1_REG_PHY_GATELVL_INIT_MODE_0 0x01A8 389 #define DATA1_REG_PHY_FIFO_WE_SLAVE_RATIO_0 0x01AC 390 #define DATA1_REG_PHY_DQ_OFFSET_0 0x01C0 391 #define DATA1_REG_PHY_WR_DATA_SLAVE_RATIO_0 0x01C4 392 #define DATA1_REG_PHY_USE_RANK0_DELAYS 0x01D8 393 #define DATA1_REG_PHY_LOCK_DIFF_0 0x01DC 259 394 /*===========================================================================*/ 260 395
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