Changeset 8fb685b in rtems


Ignore:
Timestamp:
Jun 5, 2014, 6:41:56 AM (7 years ago)
Author:
Sebastian Huber <sebastian.huber@…>
Branches:
4.11, 5, master
Children:
40599e7e
Parents:
330ccc5
git-author:
Sebastian Huber <sebastian.huber@…> (06/05/14 06:41:56)
git-committer:
Sebastian Huber <sebastian.huber@…> (06/06/14 06:02:09)
Message:

bsp/altera-cyclone-v: Simplify start hooks

Use arm_a9mpcore_start_hook_0(). The L2 cache is now disabled.

File:
1 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/arm/altera-cyclone-v/startup/bspstarthooks.c

    r330ccc5 r8fb685b  
    11/*
    2  * Copyright (c) 2013 embedded brains GmbH.  All rights reserved.
     2 * Copyright (c) 2013-2014 embedded brains GmbH.  All rights reserved.
    33 *
    44 *  embedded brains GmbH
     
    2121#include <bsp/linker-symbols.h>
    2222#include <alt_address_space.h>
    23 #include "socal/socal.h"
    24 #include "socal/alt_sdr.h"
    25 #include "socal/hps.h"
    26 #include "../include/arm-cache-l1.h"
    27 
    28 #ifdef RTEMS_SMP
    29   #define MMU_DATA_READ_WRITE ARMV7_MMU_DATA_READ_WRITE_SHAREABLE
    30 #else
    31   #define MMU_DATA_READ_WRITE ARMV7_MMU_DATA_READ_WRITE_CACHED
    32 #endif
     23#include <socal/socal.h>
     24#include <socal/alt_sdr.h>
     25#include <socal/hps.h>
    3326
    3427/* 1 MB reset default value for address filtering start */
    3528#define BSPSTART_L2_CACHE_ADDR_FILTERING_START_RESET 0x100000
    3629
    37 #ifndef BSPSTARTHOOKS_MIN
    38 #define BSPSTARTHOOKS_MIN( a, b ) ( ( a ) < ( b ) ? ( a ) : ( b ) )
    39 #endif
    40 
    41 LINKER_SYMBOL( bsp_section_nocache_size );
    42 LINKER_SYMBOL( bsp_section_nocache_end );
    43 LINKER_SYMBOL( bsp_section_nocache_begin );
     30LINKER_SYMBOL(bsp_section_nocache_size);
     31LINKER_SYMBOL(bsp_section_nocache_end);
     32LINKER_SYMBOL(bsp_section_nocache_begin);
    4433
    4534BSP_START_DATA_SECTION static const arm_cp15_start_section_config
     
    5746};
    5847
    59 BSP_START_TEXT_SECTION static void setup_mmu_and_cache( const uint32_t CPU_ID )
     48BSP_START_TEXT_SECTION void bsp_start_hook_0( void )
    6049{
    61   uint32_t       ctrl  = arm_cp15_get_control();
    62   const uint32_t CORES = BSPSTARTHOOKS_MIN(
    63     (uintptr_t) bsp_processor_count,
    64     rtems_configuration_get_maximum_processors() );
    65 
    66   /* We expect the L1 caches and program flow prediction to be off */
    67   assert( ( ctrl & ARM_CP15_CTRL_I ) == 0 );
    68   assert( ( ctrl & ARM_CP15_CTRL_C ) == 0 );
    69   assert( ( ctrl & ARM_CP15_CTRL_Z ) == 0 );
    70 
    71   ctrl = arm_cp15_start_setup_mmu_and_cache(
    72     ARM_CP15_CTRL_A | ARM_CP15_CTRL_M,
    73     ARM_CP15_CTRL_AFE
    74     );
    75 
    76   if( CPU_ID == 0 ) {
    77     arm_cp15_start_setup_translation_table(
    78       (uint32_t *) bsp_translation_table_base,
    79       ARM_MMU_DEFAULT_CLIENT_DOMAIN,
    80       &altcycv_mmu_config_table[0],
    81       RTEMS_ARRAY_SIZE( altcycv_mmu_config_table )
    82     );
    83   } else {
    84     /* FIXME: Sharing the translation table between processors is brittle */
    85     arm_cp15_set_translation_table_base((uint32_t *) bsp_translation_table_base);
    86   }
    87 
    88   /* Enable MMU */
    89   ctrl |= ARM_CP15_CTRL_M;
    90 
    91   arm_cp15_set_control( ctrl );
    92  
    93   if( CPU_ID == (CORES - 1) ) {
    94     /* Enable all cache levels for the last core */
    95     rtems_cache_enable_instruction();
    96     rtems_cache_enable_data();
    97   } else {
    98     /* Enable only L1 cache */
    99     arm_cache_l1_enable_data();
    100     arm_cache_l1_enable_instruction();
    101   }
    102 
    103   /* Enable flow control prediction aka. branch prediction */
    104 
    105 /* TODO: With the current network stack 06-Feb2014 in_checksum()
    106  * becomes a severe performance bottle neck with branch prediction enabled
    107    ctrl |= ARM_CP15_CTRL_Z;
    108    arm_cp15_set_control(ctrl);*/
     50  arm_cp15_instruction_cache_invalidate();
     51  arm_cp15_data_cache_invalidate_all_levels();
     52  arm_a9mpcore_start_hook_0();
    10953}
    11054
    111 BSP_START_TEXT_SECTION void bsp_start_hook_0( void )
     55BSP_START_TEXT_SECTION static void setup_mmu_and_cache(void)
    11256{
    113   uint32_t ctrl;
    114   volatile a9mpcore_scu *scu    = (volatile a9mpcore_scu *) BSP_ARM_A9MPCORE_SCU_BASE;
    115   uint32_t               cpu_id = arm_cortex_a9_get_multiprocessor_cpu_id();
    116   const uint32_t         CORES  = BSPSTARTHOOKS_MIN(
    117     (uintptr_t) bsp_processor_count,
    118     rtems_configuration_get_maximum_processors() );
     57  uint32_t ctrl = arm_cp15_start_setup_mmu_and_cache(
     58    ARM_CP15_CTRL_A | ARM_CP15_CTRL_M,
     59    ARM_CP15_CTRL_AFE | ARM_CP15_CTRL_Z
     60  );
    11961
    120   assert( cpu_id < CORES );
    121 
    122   if( cpu_id < CORES ) {
    123     if( cpu_id == 0 ) {
    124       ctrl = arm_cp15_mmu_disable( 32 );
    125 
    126       ctrl &= ~( ARM_CP15_CTRL_I | ARM_CP15_CTRL_C | ARM_CP15_CTRL_Z );
    127       arm_cp15_set_control( ctrl );
    128 
    129       /* Enable Snoop Control Unit (SCU) */
    130       arm_a9mpcore_start_scu_enable( scu );
    131     }
    132 
    133 #ifdef RTEMS_SMP
    134     /* Enable cache coherency support for this processor */
    135     uint32_t actlr = arm_cp15_get_auxiliary_control();
    136     actlr |= ARM_CORTEX_A9_ACTL_SMP | ARM_CORTEX_A9_ACTL_FW;
    137     arm_cp15_set_auxiliary_control(actlr);
    138 #endif
    139 
    140     if (cpu_id == 0) {
    141       arm_a9mpcore_start_scu_invalidate(scu, cpu_id, 0xF);
    142     }
    143 
    144     setup_mmu_and_cache( cpu_id );
    145 
    146 #ifdef RTEMS_SMP
    147     if (cpu_id != 0) {
    148       arm_a9mpcore_start_set_vector_base();
    149 
    150       arm_gic_irq_initialize_secondary_cpu();
    151 
    152       arm_cp15_set_domain_access_control(
    153         ARM_CP15_DAC_DOMAIN(ARM_MMU_DEFAULT_CLIENT_DOMAIN, ARM_CP15_DAC_CLIENT)
    154       );
    155       _SMP_Start_multitasking_on_secondary_processor();
    156     }
    157 #endif
    158   } else {
    159     /* FIXME: Shutdown processor */
    160     while (1) {
    161       __asm__ volatile ("wfi");
    162     }
    163   }
     62  arm_cp15_start_setup_translation_table_and_enable_mmu_and_cache(
     63    ctrl,
     64    (uint32_t *) bsp_translation_table_base,
     65    ARM_MMU_DEFAULT_CLIENT_DOMAIN,
     66    &altcycv_mmu_config_table[0],
     67    RTEMS_ARRAY_SIZE(altcycv_mmu_config_table)
     68  );
    16469}
    16570
     
    199104  arm_a9mpcore_start_hook_1();
    200105  bsp_start_copy_sections();
    201 
     106  setup_mmu_and_cache();
    202107  bsp_start_clear_bss();
    203108}
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