Ignore:
Timestamp:
06/14/17 14:53:44 (5 years ago)
Author:
Sichen Zhao <1473996754@…>
Branches:
5, master
Children:
369372c3
Parents:
7741545b
git-author:
Sichen Zhao <1473996754@…> (06/14/17 14:53:44)
git-committer:
Joel Sherrill <joel@…> (06/14/17 17:11:31)
Message:

Add the i2c driver for Beaglebone Black

Update ticket #2891 and my GSOC project
add c/src/lib/libbsp/arm/beagle/i2c/bbb-i2c.c
modify c/src/lib/libbsp/arm/beagle/include/i2c.h
modify c/src/lib/libbsp/arm/beagle/include/bbb-gpio.h
modify c/src/lib/libcpu/arm/shared/include/am335x.h
modify c/src/lib/libbsp/arm/beagle/Makefile.am
Now can read the EEPROM by i2c, the test application link is: https://github.com/hahchenchen/GSOC-test-application

File:
1 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libcpu/arm/shared/include/am335x.h

    r7741545b r8f550d2  
    564564
    565565
     566/* I2C registers */
     567#define AM335X_I2C0_BASE 0x44e0b000
     568    /* I2C0 base address */
     569#define AM335X_I2C1_BASE 0x4802a000
     570    /* I2C1 base address */
     571#define AM335X_I2C2_BASE 0x4819c000
     572    /* I2C2 base address */
     573#define AM335X_I2C_REVNB_LO        0x00
     574    /* Module Revision Register (low bytes) */
     575#define AM335X_I2C_REVNB_HI        0x04
     576    /* Module Revision Register (high bytes) */
     577#define AM335X_I2C_SYSC            0x10
     578    /* System Configuration Register */
     579#define AM335X_I2C_IRQSTATUS_RAW   0x24
     580    /* I2C Status Raw Register */
     581#define AM335X_I2C_IRQSTATUS       0x28
     582    /* I2C Status Register */
     583#define AM335X_I2C_IRQENABLE_SET   0x2c
     584    /* I2C Interrupt Enable Set Register */
     585#define AM335X_I2C_IRQENABLE_CLR   0x30
     586    /* I2C Interrupt Enable Clear Register */
     587#define AM335X_I2C_WE              0x34
     588    /* I2C Wakeup Enable Register */
     589#define AM335X_I2C_DMARXENABLE_SET 0x38
     590    /* Receive DMA Enable Set Register */
     591#define AM335X_I2C_DMATXENABLE_SET 0x3c
     592    /* Transmit DMA Enable Set Register */
     593#define AM335X_I2C_DMARXENABLE_CLR 0x40
     594    /* Receive DMA Enable Clear Register */
     595#define AM335X_I2C_DMATXENABLE_CLR 0x44
     596    /* Transmit DMA Enable Clear Register */
     597#define AM335X_I2C_DMARXWAKE_EN    0x48
     598    /* Receive DMA Wakeup Register */
     599#define AM335X_I2C_DMATXWAKE_EN    0x4c
     600    /* Transmit DMA Wakeup Register */
     601#define AM335X_I2C_SYSS            0x90
     602    /* System Status Register */
     603#define AM335X_I2C_BUF             0x94
     604    /* Buffer Configuration Register */
     605#define AM335X_I2C_CNT             0x98
     606    /* Data Counter Register */
     607#define AM335X_I2C_DATA            0x9c
     608    /* Data Access Register */
     609#define AM335X_I2C_CON             0xa4
     610    /* I2C Configuration Register */
     611#define AM335X_I2C_OA              0xa8
     612    /* I2C Own Address Register */
     613#define AM335X_I2C_SA              0xac
     614    /* I2C Slave Address Register */
     615#define AM335X_I2C_PSC             0xb0
     616    /* I2C Clock Prescaler Register */
     617#define AM335X_I2C_SCLL            0xb4
     618    /* I2C SCL Low Time Register */
     619#define AM335X_I2C_SCLH            0xb8
     620    /* I2C SCL High Time Register */
     621#define AM335X_I2C_SYSTEST         0xbc
     622    /* System Test Register */
     623#define AM335X_I2C_BUFSTAT         0xc0
     624    /* I2C Buffer Status Register */
     625#define AM335X_I2C_OA1             0xc4
     626    /* I2C Own Address 1 Register */
     627#define AM335X_I2C_OA2             0xc8
     628    /* I2C Own Address 2 Register */
     629#define AM335X_I2C_OA3             0xcc
     630    /* I2C Own Address 3 Register */
     631#define AM335X_I2C_ACTOA           0xd0
     632    /* Active Own Address Register */
     633#define AM335X_I2C_SBLOCK          0xd4
     634    /* I2C Clock Blocking Enable Register */
     635
     636#define AM335X_CM_PER_L4LS_CLKSTCTRL  (0x0)
     637#define AM335X_CM_PER_L4LS_CLKSTCTRL_CLKTRCTRL_SW_WKUP  (0x2u)
     638#define AM335X_CM_PER_L4LS_CLKSTCTRL_CLKTRCTRL  (0x00000003u)
     639#define AM335X_CM_PER_L4LS_CLKCTRL  (0x60)
     640#define AM335X_CM_PER_L4LS_CLKCTRL_MODULEMODE_ENABLE  (0x2u)
     641#define AM335X_CM_PER_L4LS_CLKCTRL_MODULEMODE  (0x00000003u)
     642#define AM335X_CM_PER_I2C1_CLKCTRL  (0x48)
     643#define AM335X_CM_PER_I2C1_CLKCTRL_MODULEMODE_ENABLE  (0x2u)
     644#define AM335X_CM_PER_I2C1_CLKCTRL_MODULEMODE  (0x00000003u)
     645#define AM335X_CM_PER_I2C2_CLKCTRL (0x44)
     646#define AM335X_CM_PER_I2C2_CLKCTRL_MODULEMODE_ENABLE  (0x2u)
     647#define AM335X_CM_PER_I2C2_CLKCTRL_MODULEMODE  (0x00000003u)
     648#define AM335X_CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_L4LS_GCLK (0x00000100u)
     649#define AM335X_CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_I2C_FCLK (0x01000000u)
     650#define AM335X_CM_PER_I2C1_CLKCTRL_MODULEMODE   (0x00000003u)
     651#define AM335X_I2C_CON_XSA  (0x00000100u)
     652#define AM335X_I2C_CFG_10BIT_SLAVE_ADDR  AM335X_I2C_CON_XSA
     653#define AM335X_I2C_CON_XSA_SHIFT  (0x00000008u)
     654#define AM335X_I2C_CFG_7BIT_SLAVE_ADDR  (0 << AM335X_I2C_CON_XSA_SHIFT)
     655#define AM335X_I2C_CON_I2C_EN   (0x00008000u)
     656#define AM335X_I2C_CON_TRX   (0x00000200u)
     657#define AM335X_I2C_CON_MST   (0x00000400u)
     658#define AM335X_I2C_CON_STB   (0x00000800u)
     659#define AM335X_I2C_SYSC_AUTOIDLE   (0x00000001u)
     660
     661/*I2C0 module clock registers*/
     662
     663#define AM335X_CM_WKUP_CONTROL_CLKCTRL   (0x4)
     664#define AM335X_CM_WKUP_CLKSTCTRL   (0x0)
     665#define AM335X_CM_WKUP_I2C0_CLKCTRL   (0xb8)
     666#define AM335X_CM_WKUP_I2C0_CLKCTRL_MODULEMODE_ENABLE   (0x2u)
     667#define AM335X_CM_WKUP_I2C0_CLKCTRL_MODULEMODE   (0x00000003u)
     668#define AM335X_CM_WKUP_CONTROL_CLKCTRL_IDLEST_FUNC   (0x0u)
     669#define AM335X_CM_WKUP_CONTROL_CLKCTRL_IDLEST_SHIFT   (0x00000010u)
     670#define AM335X_CM_WKUP_CONTROL_CLKCTRL_IDLEST   (0x00030000u)
     671#define AM335X_CM_WKUP_CLKSTCTRL_CLKACTIVITY_I2C0_GFCLK   (0x00000800u)
     672#define AM335X_CM_WKUP_I2C0_CLKCTRL_IDLEST_FUNC   (0x0u)
     673#define AM335X_CM_WKUP_I2C0_CLKCTRL_IDLEST_SHIFT   (0x00000010u)
     674#define AM335X_CM_WKUP_I2C0_CLKCTRL_IDLEST   (0x00030000u)
     675#define AM335X_SOC_CM_WKUP_REGS                     (AM335X_CM_PER_ADDR + 0x400)
     676
     677/* I2C status Register */
     678#define AM335X_I2C_IRQSTATUS_NACK (1 << 1)
     679#define AM335X_I2C_IRQSTATUS_ROVR (1 << 11)
     680#define AM335X_I2C_IRQSTATUS_AL   (1<<0)
     681#define AM335X_I2C_IRQSTATUS_ARDY (1 << 2)
     682#define AM335X_I2C_IRQSTATUS_RRDY (1 << 3)
     683#define AM335X_I2C_IRQSTATUS_XRDY (1 << 4)
     684#define AM335X_I2C_IRQSTATUS_XUDF (1 << 10)
     685#define AM335X_I2C_BUF_TXFIFO_CLR   (0x00000040u)
     686#define AM335X_I2C_BUF_RXFIFO_CLR   (0x00004000u)
     687#define AM335X_I2C_IRQSTATUS_AAS  (1 << 9)
     688#define AM335X_I2C_IRQSTATUS_BF  (1 << 8)
     689#define AM335X_I2C_IRQSTATUS_STC  (1 << 6)
     690#define AM335X_I2C_IRQSTATUS_GC (1 << 5)
     691#define AM335X_I2C_IRQSTATUS_XDR (1 << 14)
     692#define AM335X_I2C_IRQSTATUS_RDR (1 << 13)
     693
     694#define AM335X_I2C_INT_RECV_READY AM335X_I2C_IRQSTATUS_RRDY
     695#define AM335X_I2C_CON_STOP  (0x00000002u)
     696#define AM335X_I2C_CON_START (0x00000001u)
     697#define AM335X_I2C_CFG_MST_RX AM335X_I2C_CON_MST
     698#define AM335X_I2C_CFG_MST_TX  (AM335X_I2C_CON_TRX | AM335X_I2C_CON_MST)
     699#define AM335X_I2C_IRQSTATUS_RAW_BB   (0x00001000u)
     700#define AM335X_CM_PER_OCPWP_L3_CLKSTCTRL_CLKACTIVITY_OCPWP_L4_GCLK (0x00000020u)
     701#define AM335X_I2C_INT_STOP_CONDITION AM335X_I2C_IRQSTATUS_BF
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