Changeset 8f550d2 in rtems


Ignore:
Timestamp:
06/14/17 14:53:44 (6 years ago)
Author:
Sichen Zhao <1473996754@…>
Branches:
5, master
Children:
369372c3
Parents:
7741545b
git-author:
Sichen Zhao <1473996754@…> (06/14/17 14:53:44)
git-committer:
Joel Sherrill <joel@…> (06/14/17 17:11:31)
Message:

Add the i2c driver for Beaglebone Black

Update ticket #2891 and my GSOC project
add c/src/lib/libbsp/arm/beagle/i2c/bbb-i2c.c
modify c/src/lib/libbsp/arm/beagle/include/i2c.h
modify c/src/lib/libbsp/arm/beagle/include/bbb-gpio.h
modify c/src/lib/libcpu/arm/shared/include/am335x.h
modify c/src/lib/libbsp/arm/beagle/Makefile.am
Now can read the EEPROM by i2c, the test application link is: ​https://github.com/hahchenchen/GSOC-test-application

Location:
c/src/lib
Files:
1 added
4 edited

Legend:

Unmodified
Added
Removed

  • c/src/lib/libbsp/arm/beagle/Makefile.am

    r7741545b r8f550d2  
    115115
    116116# I2C
     117libbsp_a_SOURCES += i2c/bbb-i2c.c
    117118
    118119# GPIO

  • c/src/lib/libbsp/arm/beagle/include/bbb-gpio.h

    r7741545b r8f550d2  
    3636#define BBB_PD_EN ~BBB_PU_EN
    3737#define BBB_MUXMODE(X) (X & 0x7)
     38#define BBB_RXACTIVE (1 << 5)
     39#define BBB_SLEWCTRL (1 << 6)
    3840
    3941#ifdef __cplusplus

  • c/src/lib/libbsp/arm/beagle/include/i2c.h

    r7741545b r8f550d2  
    2525
    2626#include <rtems.h>
    27 
     27#include <dev/i2c/i2c.h>
    2828#include <bsp.h>
    2929
    … …  
    3535/* I2C Configuration Register (I2C_CON): */
    3636
    37 #define I2C_CON_EN  (1 << 15)  /* I2C module enable */
    38 #define I2C_CON_BE  (1 << 14)  /* Big endian mode */
    39 #define I2C_CON_STB (1 << 11)  /* Start byte mode (master mode only) */
    40 #define I2C_CON_MST (1 << 10)  /* Master/slave mode */
    41 #define I2C_CON_TRX (1 << 9)   /* Transmitter/receiver mode */
     37#define BBB_I2C_CON_EN  (1 << 15)  /* I2C module enable */
     38#define BBB_I2C_CON_BE  (1 << 14)  /* Big endian mode */
     39#define BBB_I2C_CON_STB (1 << 11)  /* Start byte mode (master mode only) */
     40#define BBB_I2C_CON_MST (1 << 10)  /* Master/slave mode */
     41#define BBB_I2C_CON_TRX (1 << 9)   /* Transmitter/receiver mode */
    4242           /* (master mode only) */
    43 #define I2C_CON_XA  (1 << 8)   /* Expand address */
    44 #define I2C_CON_STP (1 << 1)   /* Stop condition (master mode only) */
    45 #define I2C_CON_STT (1 << 0)   /* Start condition (master mode only) */
    46 
     43#define BBB_I2C_CON_XA  (1 << 8)   /* Expand address */
     44#define BBB_I2C_CON_STP (1 << 1)   /* Stop condition (master mode only) */
     45#define BBB_I2C_CON_STT (1 << 0)   /* Start condition (master mode only) */
     46#define BBB_I2C_CON_CLR 0x0  /* Clear configuration register */
    4747/* I2C Status Register (I2C_STAT): */
    4848
    49 #define I2C_STAT_SBD  (1 << 15) /* Single byte data */
    50 #define I2C_STAT_BB (1 << 12) /* Bus busy */
    51 #define I2C_STAT_ROVR (1 << 11) /* Receive overrun */
    52 #define I2C_STAT_XUDF (1 << 10) /* Transmit underflow */
    53 #define I2C_STAT_AAS  (1 << 9)  /* Address as slave */
    54 #define I2C_STAT_GC (1 << 5)
    55 #define I2C_STAT_XRDY (1 << 4)  /* Transmit data ready */
    56 #define I2C_STAT_RRDY (1 << 3)  /* Receive data ready */
    57 #define I2C_STAT_ARDY (1 << 2)  /* Register access ready */
    58 #define I2C_STAT_NACK (1 << 1)  /* No acknowledgment interrupt enable */
    59 #define I2C_STAT_AL (1 << 0)  /* Arbitration lost interrupt enable */
     49#define BBB_I2C_STAT_SBD  (1 << 15) /* Single byte data */
     50#define BBB_I2C_STAT_BB (1 << 12) /* Bus busy */
     51#define BBB_I2C_STAT_ROVR (1 << 11) /* Receive overrun */
     52#define BBB_I2C_STAT_XUDF (1 << 10) /* Transmit underflow */
     53#define BBB_I2C_STAT_AAS  (1 << 9)  /* Address as slave */
     54#define BBB_I2C_STAT_GC (1 << 5)
     55#define BBB_I2C_STAT_XRDY (1 << 4)  /* Transmit data ready */
     56#define BBB_I2C_STAT_RRDY (1 << 3)  /* Receive data ready */
     57#define BBB_I2C_STAT_ARDY (1 << 2)  /* Register access ready */
     58#define BBB_I2C_STAT_NACK (1 << 1)  /* No acknowledgment interrupt enable */
     59#define BBB_I2C_STAT_AL (1 << 0)  /* Arbitration lost interrupt enable */
    6060
    6161/* I2C Interrupt Enable Register (I2C_IE): */
    62 #define I2C_IE_GC_IE  (1 << 5)
    63 #define I2C_IE_XRDY_IE  (1 << 4) /* Transmit data ready interrupt enable */
    64 #define I2C_IE_RRDY_IE  (1 << 3) /* Receive data ready interrupt enable */
    65 #define I2C_IE_ARDY_IE  (1 << 2) /* Register access ready interrupt enable */
    66 #define I2C_IE_NACK_IE  (1 << 1) /* No acknowledgment interrupt enable */
    67 #define I2C_IE_AL_IE  (1 << 0) /* Arbitration lost interrupt enable */
    68 /*
    69  * The equation for the low and high time is
    70  * tlow = scll + scll_trim = (sampling clock * tlow_duty) / speed
    71  * thigh = sclh + sclh_trim = (sampling clock * (1 - tlow_duty)) / speed
    72  *
    73  * If the duty cycle is 50%
    74  *
    75  * tlow = scll + scll_trim = sampling clock / (2 * speed)
    76  * thigh = sclh + sclh_trim = sampling clock / (2 * speed)
    77  *
    78  * In TRM
    79  * scll_trim = 7
    80  * sclh_trim = 5
    81  *
    82  * The linux 2.6.30 kernel uses
    83  * scll_trim = 6
    84  * sclh_trim = 6
    85  *
    86  * These are the trim values for standard and fast speed
    87  */
    88 #ifndef I2C_FASTSPEED_SCLL_TRIM
    89 #define I2C_FASTSPEED_SCLL_TRIM   6
    90 #endif
    91 #ifndef I2C_FASTSPEED_SCLH_TRIM
    92 #define I2C_FASTSPEED_SCLH_TRIM   6
    93 #endif
    94 
    95 /* These are the trim values for high speed */
    96 #ifndef I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM
    97 #define I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM I2C_FASTSPEED_SCLL_TRIM
    98 #endif
    99 #ifndef I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM
    100 #define I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM I2C_FASTSPEED_SCLH_TRIM
    101 #endif
    102 #ifndef I2C_HIGHSPEED_PHASE_TWO_SCLL_TRIM
    103 #define I2C_HIGHSPEED_PHASE_TWO_SCLL_TRIM I2C_FASTSPEED_SCLL_TRIM
    104 #endif
    105 #ifndef I2C_HIGHSPEED_PHASE_TWO_SCLH_TRIM
    106 #define I2C_HIGHSPEED_PHASE_TWO_SCLH_TRIM I2C_FASTSPEED_SCLH_TRIM
    107 #endif
    108 
    109 #define OMAP_I2C_STANDARD 100000
    110 #define OMAP_I2C_FAST_MODE  400000
    111 #define OMAP_I2C_HIGH_SPEED 3400000
    112 
    113 
    114 /* Use the reference value of 96MHz if not explicitly set by the board */
    115 #ifndef I2C_IP_CLK
    116 #define I2C_IP_CLK    SYSTEM_CLOCK_96
    117 #endif
    118 
    119 /*
    120  * The reference minimum clock for high speed is 19.2MHz.
    121  * The linux 2.6.30 kernel uses this value.
    122  * The reference minimum clock for fast mode is 9.6MHz
    123  * The reference minimum clock for standard mode is 4MHz
    124  * In TRM, the value of 12MHz is used.
    125  */
    126 #ifndef I2C_INTERNAL_SAMPLING_CLK
    127 #define I2C_INTERNAL_SAMPLING_CLK 19200000
    128 #endif
    129 
    130 #define I2C_PSC_MAX   0x0f
    131 #define I2C_PSC_MIN   0x00
    132 
    133 
    134 #define DISP_LINE_LEN 128
    135 #define I2C_TIMEOUT 1000
    136 
    137 #define I2C_BUS_MAX 3
    138 
    139 #define I2C_BASE1         (OMAP34XX_CORE_L4_IO_BASE + 0x070000)
    140 
    141 #define I2C_DEFAULT_BASE      I2C_BASE1
    142 
    143 #define I2C_SYSS_RDONE            (1 << 0)  /* Internel reset monitoring */
    144 
    145 #define CONFIG_SYS_I2C_SPEED    100000
    146 #define CONFIG_SYS_I2C_SLAVE    1
    147 
    148 struct i2c {
    149   unsigned short rev;   /* 0x00 */
    150   unsigned short res1;
    151   unsigned short ie;    /* 0x04 */
    152   unsigned short res2;
    153   unsigned short stat;  /* 0x08 */
    154   unsigned short res3;
    155   unsigned short iv;    /* 0x0C */
    156   unsigned short res4;
    157   unsigned short syss;  /* 0x10 */
    158   unsigned short res4a;
    159   unsigned short buf;   /* 0x14 */
    160   unsigned short res5;
    161   unsigned short cnt;   /* 0x18 */
    162   unsigned short res6;
    163   unsigned short data;  /* 0x1C */
    164   unsigned short res7;
    165   unsigned short sysc;  /* 0x20 */
    166   unsigned short res8;
    167   unsigned short con;   /* 0x24 */
    168   unsigned short res9;
    169   unsigned short oa;    /* 0x28 */
    170   unsigned short res10;
    171   unsigned short sa;    /* 0x2C */
    172   unsigned short res11;
    173   unsigned short psc;   /* 0x30 */
    174   unsigned short res12;
    175   unsigned short scll;  /* 0x34 */
    176   unsigned short res13;
    177   unsigned short sclh;  /* 0x38 */
    178   unsigned short res14;
    179   unsigned short systest; /* 0x3c */
    180   unsigned short res15;
    181 };
     62#define BBB_I2C_IE_GC_IE  (1 << 5)
     63#define BBB_I2C_IE_XRDY_IE  (1 << 4) /* Transmit data ready interrupt enable */
     64#define BBB_I2C_IE_RRDY_IE  (1 << 3) /* Receive data ready interrupt enable */
     65#define BBB_I2C_IE_ARDY_IE  (1 << 2) /* Register access ready interrupt enable */
     66#define BBB_I2C_IE_NACK_IE  (1 << 1) /* No acknowledgment interrupt enable */
     67#define BBB_I2C_IE_AL_IE  (1 << 0) /* Arbitration lost interrupt enable */
     68
     69/* I2C SYSC Register (I2C_SYSC): */
     70#define BBB_I2C_SYSC_SRST (1 << 1)
     71
     72#define BBB_I2C_TIMEOUT 1000
     73
     74#define BBB_I2C_SYSS_RDONE            (1 << 0)  /* Internel reset monitoring */
     75
     76#define BBB_CONFIG_SYS_I2C_SPEED    100000
     77#define BBB_CONFIG_SYS_I2C_SLAVE    1
     78#define BBB_I2C_ALL_FLAGS 0x7FFF
     79#define BBB_I2C_ALL_IRQ_FLAGS 0xFFFF
     80
     81#define BBB_I2C_SYSCLK 48000000
     82#define BBB_I2C_INTERNAL_CLK 12000000
     83#define BBB_I2C_SPEED_CLK 100000
     84
     85#define BBB_I2C_IRQ_ERROR \
     86  ( AM335X_I2C_IRQSTATUS_NACK \
     87    | AM335X_I2C_IRQSTATUS_ROVR \
     88    | AM335X_I2C_IRQSTATUS_AL \
     89    | AM335X_I2C_IRQSTATUS_ARDY \
     90    | AM335X_I2C_IRQSTATUS_RRDY \
     91    | AM335X_I2C_IRQSTATUS_XRDY \
     92    | AM335X_I2C_IRQSTATUS_XUDF )
     93
     94#define BBB_I2C_IRQ_USED \
     95  ( AM335X_I2C_IRQSTATUS_ARDY \
     96    | AM335X_I2C_IRQSTATUS_XRDY )
     97
     98#define BBB_I2C_0_BUS_PATH "/dev/i2c-0"
     99#define BBB_I2C_1_BUS_PATH "/dev/i2c-1"
     100#define BBB_I2C_2_BUS_PATH "/dev/i2c-2"
     101
     102#define BBB_I2C0_IRQ 70
     103#define BBB_I2C1_IRQ 71
     104#define BBB_I2C2_IRQ 30
     105
     106#define BBB_MODE2 2
     107#define BBB_MODE3 3
     108
     109typedef enum {
     110  I2C0,
     111  I2C1,
     112  I2C2,
     113  I2C_COUNT
     114} bbb_i2c_id_t;
     115
     116typedef struct i2c_regs {
     117  uint32_t BBB_I2C_REVNB_LO;
     118  uint32_t BBB_I2C_REVNB_HI;
     119  uint32_t dummy1[ 2 ];
     120  uint32_t BBB_I2C_SYSC;
     121  uint32_t dummy2[ 4 ];
     122  uint32_t BBB_I2C_IRQSTATUS_RAW;
     123  uint32_t BBB_I2C_IRQSTATUS;
     124  uint32_t BBB_I2C_IRQENABLE_SET;
     125  uint32_t BBB_I2C_IRQENABLE_CLR;
     126  uint32_t BBB_I2C_WE;
     127  uint32_t BBB_I2C_DMARXENABLE_SET;
     128  uint32_t BBB_I2C_DMATXENABLE_SET;
     129  uint32_t BBB_I2C_DMARXENABLE_CLR;
     130  uint32_t BBB_I2C_DMATXENABLE_CLR;
     131  uint32_t BBB_I2C_DMARXWAKE_EN;
     132  uint32_t BBB_I2C_DMATXWAKE_EN;
     133  uint32_t dummy3[ 16 ];
     134  uint32_t BBB_I2C_SYSS;
     135  uint32_t BBB_I2C_BUF;
     136  uint32_t BBB_I2C_CNT;
     137  uint32_t BBB_I2C_DATA;
     138  uint32_t dummy4;
     139  uint32_t BBB_I2C_CON;
     140  uint32_t BBB_I2C_OA;
     141  uint32_t BBB_I2C_SA;
     142  uint32_t BBB_I2C_PSC;
     143  uint32_t BBB_I2C_SCLL;
     144  uint32_t BBB_I2C_SCLH;
     145  uint32_t BBB_I2C_SYSTEST;
     146  uint32_t BBB_I2C_BUFSTAT;
     147  uint32_t BBB_I2C_OA1;
     148  uint32_t BBB_I2C_OA2;
     149  uint32_t BBB_I2C_OA3;
     150  uint32_t BBB_I2C_ACTOA;
     151  uint32_t BBB_I2C_SBLOCK;
     152} bbb_i2c_regs;
     153
     154typedef struct bbb_i2c_bus {
     155  i2c_bus base;
     156  volatile bbb_i2c_regs *regs;
     157  i2c_msg *msgs;
     158  uint32_t msg_todo;
     159  uint32_t current_msg_todo;
     160  uint8_t *current_msg_byte;
     161  uint32_t current_todo;
     162  bool read;
     163  bool hold;
     164  rtems_id task_id;
     165  rtems_vector_number irq;
     166  uint32_t input_clock;
     167  uint32_t already_transferred;
     168} bbb_i2c_bus;
     169
     170int am335x_i2c_bus_register(
     171  const char         *bus_path,
     172  uintptr_t           register_base,
     173  uint32_t            input_clock,
     174  rtems_vector_number irq
     175);
     176
     177static inline int bbb_register_i2c_0( void )
     178{
     179  return am335x_i2c_bus_register(
     180    BBB_I2C_0_BUS_PATH,
     181    AM335X_I2C0_BASE,
     182    I2C_BUS_CLOCK_DEFAULT,
     183    BBB_I2C0_IRQ
     184  );
     185}
     186
     187static inline int bbb_register_i2c_1( void )
     188{
     189  return am335x_i2c_bus_register(
     190    BBB_I2C_1_BUS_PATH,
     191    AM335X_I2C1_BASE,
     192    I2C_BUS_CLOCK_DEFAULT,
     193    BBB_I2C1_IRQ
     194  );
     195}
     196
     197static inline int bbb_register_i2c_2( void )
     198{
     199  return am335x_i2c_bus_register(
     200    BBB_I2C_2_BUS_PATH,
     201    AM335X_I2C2_BASE,
     202    I2C_BUS_CLOCK_DEFAULT,
     203    BBB_I2C2_IRQ
     204  );
     205}
    182206
    183207#ifdef __cplusplus

  • c/src/lib/libcpu/arm/shared/include/am335x.h

    r7741545b r8f550d2  
    564564
    565565
     566/* I2C registers */
     567#define AM335X_I2C0_BASE 0x44e0b000
     568    /* I2C0 base address */
     569#define AM335X_I2C1_BASE 0x4802a000
     570    /* I2C1 base address */
     571#define AM335X_I2C2_BASE 0x4819c000
     572    /* I2C2 base address */
     573#define AM335X_I2C_REVNB_LO        0x00
     574    /* Module Revision Register (low bytes) */
     575#define AM335X_I2C_REVNB_HI        0x04
     576    /* Module Revision Register (high bytes) */
     577#define AM335X_I2C_SYSC            0x10
     578    /* System Configuration Register */
     579#define AM335X_I2C_IRQSTATUS_RAW   0x24
     580    /* I2C Status Raw Register */
     581#define AM335X_I2C_IRQSTATUS       0x28
     582    /* I2C Status Register */
     583#define AM335X_I2C_IRQENABLE_SET   0x2c
     584    /* I2C Interrupt Enable Set Register */
     585#define AM335X_I2C_IRQENABLE_CLR   0x30
     586    /* I2C Interrupt Enable Clear Register */
     587#define AM335X_I2C_WE              0x34
     588    /* I2C Wakeup Enable Register */
     589#define AM335X_I2C_DMARXENABLE_SET 0x38
     590    /* Receive DMA Enable Set Register */
     591#define AM335X_I2C_DMATXENABLE_SET 0x3c
     592    /* Transmit DMA Enable Set Register */
     593#define AM335X_I2C_DMARXENABLE_CLR 0x40
     594    /* Receive DMA Enable Clear Register */
     595#define AM335X_I2C_DMATXENABLE_CLR 0x44
     596    /* Transmit DMA Enable Clear Register */
     597#define AM335X_I2C_DMARXWAKE_EN    0x48
     598    /* Receive DMA Wakeup Register */
     599#define AM335X_I2C_DMATXWAKE_EN    0x4c
     600    /* Transmit DMA Wakeup Register */
     601#define AM335X_I2C_SYSS            0x90
     602    /* System Status Register */
     603#define AM335X_I2C_BUF             0x94
     604    /* Buffer Configuration Register */
     605#define AM335X_I2C_CNT             0x98
     606    /* Data Counter Register */
     607#define AM335X_I2C_DATA            0x9c
     608    /* Data Access Register */
     609#define AM335X_I2C_CON             0xa4
     610    /* I2C Configuration Register */
     611#define AM335X_I2C_OA              0xa8
     612    /* I2C Own Address Register */
     613#define AM335X_I2C_SA              0xac
     614    /* I2C Slave Address Register */
     615#define AM335X_I2C_PSC             0xb0
     616    /* I2C Clock Prescaler Register */
     617#define AM335X_I2C_SCLL            0xb4
     618    /* I2C SCL Low Time Register */
     619#define AM335X_I2C_SCLH            0xb8
     620    /* I2C SCL High Time Register */
     621#define AM335X_I2C_SYSTEST         0xbc
     622    /* System Test Register */
     623#define AM335X_I2C_BUFSTAT         0xc0
     624    /* I2C Buffer Status Register */
     625#define AM335X_I2C_OA1             0xc4
     626    /* I2C Own Address 1 Register */
     627#define AM335X_I2C_OA2             0xc8
     628    /* I2C Own Address 2 Register */
     629#define AM335X_I2C_OA3             0xcc
     630    /* I2C Own Address 3 Register */
     631#define AM335X_I2C_ACTOA           0xd0
     632    /* Active Own Address Register */
     633#define AM335X_I2C_SBLOCK          0xd4
     634    /* I2C Clock Blocking Enable Register */
     635
     636#define AM335X_CM_PER_L4LS_CLKSTCTRL  (0x0)
     637#define AM335X_CM_PER_L4LS_CLKSTCTRL_CLKTRCTRL_SW_WKUP  (0x2u)
     638#define AM335X_CM_PER_L4LS_CLKSTCTRL_CLKTRCTRL  (0x00000003u)
     639#define AM335X_CM_PER_L4LS_CLKCTRL  (0x60)
     640#define AM335X_CM_PER_L4LS_CLKCTRL_MODULEMODE_ENABLE  (0x2u)
     641#define AM335X_CM_PER_L4LS_CLKCTRL_MODULEMODE  (0x00000003u)
     642#define AM335X_CM_PER_I2C1_CLKCTRL  (0x48)
     643#define AM335X_CM_PER_I2C1_CLKCTRL_MODULEMODE_ENABLE  (0x2u)
     644#define AM335X_CM_PER_I2C1_CLKCTRL_MODULEMODE  (0x00000003u)
     645#define AM335X_CM_PER_I2C2_CLKCTRL (0x44)
     646#define AM335X_CM_PER_I2C2_CLKCTRL_MODULEMODE_ENABLE  (0x2u)
     647#define AM335X_CM_PER_I2C2_CLKCTRL_MODULEMODE  (0x00000003u)
     648#define AM335X_CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_L4LS_GCLK (0x00000100u)
     649#define AM335X_CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_I2C_FCLK (0x01000000u)
     650#define AM335X_CM_PER_I2C1_CLKCTRL_MODULEMODE   (0x00000003u)
     651#define AM335X_I2C_CON_XSA  (0x00000100u)
     652#define AM335X_I2C_CFG_10BIT_SLAVE_ADDR  AM335X_I2C_CON_XSA
     653#define AM335X_I2C_CON_XSA_SHIFT  (0x00000008u)
     654#define AM335X_I2C_CFG_7BIT_SLAVE_ADDR  (0 << AM335X_I2C_CON_XSA_SHIFT)
     655#define AM335X_I2C_CON_I2C_EN   (0x00008000u)
     656#define AM335X_I2C_CON_TRX   (0x00000200u)
     657#define AM335X_I2C_CON_MST   (0x00000400u)
     658#define AM335X_I2C_CON_STB   (0x00000800u)
     659#define AM335X_I2C_SYSC_AUTOIDLE   (0x00000001u)
     660
     661/*I2C0 module clock registers*/
     662
     663#define AM335X_CM_WKUP_CONTROL_CLKCTRL   (0x4)
     664#define AM335X_CM_WKUP_CLKSTCTRL   (0x0)
     665#define AM335X_CM_WKUP_I2C0_CLKCTRL   (0xb8)
     666#define AM335X_CM_WKUP_I2C0_CLKCTRL_MODULEMODE_ENABLE   (0x2u)
     667#define AM335X_CM_WKUP_I2C0_CLKCTRL_MODULEMODE   (0x00000003u)
     668#define AM335X_CM_WKUP_CONTROL_CLKCTRL_IDLEST_FUNC   (0x0u)
     669#define AM335X_CM_WKUP_CONTROL_CLKCTRL_IDLEST_SHIFT   (0x00000010u)
     670#define AM335X_CM_WKUP_CONTROL_CLKCTRL_IDLEST   (0x00030000u)
     671#define AM335X_CM_WKUP_CLKSTCTRL_CLKACTIVITY_I2C0_GFCLK   (0x00000800u)
     672#define AM335X_CM_WKUP_I2C0_CLKCTRL_IDLEST_FUNC   (0x0u)
     673#define AM335X_CM_WKUP_I2C0_CLKCTRL_IDLEST_SHIFT   (0x00000010u)
     674#define AM335X_CM_WKUP_I2C0_CLKCTRL_IDLEST   (0x00030000u)
     675#define AM335X_SOC_CM_WKUP_REGS                     (AM335X_CM_PER_ADDR + 0x400)
     676
     677/* I2C status Register */
     678#define AM335X_I2C_IRQSTATUS_NACK (1 << 1)
     679#define AM335X_I2C_IRQSTATUS_ROVR (1 << 11)
     680#define AM335X_I2C_IRQSTATUS_AL   (1<<0)
     681#define AM335X_I2C_IRQSTATUS_ARDY (1 << 2)
     682#define AM335X_I2C_IRQSTATUS_RRDY (1 << 3)
     683#define AM335X_I2C_IRQSTATUS_XRDY (1 << 4)
     684#define AM335X_I2C_IRQSTATUS_XUDF (1 << 10)
     685#define AM335X_I2C_BUF_TXFIFO_CLR   (0x00000040u)
     686#define AM335X_I2C_BUF_RXFIFO_CLR   (0x00004000u)
     687#define AM335X_I2C_IRQSTATUS_AAS  (1 << 9)
     688#define AM335X_I2C_IRQSTATUS_BF  (1 << 8)
     689#define AM335X_I2C_IRQSTATUS_STC  (1 << 6)
     690#define AM335X_I2C_IRQSTATUS_GC (1 << 5)
     691#define AM335X_I2C_IRQSTATUS_XDR (1 << 14)
     692#define AM335X_I2C_IRQSTATUS_RDR (1 << 13)
     693
     694#define AM335X_I2C_INT_RECV_READY AM335X_I2C_IRQSTATUS_RRDY
     695#define AM335X_I2C_CON_STOP  (0x00000002u)
     696#define AM335X_I2C_CON_START (0x00000001u)
     697#define AM335X_I2C_CFG_MST_RX AM335X_I2C_CON_MST
     698#define AM335X_I2C_CFG_MST_TX  (AM335X_I2C_CON_TRX | AM335X_I2C_CON_MST)
     699#define AM335X_I2C_IRQSTATUS_RAW_BB   (0x00001000u)
     700#define AM335X_CM_PER_OCPWP_L3_CLKSTCTRL_CLKACTIVITY_OCPWP_L4_GCLK (0x00000020u)
     701#define AM335X_I2C_INT_STOP_CONDITION AM335X_I2C_IRQSTATUS_BF
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